IDTQS5917T-70TQ8 [IDT]
PLL Based Clock Driver, 5917 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, QSOP-28;
| 型号： | IDTQS5917T-70TQ8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 5917 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, QSOP-28 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
QS5917T
INTEGRATED LOOP FILTER
FEATURES:
DESCRIPTION
• 5V operation
The QS5917T Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight
outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design
insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T
includes an internal RC filter which provides excellent jitter characteris-
tics and eliminates the need for external components. In addition, TTL
level outputs reduce clock signal noise. Various combinations of feed-
back and a divide-by-2 in the VCO path allow applications to be custom-
ized for linear VCO operation over a wide range of input SYNC fre-
quencies. The VCO can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5917T is designed for use in
high-performance workstations, multi-board computers, networking hardware,
and mainframe systems. Several can be used in parallel or scattered
throughout a system for guaranteed low skew, system-wide clock distri-
bution networks.
• 2xQ output, Q/2 output, Q output
• Outputs tri-state while RST low
• Internal loop filter RC network
• Low noise TTL level outputs
• < 500ps output skew, Q0-Q4
• PLL disable feature for low frequency testing
• Balanced Drive Outputs ± 24mA
• 132MHz maximum frequency (2xQ output)
• Functional equivalent to Motorola MC88915
• ESD > 2000V
• Latch-up > –300mA
• Available in QSOP and PLCC packages
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONALBLOCKDIAGRAM
REF_SEL
FEEDBACK
PLL_EN
FREQ_SEL
LOCK
0
1
SYNC0
SYNC1
0
1
1
0
PHASE
DETECTOR
LOOP
FILTER
VCO
/2
RST
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q5
Q/2
Q4
Q3
Q2
Q1
Q0
2xQ
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-5227/4
QS5917T
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
Q4
GND
Q5
VDD
VDD
2xQ
Q/2
4
3
2
1
28 27 26
25 Q/2
FEEDBACK
REF_SEL
SYNC0
AVDD
5
RST
GND
24
23
22
21
20
19
FEEDBACK
REF_SEL
SYNC0
GND
Q3
6
5
6
7
8
9
Q3
7
VDD
Q2
VDD
Q2
8
AVDD
NC
NC
9
GND
10
11
GND
LOCK
AGND
LOCK
PLL_EN
GND
10
11
12
13
14
AGND
SYNC1
SYNC1
12 13 14 15 16 17 18
17
16
15
FREQ_SEL
GND
Q1
VDD
Q0
PLCC
TOP VIEW
QSOP
TOP VIEW
ABSOLUTEMAXIMUMRATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz, VIN = 0V)
Symbol
Rating
Max
–0.5 to +7
–0.5 to +7
–3
Unit
V
QSOP
PLCC
Supply Voltage to Ground
DC Input Voltage VIN
V
Parameter
CIN
Typ.
Max.
Typ.
Max.
6
Unit
pF
AC Input Voltage (pulse width ≤ 20ns)
Maximum Power Dissipation (TA = 85°C)
Storage Temperature Range
V
3
7
4
9
4
8
1.2
W
°C
COUT
10
pF
TSTG
–65 to +150
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2
QS5917T
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
Pin Names
I/O
Description
SYNC0
I
I
I
I
I
Reference clock input
Referenceclockinput
SYNC1
REF_SEL
FREQ_SEL
FEEDBACK
Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0.
VCOfrequencyselect. ForchoosingoptimalVCOoperatingfrequencydependingoninputfrequency.
PLLfeedbackinputwhichisconnectedtoauserselectedoutputpin.Externalfeedbackprovidesflexibilityfordifferentoutputfrequency
relationships.SeetheFrequencySelectionTableformoreinformation.
Q0 -Q4
Q5
O
O
O
O
O
I
Clockoutputs
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
PLLlockindicationsignal.1indicatespositivelock.0indicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtotheinputs.
2xQ
Q/2
LOCK
RST
Asynchronousreset.Resetsalloutputregisters.When0,alloutputsareheldinatri-statedcondition.When1,outputsareenabled(normal
operation).
PLL_EN
N C
I
PLLenable. When1, PLLisenabled(normaloperation). When0, PLLisdisabled(fortestingpurposes).
NoConnection
—
OUTPUTFREQUENCYSPECIFICATIONS
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5%
Symbol
F2XQ
FQ
Description
–70
70
–100
100
50
–132
132
66
Units
MHz
MHz
MHz
Max Frequency, 2xQ output
Max Frequency, Q0 - Q4, Q5 outputs
Max Frequency, Q/2output
35
FQ/2
17.5
25
33
3
QS5917T
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
FREQUENCYSELECTIONTABLE
SYNC (MHz)
Output Used for
(allowable range)
Min.
OutputFrequencyRelationships
FREQ_SEL
Feedback
Q/2
Max
Q/2
Q5
Q Outputs
SYNC X 2
SYNC
2XQ
1
1
1
1
0
0
0
14
28
28
56
7
F2XQ / 4
F2XQ / 2
F2XQ / 2
SYNC
– SYNC X 2
– SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
Q0 -Q4
Q5
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
(1)
2xQ
F2XQ
– SYNC / 2
– SYNC X 2
– SYNC
Q/2
F2XQ / 8
F2XQ / 4
F2XQ / 4
SYNC X 4
SYNC X 2
– SYNC X 2
Q0 -Q4
Q5
14
14
SYNC / 2
– SYNC / 2
SYNC
– SYNC
0
2xQ
28
F2XQ / 2
SYNC / 4
– SYNC / 2
SYNC / 2
SYNC
NOTE:
1. For the –132 speed grade, maximum input frequency is restricted to 100MHz.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5%
Symbol
Parameter
Test Conditions
Guaranteed Logic HIGH level
Min.
Typ.
Max.
Unit
VIH
Input HIGH Voltage Level
2
—
—
V
VIL
Input LOW Voltage Level
Output HIGH Voltage
Guaranteed Logic LOW level
VDD = Min., IOH = −24mA (1)
VDD = Min., IOH = −100μA
VDD = Min., IOL = 24mA (1)
VDD = Min., IOL = 100μA
—
2.4
3
—
—
—
—
—
—
—
0.9
—
V
V
VOH
—
VOL
OutputLOWVoltage
—
—
—
—
0.55
0.2
±5
±5
V
IOZ
IIN
OutputLeakageCurrent
InputLeakageCurrent
VOUT = VDD or GND, VDD = Max.
VIN = AVDD or GND, AVDD = Max.
μA
μA
NOTE:
1. IOL and IOH are 12mA and –12mA, respectively, for the LOCK output.
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
VDD = Max., VIN = 3.4V
VDD = Max
Typ.
Max.
1.5
Unit
ΔICC
Input Power Supply Current per TTL Input HIGH (2)
0.4
—
mA
ICCD
Dynamic Power Supply Current
0.4
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. This specification does not apply to the PLL_EN input.
4
QS5917T
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
INPUTTIMINGREQUIREMENTS
Symbol
tR,tF
FI
Description
Min.
—
Max.
3
Unit
ns
Maximum input rise and fall times, 0.8V to 2V
(1)
Input Clock Frequency, SYNC0, SYNC1
14
F2XQ
—
MHz
ns
tPWC
DH
Input clock pulse, HIGH or LOW
Duty cycle, SYNC0, SYNC1
2
25
75
%
NOTE:
1. The FI specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations.
SWITCHINGCHARACTERISTICS(1)
Symbol
Parameter
Min.
Max.
Unit
tSKR
Output Skew Between Rising Edges, Q0-Q4 and Q/2 (1)
—
350
ps
tSKF
tSKALL
tPW
Output Skew Between Falling Edges, Q0-Q4 (1)
Output Skew, All Outputs (1)
—
350
ps
ps
ns
ns
ns
ps
ps
ms
ns
—
TCY/2−0.65
TCY/2 −0.5
—
500
Pulse Width, Q5, 2xQ outputs
TCY/2 + 0.65
tPW
Pulse Width, Q0-Q4, Q/2outputs (1)
Cycle-to-Cycle Jitter, 33MHz (3)
TCY/2 + 0.5
tJ
0.25
400
400
10
tPD
SYNC Input to Feedback Delay, 28MHz
SYNC Input to Feedback Delay, 33MHz, 50Ω to 1.5V
SYNC to Phase Lock
−100
−100
—
tPD
tLOCK
tPZH
tPZL
Output Enable Time, RST LOW to HIGH (2)
0
7
tPHZ
tPLZ
Output Disable Time, RST HIGH to LOW (2)
0
6
ns
ns
tR,tF
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
NOTES:
1. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
2. Measured in open loop mode PLL_EN = 0.
3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information
on proper FREQ_SEL level for specified input frequencies.
5
QS5917T
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
TESTLOAD
VDD
300Ω
160Ω
7.0V
OUTPUT
OUTPUT
20pF
300Ω
68Ω
30pF
TEST CIRCUIT 1
TEST CIRCUIT 2
TEST CIRCUIT 2 is used for output enable/disable parameters.
TEST CIRCUIT 1 is used for all other timing parameters.
PLLOPERATION
ThePhaseLockedLoop(PLL)circuitincludedintheQS5917Tprovides PLLcircuit is to provide an effective zero propagation delay between the
for replication of incoming SYNC clock signals. Any manipulation of that outputandinputsignals. Infact, addingdelaycircuitsinthefeedbackpath,
signal, such as frequency multiplying or inversion is performed by digital ‘propagation delay’ can even be negative! A simplified schematic of the
logic following the PLL (see the block diagram). The key advantage of the QS5917T PLL circuit is shown below.
SIMPLIFIEDDIAGRAMOFQS5917TFEEDBACK
2xQ
Q
Q/2
Q
INPUT
VCO
/2
/2
PHASE
DETECTOR
Thephasedifferencebetweentheoutputandtheinputfrequenciesfeeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilizeatthesamefrequencyastheinput. Hence, thisisatruenegative
feedbackclosedloopsystem.Inmostapplications,theoutputwilloptimally
havezerophaseshiftwithrespecttotheinput.Infact,theinternalloopfilter
on the QS5917T typically provides within 150ps of phase shift between
inputandoutput.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
beadvancedbytheamountofdelayinthefeedbackpath. Allotheroutputs
will retain their proper relationships to that output.
6
QS5917T
LOWSKEWCMOSPLLCLOCKDRIVERWITHINTEGRATEDLOOPFILTER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
QS
X
XXXX
XX
X
Process
Speed
Device Type
Package
Industrial (-40°C to +85°C)
Blank
Q
QG
J
Quarter Size Outline Package
QSOP - Green
Plastic Leaded Chip Carrier
PLCC - Green
JG
-70T
70MHz Max. Frequency
-100T 100MHz Max. Frequency
-132T 132MHz Max. Frequency
Low Skew CMOS PLL Clock Driver with Integrated
Loop Filter
5917T
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
logichelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
7
相关型号：
IDTQS5930-50TQ
PLL Based Clock Driver, 5930 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
IDTQS5LV919-100J
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28
IDT
IDTQS5LV919-133J
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28
IDT
IDTQS5LV919-133Q
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, QSOP-28
IDT
IDTQS5LV919-160Q
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, QSOP-28
IDT
IDTQS5LV919-55J
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28
IDT
IDTQS5LV919-55Q
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PDSO28, QSOP-28
IDT
IDTQS5LV919-70J
PLL Based Clock Driver, 5LV Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28
IDT
IDTQS5LV931-50Q8
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
IDTQS5LV931-66Q
PLL Based Clock Driver, 5LV Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
IDTQS5LV931-66Q8
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明