MK3771-17ATR [IDT]
Clock Generator, 108MHz, CMOS, PDSO28, QSOP-28;
| 型号： | MK3771-17ATR |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 108MHz, CMOS, PDSO28, QSOP-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总4页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK3771-17
VCXO and HDTV Set-Top Clock Source
Description
Features
The MK3771-17 is a low cost, low jitter, high
• MK3771-17A is a drop-in replacement for the earlier
performance VCXO and clock synthesizer designed
for set-top boxes and HDTV receivers. The on-chip
Voltage Controlled Crystal Oscillator accepts a 0 to 3.3
V input voltage to cause the output clocks to vary by
±100 ppm (R verstion) or ±115 (A version). Using ICS’s
patented VCXO and analog Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive
13.5 MHz crystal input to produce multiple output
clocks including selectable BCLK, a selectable audio
clock, two communications clocks, a 13.5 MHz clock,
and three 27 MHz clocks. All clocks are frequency
locked to the 27.00 MHz output (and to each other)
with zero ppm error, so any output can be used as the
VCXO output.
MK3771-17R device
• Packaged in 28 pin SSOP (QSOP)
• HDTV frequencies of 74.25 and 74.175824 MHz
• On-chip patented VCXO with pull range
of 200ppm (minimum)
• VCXO tuning voltage of 0 to 3.3 V
• Supports Ethernet with 20 and 25 MHz clocks
• Modem clocks of 11.0592 and 24.576 MHz option
• Audio clocks support 32 kHz, 44.1 kHz, 48 kHz
and 96 kHz sampling rates
• Zero ppm synthesis error in all clocks (all exactly
track 27MHz VCXO)
• Uses an inexpensive 13.5 MHz crystal
• Full CMOS output swings with 12 mA output
drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 3.3 V ±5% operating supply
Block Diagram
3
Output
AS2:0
Audio Clock
Buffer
PLL
Clock
Synthesis
Circuitry
2
Output
Buffer
BS1, BS0
BCLK
Output
Buffer
CCLK1
CCLK2
CS
Output
Buffer
VIN
X1
Voltage
13.5 MHz
pullable
crystal
108 MHz
or 27 MHz
Output
Buffers
Controlled
Crystal
x8
PLL
Oscillator
Divide
Logic
Output
Buffer
54 MHz
or 27 MHz
X2
VS
Output
Buffer
27 MHz
Output
Buffer
13.5 MHz
or 27 MHz
MDS 3771-17 B
1
Revision 091701
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • 408) 295-9800tel • www.icst.com
MK3771-17
VCXO and HDTV Set-Top Clock Source
Pin Assignment
Audio Clock (MHz)
B and C Clocks (MHz)
AS2AS1AS0 ACLK
BS1BS0 CS BCLK
CCLK1
20
CCLK2
25
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AS1
AS0
BS0
X2
X1
VDD
VDD
VIN
VDD
VDD
CS
GND
GND
BCLK
VS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.192
11.2896
12.288
16.9344
16.384
22.5792
18.432
24.576
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
M
1
0
M
1
74.175
74.175 11.0592 24.576
VCLK2
VCLK1
GND
VCLK4
VDD
AS2
GND
GND
0
74.25
74.25
5.06
5.06
10.12
10.12
48
20
11.0592 24.576
20 25
11.0592 24.576
20 25
11.0592 24.576
25
0
M
M
M
M
1
9
10
11
12
13
14
20
25
24
VCLK3
CCLK1
BS1
1
48
7.3728
1
48
11.0592 24.576
CCLK2
ACLK
1
14.318
14.318
20
25
1
7.3728
28.636
VCXO Clocks (MHz)
1
14.318 11.0592 24.576
VS VCLK1 VCLK2 VCLK3 VCLK4
0 = connect directly to GND
M = leave unconnected (floating)
1 = connect directly to VDDIO
X = don’t care
0
M
1
27
27
27
27
54
27
27
13.5
27
108
108
27
Pin Descriptions
Number
Name Type Description
1
BS0
X2
I
B Clock Select 0. Selects BCLK frequency. See table above. Internal pull-up.
2
XO Crystal connection. Connect to a pullable 13.5 MHz crystal.
XI Crystal connection. Connect to a pullable 13.5 MHz crystal.
3
X1
4, 5, 7, 8, 22
VDD
P
Connect to +3.3V.
6
VIN
VI Analog control voltage for VCXO. Pulls outputs ±100 ppm by varying from 0 to 3.3V.
TI Communications Clock Select. Selects CCLK 1 and 2 per table above. Internal pull-up.
9
CS
10, 11,19,20,24
GND
BCLK
VS
P
Connect to ground.
12
13
14
15
16
17
18
21
23
25
26
27
28
O
B Clock output. Determined by status of BS1, BS0.
TI VCXO Clock Select. Selects frequencies on VCLK1-VCLK4 per table above.
ACLK
CCLK2
BS1
O
O
Audio Clock output. Determined by status of AS2:0 per table above.
Communications Clock Output 2. Determined by status of CS per table above.
TI B Clock Select 1. Selects BCLK frequency. See table above.
CCLK1
VCLK3
AS2
O
O
I
Communications Clock output 1. Determined by status of CS per table above.
VCXO Clock output 3. Can be either 27 or 13.5 MHz per table above.
Audio Clock Select pin 2. Selects Audio clock on pin 14 per table above. Internal pull-up.
VCXO Clock output 4. Can be either 27 or 108 MHz per table above.
VCLK4
VCLK1
VCLK2
AS0
O
O
O
I
VCXO Clock output pin 1. Always 27 MHz.
VCXO Clock output pin 2. Can be either 27 or 54 MHz per table above.
Audio Clock Select pin 0. Selects Audio clock on pin 14. See table above. Internal pull-up.
Audio Clock Select pin 1. Selects Audio clock on pin 14. See table above. Internal pull-up.
AS1
I
Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections
MDS 3771-17 B
2
Revision 091701
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • 408) 295-9800tel • www.icst.com
MK3771-17
VCXO and HDTV Set-Top Clock Source
Electrical Specifications
Parameter
Conditions
Minimum Typical Maximum Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
VDD+0.5
70
V
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Referenced to GND
-0.5
0
V
°C
°C
°C
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
3.15
2
3.30
3.45
0.8
V
V
Input High Voltage, VIH, except TI pins
Input Low Voltage, VIL, except TI pins
Input High Voltage, VIH, all TI pins
V
VDD-0.5
2.4
V
Input Low Voltage, VIL, all TI pins
0.5
V
Output High Voltage, VOH
IOH=-12mA
IOL=12mA
IOH=-8mA
V
Output Low Voltage, VOL
0.4
V
Output High Voltage, VOH, CMOS level
VDD-0.4
V
Operating Supply Current, IDD, MK3771-17R No Load, note 2
Operating Supply Current, IDD, MK3771-17A No Load, note 2
28
37
±50
5
mA
mA
mA
pF
ppm
V
Short Circuit Current
Each output
Input Capacitance
Frequency synthesis error
VIN, VCXO control voltage
All clocks
0
0
3.3
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequency
13.500000
MHz
ns
Output Clock Rise Time
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
1.5
1.5
60
Output Clock Fall Time
ns
Output Clock Duty Cycle
40
%
Maximum Absolute Jitter, short term
VCXO Gain, MK3771-17R
±250
100
ps
VIN = VDD/2 ± 1V
VIN = VDD/2 ± 1V
0V £ VIN £ 3.3 V
0V £ VIN £ 3.3 V
ppm/V
ppm/V
ppm
ppm
VCXO Gain, MK3771-17A
120
Crystal pullability, note 3, MK3771-17R
Crystal pullability, note 3, MK3771-17A
±100
±115
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device.
Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest MHz.
3. With a pullable crystal that conforms to ICS’ specifications
External Components
The MK3771-17 requires a minimum number of external components for proper operation. Use a low inductance
ground plane, connect all GNDs to this. Connect 0.01µF decoupling caps on pins 4, 5, 7, 8 and 22 directly to the
ground plane, as close to the MK3771-17 as possible. A series termination resistor of 33 W may be used for each clock
output. The 13.500 MHz crystal must be connected as close to the chip as possible. The crystal should be a parallel
mode, pullable, with load capacitance of 14 pF. See page 4 for crystal specifications. Please follow Application Note
MAN05 for pullable crystal layout.
MDS 3771-17 B
3
Revision 091701
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • 408) 295-9800tel • www.icst.com
MK3771-17
VCXO and HDTV Set-Top Clock Source
Pullable Crystal Specifications:
Frequency
Correlation (load) Capacitance
C0/C1
13.500000 MHz
14 pF
240 max
ESR
35 W max
0 to 70 °C
±20 ppm
±50 ppm
Operating Temperature
Initial Accuracy
Temperature plus Aging Stability
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
28 pin SSOP
Inches
Millimeters
Min Max
0.053 0.069 1.35 1.75
Symbol Min
Max
E1
E
A
A1
b
0.004 0.010 0.102 0.254
0.008 0.012 0.203 0.305
0.007 0.010 0.191 0.254
0.386 0.394 9.804 10.008
c
D
e
.025 BSC
0.635 BSC
E
0.228 0.244 5.791 6.198
0.150 0.157 3.810 3.988
0.016 0.050 0.406 1.270
E1
L
D
A
A1
c
b
L
e
Ordering Information
Part/Order Number
MK3771-17R
Marking
Shipping packaging
tubes
Package
Temperature
0-70 °C
MK3771-17R
MK3771-17R
MK3771-17A
MK3771-17A
28 pin SSOP (QSOP)
28 pin SSOP (QSOP)
28 pin SSOP (QSOP)
28 pin SSOP (QSOP)
MK3771-17RTR
MK3771-17A
tape and reel
tubes
0-70 °C
0-70 °C
MK3771-17ATR
tape and reel
0-70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 3771-17 B
4
Revision 091701
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126 • 408) 295-9800tel • www.icst.com
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