MPC93R52FAR2 [IDT]
PLL Based Clock Driver, 93R Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32;
| 型号： | MPC93R52FAR2 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 93R Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总11页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC93R52/D
Rev 2, 04/2003
Freescale Semiconductor, Inc.
ꢆ
ꢋ
ꢇ
ꢒ
ꢆ
ꢐ
ꢈ
ꢕ
ꢉ
ꢊ
ꢉ
ꢎ
ꢉ
ꢘ
ꢄ
ꢎ
ꢈ
ꢋ
ꢀ
ꢐ
ꢁ
ꢏ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢑ
ꢎ
ꢒ
ꢓ
ꢔ
ꢀꢚ ꢋꢛ ꢆꢃꢜ ꢝ
ꢖ
ꢗ
ꢏ
ꢓ
ꢙ
The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output fre-
quencies up to 240 MHz and output skews lower than 200 ps the device
meets the needs of most demanding clock applications.
2
LOW VOLTAGE
3.3V LVCMOS 1:11
CLOCK GENERATOR
Features
• Configurable 11 outputs LVCMOS PLL clock generator
• Fully integrated PLL
• Wide range of output clock frequency of 16.67 MHz to 240 MHz
• Multiplication of the input reference clock frequency by 3, 2, 1, 3B2,
2B3, 1B3 and 1B2
• 3.3V LVCMOS compatible
• Maximum output skew of 200 ps
• Supports zero–delay applications
• Designed for high–performance telecom, networking and computing
applications
• 32 lead LQFP package
• Ambient Temperature Range – 0°C to +70°C
• Pin and function compatible to the MPC952
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
Functional Description
The MPC93R52 is a fully 3.3V compatible PLL clock generator and
clock driver. The device has the capability to generate output clock sig-
nals of 16.67 to 240 MHz from external clock sources. The internal PLL
optimized for its frequency range and does not require external look filter
components. One output of the MPC93R52 has to be connected to the
PLL feedback input FB_IN to close the external PLL feedback path. The
output divider of this output setting determines the PLL frequency multi-
plication factor. This multiplication factor, F_RANGE and the reference
clock frequency must be selected to situate the VCO in its specified lock
range. The frequency of the clock outputs can be configured individually
for all three output banks by the FSELx pins supporting systems with
different but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is package in a 32 ld LQFP.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
139
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
ꢃ ꢩꢦ ꢳ ꢋ
ꢁꢁ ꢒꢖ
ꢀ ꢁꢕ
ꢂ ꢋꢉ
1
0
1
0
÷2
÷6
÷4
÷2
1
0
ꢂ ꢋꢊ
ꢂ ꢋꢄ
ꢁ ꢁ ꢒ ꢖ
ꢍ ꢃꢎꢗ ꢇ
ꢏꢢ ꢬ
ꢍꢃ
PLL
ꢂ ꢋꢅ
ꢂ ꢋꢌ
ꢄ
ꢉ
ꢉ
ꢸ
ꢌ
ꢛ
ꢉ
ꢓ
ꢺ
ꢻ
2
ꢝ
ꢒ
ꢒ
ꢎ
ꢐ
ꢇ
ꢃ
ꢩ
ꢦ
ꢳ
ꢃ
ꢂ
ꢃ
ꢉ
1
0
ꢍ
ꢎ
ꢏ
ꢋ
ꢇ
ꢆ
ꢐ
ꢂ ꢃꢊ
ꢂ ꢃꢄ
ꢂ ꢃꢅ
ꢍ ꢑꢐꢒꢋ
ꢍ ꢑꢐꢒꢃ
ꢃ ꢩꢦ ꢳ ꢁ
1
0
ꢂ ꢁ ꢉ
ꢂ ꢁ ꢊ
ꢍ ꢑꢐꢒꢁ
ꢓꢏ ꢔ ꢕ ꢐ
ꢝ ꢕꢷ ꢐꢏ ꢸꢕ ꢇ ꢏ ꢐꢑꢐ ꢹ
ꢴ
ꢩ
ꢫ
ꢫ
ꢟ
ꢦ
ꢯ
ꢨ
ꢞ
ꢡ
ꢢ
ꢠ
ꢟ
ꢠ
ꢞ
ꢤ
ꢡ
ꢠ
ꢭ
ꢩ
ꢵ
ꢢ
ꢩ
ꢵ
ꢩ
ꢫ
ꢨ
ꢢ
ꢤ
ꢬ
ꢄ
ꢘ
ꢳ
W
ꢶ
Figure 1. MPC93R52 Logic Diagram
ꢄ
ꢌ
ꢄ
ꢅ
ꢄ
ꢄ
ꢄ
ꢊ
ꢄ
ꢉ
ꢊ
ꢜ
ꢊ
ꢛ
ꢊ
ꢚ
ꢄꢘ
ꢄꢙ
ꢄꢚ
ꢄꢛ
ꢄꢜ
ꢅꢉ
ꢅꢊ
ꢅꢄ
ꢊ
ꢙ
ꢀ
ꢁ
ꢁ
ꢀ ꢁꢁ
ꢂ ꢃꢄ
ꢂ ꢃꢅ
ꢆ ꢇꢈ
ꢆ ꢇꢈ
ꢂ ꢁꢉ
ꢂ ꢁꢊ
ꢀ ꢁꢁ
ꢊ ꢘ
ꢊ ꢌ
ꢊ ꢅ
ꢊ ꢄ
ꢊ ꢊ
ꢊ ꢉ
ꢜ
ꢂ ꢋ ꢄ
ꢂ
ꢋ
ꢊ
ꢆ ꢇꢈ
ꢂ ꢋ ꢉ
MPC93R52
ꢀ ꢁꢁ
ꢀ ꢁꢁꢋ
ꢝ ꢒꢒ ꢎ ꢐꢇ
ꢊ
ꢄ
ꢅ
ꢌ
ꢘ
ꢙ
ꢚ
ꢛ
ꢗꢞ ꢟꢠ ꢡꢢ ꢣꢤꢥ ꢥꢢ ꢦꢧꢢ ꢧ ꢞ ꢤ ꢨꢠꢢ ꢩꢦ ꢢꢪꢞ ꢢꢡ ꢦꢩ ꢫ ꢏ ꢁ ꢬ ꢟꢫꢞ ꢢꢡ ꢬ ꢤ ꢡ ꢞ ꢭꢢ ꢩ ꢦꢩ ꢫꢤ ꢮ ꢯ ꢤꢰ ꢢꢡ ꢠꢨ ꢯꢯ ꢫꢱ ꢯ ꢟꢦ ꢀ ꢁꢁꢋ ꢲ ꢝ ꢫꢢꢩ ꢠꢢ ꢠꢢ ꢢ ꢩ ꢯꢯ ꢫꢟꢣꢩ ꢞ ꢟꢤꢦ ꢠꢢ ꢣꢞ ꢟꢤꢦ ꢬ ꢤ ꢡ ꢧ ꢢꢞ ꢩ ꢟꢫꢠꢲ
Figure 2. MPC93R52 32–Lead Package Pinout (Top View)
140
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
Table 1: PIN CONFIGURATION
Pin
I/O
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Function
CCLK
FB_IN
Input
Input
Input
Input
Input
Input
PLL reference clock signal
PLL feedback signal input, connect to an output
PLL frequency range select
F_RANGE
FSELA
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
FSELB
FSELC
2
PLL_EN
MR/OE
Input
Input
LVCMOS
PLL enable/disable
LVCMOS
LVCMOS
Ground
VCC
Output enable/disable (high–impedance tristate) and device reset
Clock outputs
QA0–4, QB0–3, QC0–1 Output
GND
Supply
Supply
Negative power supply
VCCA
PLL positive power supply (analog power supply). It is recommended to use
an external RC filter for the analog power supply pin V
applications section for details.
. Please see
CCA
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 1 and Table 2 for supported frequency ranges and output to input frequency ratios.
F_RANGE
FSELA
0
0
0
0
VCO ÷ 1 (High input frequency range)
Output divider ÷ 4
VCO ÷ 2 (Low input frequency range)
Output divider ÷ 6
FSELB
Output divider ÷ 4
Output divider ÷ 2
FSELC
Output divider ÷ 2
Output divider ÷ 4
MR/OE
0
Outputs enabled (active)
Outputs disabled (high–impedance state) and
reset of the device. During reset, the PLL
feedback loop is open and the VCO is operating
at its lowest frequency. The MPC93R52
requires reset after any loss of PLL lock. Loss
of PLL lock may occur when the external
feedback path is interrupted. The length of the
reset pulse should be greater than two
reference clock cycles (CCLK). The device is
reset by the internal power–on reset (POR)
circuitry during power–up.
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is
substituted for the internal VCO output.
MPC93R52 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
141
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
Table 3: GENERAL SPECIFICATIONS
Symbol
Characteristics
Output Termination Voltage
Min
Typ
V B 2
CC
Max
Unit
V
Condition
V
TT
MM
HBM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch–Up Immunity
200
2000
200
V
V
mA
pF
pF
C
Power Dissipation Capacitance
Input Capacitance
10
Per output
Inputs
PD
C
4.0
IN
2
Table 4: ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
3.9
Unit
V
Condition
V
CC
Supply Voltage
V
IN
DC Input Voltage
V
V
+0.3
V
CC
CC
V
DC Output Voltage
DC Input Current
+0.3
V
OUT
I
20
50
mA
mA
°C
IN
I
DC Output Current
Storage Temperature
OUT
T
S
-65
125
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0° to 70°C)
Symbol
Characteristics
Input high voltage
Min
Typ
Max
V + 0.3
CC
Unit
V
Condition
LVCMOS
LVCMOS
V
IH
2.0
V
IL
Input low voltage
0.8
V
a
V
Output High Voltage
Output Low Voltage
2.4
V
I
=-24 mA
OH
OH
V
0.55
0.30
V
V
I
OL
I
OL
= 24 mA
= 12 mA
OL
Z
OUT
Output impedance
14 - 17
W
b
I
Input Current
200
5.0
10
µA
mA
mA
V
V
=V or V =GND
CC IN
IN
IN
I
Maximum PLL Supply Current
3.0
7.0
Pin
CCA
CCA
I
c
Maximum Quiescent Supply Current
All V Pins
CC
CCQ
a
The MPC93R52 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated trans-
mission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.
Inputs have pull-down resistors affecting the input current.
TT
b
c
I
is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
CCQ
142
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
Table 6: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0° to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
bc
f
ref
Input reference frequency in PLL mode
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
50.0
33.3
25.0
120.0
80.0
60.0
40.0
MHz
MHz
MHz
MHz
16.67
d
Input reference frequency in PLL bypass mode
50.0
200
250.0
480
MHz
MHz
e
f
f
VCO lock frequency range
VCO
f
Output Frequency
÷2 output
100
50
33.3
25
240
120
80
60
40
MHz
MHz
MHz
MHz
MHz
MAX
2
÷4 output
÷6 output
÷8 output
÷12 output
16.67
t
Minimum Reference Input Pulse Width
2.0
ns
ns
PWMIN
g
tr, tf
CCLK Input Rise/Fall Time
1.0
0.8 to 2.0V
PLL locked
t
∅
(
Propagation Delay CCLK to FB_IN
(static phase offset)
(f = 50MHz)
ref
-100
+200
ps
ps
)
h
t
Output-to-output Skew
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
150
100
100
50
ps
ps
ps
ps
sk(O)
DC
Output duty cycle
47
50
53
1.0
8
%
ns
ns
ns
t , t
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
0.1
0.55 to 2.4V
r
f
t
PLZ, HZ
t
10
PZL, LZ
t
output frequencies mixed
all outputs same frequency
450
100
ps
ps
JIT(CC)
t
Period Jitter
output frequencies mixed
all outputs same frequency
450
100
ps
ps
JIT(PER)
i
t
I/O Phase Jitter
÷4 feedback divider RMS (1 σ)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
j
40
50
60
80
ps
ps
ps
ps
∅
JIT(
)
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
2.0–8.0
1.0–4.0
0.8–2.5
0.6–1.5
MHz
MHz
MHz
MHz
t
Maximum PLL Lock Time
10
ms
LOCK
a
b
c
d
e
f
AC characteristics apply for parallel output termination of 50Ω to V .
TT
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
The PLL may be unstable with a divide by 2 feedback ratio.
In PLL bypass mode, the MPC93R52 divides the input reference clock.
The input frequency f on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f = f ÷ FB.
ref
ref
VCO
See Table 9 and Table 10 for output divider configurations.
g
The MPC93R52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t , can only be guaranteed if
∅
( )
tr/tf are within the specified range.
h
i
j
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 s.
-3 dB point of PLL transfer characteristics.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
143
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
APPLICATIONS INFORMATION
Programming the MPC93R52
The FSELA, FSELB, FSELC pins select the desired output
clock frequencies. Possible frequency ratios of the reference
clock input to the outputs are 1:1, 1:2, 1:3, 3:2 as well as 2:3,
3:1 and 2:1. Table 1 illustrates the various output configura-
tions and frequency ratios supported by the MPC93R52. See
also Table 9, Table 10 and Figure 3 to Figure 6 for further refer-
The MPC93R52 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider con-
figurations can be used to achieve the desired input to output
frequency relationship. The feedback frequency and divider
should be used to situate the VCO in the frequency lock range
between 200 and 480 MHz for stable and optimal operation. ence. A ÷2 output divider cannot be used for feedback.
2
Table 9: MPC93R52 Example Configuration (F_RANGE = 0)
a
PLL Feedback
fref [MHz] FSELA FSELB FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
b
VCO ÷ 4
50-120
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
fref
(50-120
MHz)
fref
fref
fref
fref
(50-120
MHz)
fref ⋅ 2 (100-240
MHz)
fref
(50-120
MHz)
(50-120
MHz)
fref
(50-120
MHz)
fref ⋅ 2÷3 (33-80
(50-120
MHz)
fref ⋅ 2 (100-240
MHz)
MHz)
fref ⋅ 2÷3 (33-80
(50-120
MHz)
fref
(50-120
MHz)
MHz)
c
VCO ÷ 6
33.3-80
fref
fref
fref
fref
(33-80
MHz)
fref ⋅3÷2 (50-120
fref ⋅ 3 (100-240
MHz)
MHz)
(33-80
MHz)
fref ⋅3÷2 (50-120
fref ⋅3÷2 (50-120
MHz)
MHz)
(33-80
MHz)
fref ⋅ 3 (100-240
fref ⋅ 3 (100-240
MHz)
MHz)
(33-80
MHz)
fref ⋅ 3 (100-240
fref ⋅3÷2 (50-120
MHz)
MHz)
a. fref is the input clock reference frequency (CCLK)
b. QAx connected to FB_IN and FSELA=0
c. QAx connected to FB_IN and FSELA=1
Table 10: MPC93R52 Example Configurations (F_RANGE = 1)
a
PLL Feedback
fref [MHz] FSELA FSELB FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
b
VCO ÷ 8
25-60
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
fref
(25-60
MHz)
fref
fref
fref
fref
(25-60
MHz)
fref ⋅ 2 (50-120 MHz)
fref
(25-60
MHz)
(25-60
MHz)
fref
(25-60
MHz)
fref ⋅2÷3 (16-40 MHz)
(25-60
MHz)
fref ⋅ 2 (50-120 MHz)
fref ⋅2÷3 (16-40 MHz)
(25-60
MHz)
fref
(25-60
MHz)
c
VCO ÷ 12
16.67-40
fref
fref
fref
fref
(16-40
MHz)
fref ⋅3÷2 (25-60 MHz)
fref ⋅ 3 (50-120 MHz)
(16-40
MHz)
fref ⋅3÷2 (25-60 MHz)
fref ⋅3÷2 (25-60 MHz)
(16-40
MHz)
fref ⋅ 3 (50-120 MHz) fref ⋅ 3 (50-120 MHz)
fref ⋅ 3 (50-120 MHz) fref ⋅3÷2 (25-60 MHz)
(16-40
MHz)
a. fref is the input clock reference frequency (CCLK)
b. QAx connected to FB_IN and FSELA=0
c. QAx connected to FB_IN and FSELA=1
144
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
Example Configurations for the MPC93R52
Figure 3. MPC93R52 Default Configuration
Figure 4. MPC93R52 Zero Delay Buffer Configuration
ꢂ ꢋꢉ
ꢂ ꢋ ꢉ
ꢬ ꢡꢢꢬ ꢼ ꢊ ꢉꢉ ꢓꢺ ꢻ
ꢬ ꢡꢢ ꢬ ꢼ ꢙ ꢄꢲ ꢘ ꢓꢺ ꢻ
ꢁ
ꢁ
ꢒ
ꢖ
ꢁ ꢁ ꢒꢖ
ꢂ ꢋꢊ
ꢂ ꢋꢄ
ꢂ ꢋꢅ
ꢂ ꢋꢌ
ꢂ ꢋ ꢊ
ꢂ ꢋ ꢄ
ꢂ ꢋ ꢅ
ꢂ ꢋ ꢌ
ꢊ
ꢉ
ꢉ
ꢓ
ꢺ
ꢻ
ꢙ
ꢄ
ꢲ
ꢘ
ꢓ
ꢺ
ꢻ
ꢍꢃ ꢎ ꢗꢇ
ꢍ ꢃꢎꢗ ꢇ
ꢂ ꢃꢉ
ꢂ ꢃꢊ
ꢂ ꢃꢄ
ꢂ ꢃꢅ
ꢂ ꢃ ꢉ
ꢂ ꢃ ꢊ
ꢂ ꢃ ꢄ
ꢂ ꢃ ꢅ
ꢍꢑ ꢐ ꢒꢋ
ꢍꢑ ꢐ ꢒꢃ
ꢍꢑ ꢐ ꢒꢁ
ꢍ ꢑꢐꢒ ꢋ
ꢍ ꢑꢐꢒ ꢃ
ꢍ ꢑꢐꢒ ꢈ
2
ꢙ ꢄ ꢲꢘ ꢓꢺ ꢻ
ꢙ ꢄ ꢲꢘ ꢓꢺ ꢻ
ꢊꢉ ꢉ ꢓ ꢺꢻ
ꢄꢉ ꢉ ꢓ ꢺꢻ
ꢀ ꢁꢁ
ꢍ
ꢎ
ꢏ
ꢋ
ꢇ
ꢆ
ꢐ
ꢍ
ꢎ
ꢏ
ꢋ
ꢇ
ꢆ
ꢐ
ꢂ ꢁꢉ
ꢂ ꢁꢊ
ꢂ ꢁꢉ
ꢂ ꢁꢊ
MPC93R52
MPC93R52
ꢊ ꢉꢉ ꢓ ꢺꢻ ꢴꢍ ꢢꢢꢧ ꢽꢩꢣꢳ ꢶ
ꢙ ꢄꢲ ꢘ ꢓꢺ ꢻ ꢴꢍꢢ ꢢ ꢧꢽ ꢩ ꢣꢳꢶ
MPC93R52 default configuration (feedback of QB0 = 100
MHz). All control pins are left open.
MPC93R52 zero–delay (feedback of QB0 = 62.5 MHz).
All control pins are left open except FSELC = 1. All out-
puts are locked in frequency and phase to the input clock.
Frequency range
Input
Min
Max
Frequency range
Input
Min
Max
50 MHz
50 MHz
50 MHz
100 MHz
120 MHz
120 MHz
120 MHz
240 MHz
50 MHz
50 MHz
50 MHz
50 MHz
120 MHz
120 MHz
120 MHz
120 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
Figure 5. MPC93R52 Default Configuration
Figure 6. MPC93R52 Zero Delay Buffer Config. 2
ꢂ
ꢋ
ꢉ
ꢂ
ꢋ
ꢉ
ꢬ
ꢡ
ꢢ
ꢬ
ꢼ
ꢅ
ꢅ
ꢲ
ꢅ
ꢓ
ꢺ
ꢻ
ꢬ
ꢡ
ꢢ
ꢬ
ꢼ
ꢅ
ꢅ
ꢲ
ꢅ
ꢓ
ꢺ
ꢻ
ꢁ
ꢁ
ꢒ
ꢖ
ꢁ
ꢁ
ꢒ
ꢖ
ꢂ ꢋꢊ
ꢂ ꢋꢄ
ꢂ ꢋꢅ
ꢂ ꢋꢌ
ꢂ ꢋ ꢊ
ꢂ ꢋ ꢄ
ꢂ ꢋ ꢅ
ꢂ ꢋ ꢌ
ꢅ
ꢅ
ꢲ
ꢅ
ꢓ
ꢺ
ꢻ
ꢅ
ꢅ
ꢲ
ꢅ
ꢓ
ꢺ
ꢻ
ꢍ
ꢃ
ꢎ
ꢗ
ꢇ
ꢍ
ꢃ
ꢎ
ꢗ
ꢇ
ꢂ ꢃꢉ
ꢂ ꢃꢊ
ꢂ ꢃꢄ
ꢂ ꢃꢅ
ꢂ ꢃ ꢉ
ꢂ ꢃ ꢊ
ꢂ ꢃ ꢄ
ꢂ ꢃ ꢅ
ꢀꢁ ꢁ
ꢀꢁ ꢁ
ꢍꢑ ꢐ ꢒꢋ
ꢍꢑ ꢐ ꢒꢃ
ꢍꢑ ꢐ ꢒꢁ
ꢍꢑ ꢐꢒ ꢋ
ꢍꢑ ꢐꢒ ꢃ
ꢍꢑ ꢐꢒ ꢁ
ꢅꢅ ꢲ ꢅ ꢓꢺ ꢻ
ꢅ ꢅ ꢲꢅ ꢓꢺ ꢻ
ꢘ
ꢉ
ꢓ
ꢺ
ꢻ
ꢀ ꢁꢁ
ꢀ ꢁꢁ
ꢍ
ꢎ
ꢏ
ꢋ
ꢇ
ꢆ
ꢐ
ꢍ
ꢎ
ꢏ
ꢋ
ꢇ
ꢆ
ꢐ
ꢀ
ꢁ
ꢁ
ꢂ ꢁꢉ
ꢂ ꢁꢊ
ꢂ ꢁꢉ
ꢂ ꢁꢊ
ꢊ
ꢉ
ꢉ
ꢓ
ꢺ
ꢻ
MPC93R52
MPC93R52
ꢅ
ꢅ
ꢲ
ꢅ
ꢓ
ꢺ
ꢻ
ꢴ
ꢍ
ꢢ
ꢢ
ꢧ
ꢽ
ꢩ
ꢣ
ꢳ
ꢶ
ꢅ
ꢅ
ꢲ
ꢅ
ꢓ
ꢺ
ꢻ
ꢴ
ꢍ
ꢢ
ꢢ
ꢧ
ꢽ
ꢩ
ꢣ
ꢳ
ꢶ
MPC93R52 configuration to multiply the reference frequen-
cy by 3, 3÷2 and 1. PLL feedback of QA4 = 33.3 MHz.
MPC93R52 zero–delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Frequency range
Input
Min
Max
Frequency range
Input
Min
Max
25 MHz
50 MHz
50 MHz
100 MHz
60 MHz
120 MHz
120 MHz
240 MHz
25 MHz
25 MHz
25 MHz
25 MHz
60 MHz
60 MHz
60 MHz
60 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
145
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
Power Supply Filtering
Using the MPC93R52 in zero–delay applications
The MPC93R52 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA (PLL) power supply impacts the device characteris-
tics, for instance I/O jitter. The MPC93R52 provides separate
power supplies for the output buffers (VCC) and the phase-
locked loop (VCCA) of the device. The purpose of this design
technique is to isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked loop.
In a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of isola-
tion may be required. The simple but effective form of isolation
is a power supply filter on the VCCA pin for the MPC93R52.
Figure 7 illustrates a typical power supply filter scheme. The
MPC93R52 frequency and phase stability is most susceptible
to noise with spectral content in the 100kHz to 20MHz range.
Therefore the filter should be designed to target this range.
The key parameter that needs to be met in the final filter design
is the DC voltage drop across the series filter resistor RF. From
the data sheet the ICCA current (the current sourced through
the VCCA pin) is typically 3 mA (5 mA maximum), assuming
that a minimum of 2.98V must be maintained on the VCCA pin.
The resistor RF shown in Figure 7 “VCCA Power Supply Filter”
should have a resistance of 5–25W to meet the voltage drop
criteria.
Nested clock trees are typical applications for the
MPC93R52. Designs using the MPC93R52 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC93R52 clock driver allows for its use as a zero delay buff-
er. One example configuration is to use a ÷4 output as a feed-
back to the PLL and configuring all other outputs to a divide-
by-4 mode. The propagation delay through the device is
virtually eliminated. The PLL aligns the feedback clock output
edge with the clock input reference edge resulting a near zero
delay through the device. The maximum insertion delay of the
device in zero-delay applications is measured between the ref-
erence clock input and any output. This effective delay con-
sists of the static phase offset, I/O jitter (phase or long-term
jitter), feedback path delay and the output-to-output skew error
relative to the feedback output.
2
Calculation of part-to-part skew
The MPC93R52 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC93R52 are connected together, the maximum overall tim-
ing uncertainty from the common CCLK input to any output is:
tSK(PP) = t ∅ + tSK(O) + tPD, LINE(FB) + tJIT( ꢀ CF
∅
)
(
)
ꢏ ꢼ ꢘ ꢸꢄ ꢘ Ω
ꢁ ꢼ ꢄꢄ µꢍ
ꢍ
ꢍ
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
ꢏ
ꢍ
ꢀ ꢁꢁꢋ
ꢀꢁ ꢁ
ꢁ
ꢍ
ꢊꢉ ꢦꢍ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀ ꢁꢁ
ꢁꢁꢒ ꢖ
ꢁ
ꢤ
ꢥ
ꢥ
ꢤ
ꢦ
ꢞ
ꢅ
ꢅ
ꢲ
ꢲ
ꢲ
ꢊ
ꢉ
ꢉ
ꢦ
ꢍ
ꢝ
ꢈ
ꢾ
ꢒ
ꢗ
ꢇ
ꢐ
ꢴ
ꢍ
ꢃ
ꢶ
ꣁ ꢞ
∅
ꢴ
ꢶ
ꢂ
ꢍ
ꢃ
ꢈ
ꢢ
ꢵ
ꢵ
ꢟ
ꢣ
ꢣ
ꢢ
ꢊ
ꢊ
Figure 7. VCCA Power Supply Filter
ꢞ
ꢿ
∅
ꢴ
ꢗ
ꢹ
ꢶ
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7 “VCCA Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
ꢋ
ꢦ
ꢱ
ꢂ
ꢈ
ꢢ
ꢟ
ꢢ
ꣀ t
ꢑ ꢖ ꢴ ꢕ ꢶ
ꣀ
ꢞ
∅
ꢴ
ꢶ
ꢂ ꢍꢃ
ꢈ
ꢢ
ꢵ
ꢟ
ꢣ
ꢢ
ꢄ
ꢞ
∅
ꢿ ꢗ ꢹ ꢴ ꢶ
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low im-
pedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC93R52 has several
design features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be ade-
ꢋ ꢦꢱ ꢂ
ꢈ ꢢ ꢵ ꢟ ꢣ ꢢ
ꢄ
ꣀ t
ꢑ ꢖ ꢴ ꢕ ꢶ
ꢓꢩ ꢪꢲ ꢠꢳꢢ ꢰ
ꢞ
ꢑ ꢖ ꢴ ꢝ ꢝ ꢶ
Figure 8. MPC93R52 max. device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 s) is
quate to eliminate power supply noise related problems in specified. I/O jitter numbers for other confidence factors (CF)
most designs. can be derived from Table 11.
146
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC93R52 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can
drive multiple series terminated lines. Figure 10 “Single versus
Dual Transmission Lines” illustrates an output driving a single
series terminated line versus two series terminated lines in
parallel. When taken to its extreme the fanout of the
MPC93R52 clock driver is effectively doubled due to its capa-
bility to drive multiple lines.
Table 11: Confidence Facter CF
CF
1s
Probability of clock edge within the distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
2s
3s
4s
5s
6s
2
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% ( 3s) is assumed, resulting in a worst
case timing uncertainty from input to any output of -445 ps to
395 ps relative to CCLK:
ꢓꢝ ꢁꢜ ꢅ ꢏꢘ ꢄ
ꢕ ꣂꢹꢝ ꣂꢹ
ꢃ ꣂꢍꢍꢐ ꢏ
ꣃ
ꢼ ꢘ ꢉΩ
ꢕ
ꢏ ꢼ ꢅ ꢙΩ
ꢑ
ꢊꢌΩ
ꢗ ꢇ
ꢕ ꢨ ꢞꢋ
tSK(PP)
=
[–200ps...150ps] + [–200ps...200ps] +
[(15ps @ –3)...(15ps @ 3)] + tPD, LINE(FB)
ꢓꢝ ꢁꢜ ꢅ ꢏꢘ ꢄ
ꢕ ꣂꢹꢝ ꣂꢹ
ꢃ ꣂꢍꢍꢐ ꢏ
ꣃ
ꣃ
ꢼ ꢘ ꢉΩ
ꢼ ꢘ ꢉΩ
ꢕ
ꢕ
ꢏ ꢼ ꢅ ꢙΩ
ꢑ
tSK(PP)
=
[–445ps...395ps] + tPD, LINE(FB)
ꢕ ꢨ ꢞꢃ ꢉ
ꢕ ꢨ ꢞꢃ ꢊ
Due to the frequency dependence of the I/O jitter, Figure 9
“Max. I/O Jitter versus frequency” can be used for a more pre-
cise timing performance analysis.
ꢊ
ꢌ
Ω
ꢗ ꢇ
ꢏ ꢼ ꢅ ꢙΩ
ꢑ
Figure 10. Single versus Dual Transmission Lines
The waveform plots in Figure 11 “Single versus Dual Line
Termination Waveforms” show the simulation results of an out-
put driving a single line versus two lines. In both cases the
drive capability of the MPC93R52 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output-to-output skew of the
MPC93R52. The output waveform in Figure 11 “Single versus
Dual Line Termination Waveforms” shows a step in the wave-
form, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36Ω se-
ries resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
Figure 9. Max. I/O Jitter versus frequency
Driving Transmission Lines
The MPC93R52 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20Ω the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the meth-
od of choice. In a point-to-point scheme either series termi-
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 36Ω || 36Ω
R0 = 14Ω
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near unity
nated or parallel terminated transmission lines can be used. reflection coefficient, to 2.6V. It will then increment towards the
The parallel technique terminates the signal at the end of the quiescent 3.0V in steps separated by one round trip delay (in
line with a 50Ω resistance to VCC÷2.
this case 4.0ns).
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
147
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
ꢅꢲ ꢉ
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 12 “Optimized Dual Line Termination” should be
used. In this case the series terminating resistors are reduced
such that when the parallel combination is added to the output
buffer impedance the line impedance is perfectly matched.
ꢕ ꢨꢞ ꢋ
ꢞ ꢼ ꢅ ꢲꢛ ꢜꢘꢙ
ꢕ ꢨꢞ ꢃ
ꢞ ꢼ ꢅꢲ ꢜꢅ ꢛꢙ
ꢈ
ꢄꢲ ꢘ
ꢄꢲ ꢉ
ꢊꢲ ꢘ
ꢊꢲ ꢉ
ꢉꢲ ꢘ
ꢉ
ꢈ
ꢗꢦ
ꢓꢝ ꢁꢜ ꢅ ꢏꢘ ꢄ
ꢕ ꣂꢹꢝ ꣂꢹ
ꣃ
ꣃ
ꢼ ꢘ ꢉΩ
ꢼ ꢘ ꢉΩ
ꢕ
ꢕ
ꢏ ꢼ ꢄ ꢄΩ
ꢑ
ꢃ ꣂꢍꢍꢐ ꢏ
2
ꢊꢌΩ
ꢏ ꢼ ꢄ ꢄΩ
ꢑ
14Ω + 22Ω ꢁ 22Ω = 50Ω ꢁ 50Ω
25Ω = 25Ω
ꢄ
ꢌ
ꢙ
ꢛ
ꢊꢉ
ꢊꢄ
ꢊ ꢌ
ꢹꢗ ꢓ ꢐ ꢴꢦ ꢑꢶ
Figure 12. Optimized Dual Line Termination
Figure 11. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
ꢓꢝ ꢁꢜ ꢅ ꢏꢘ ꢄ
ꢈꣂ ꢹ
ꢝ ꢨꢫꢠꢢ
ꢆ ꢢꢦꢢ ꢡꢩꢞ ꢤ ꢡ
ꣃ
ꢼ ꢘꢉ Ω
ꣃ ꢼ ꢘ ꢉ Ω
ꢕ
ꢕ
ꣃ ꢼ ꢘꢉ W
ꢏ ꢼ ꢘ ꢉ Ω
ꢹ
ꢏ ꢼ ꢘ ꢉΩ
ꢹ
ꢀ
ꢹ
ꢀ
ꢹ ꢹ
ꢹ
Figure 13. CCLK MPC93R52 AC test reference for Vcc = 3.3V and Vcc = 2.5V
148
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R52
ꢀ
ꢀ
ꢁ
ꢁ
ꢁ
Bꢄ
ꢁ
ꢀ
ꢀ
ꢁ
ꢁ
ꢁ
ꢆ ꢇꢈ
ꢁꢁ ꢒꢖ
ꢍꢃ ꢎ ꢗꢇ
Bꢄ
ꢁ
ꢀ
ꢀ
ꢁ
ꢁ
ꢁ
ꢆ ꢇꢈ
Bꢄ
ꢁ
ꢀ
ꢀ
ꢁ
ꢁ
ꢁ
ꢆ
ꢇ
ꢈ
Bꢄ
ꢁ
ꢞ
ꢑ ꢖ ꢴ ꢕ ꢶ
ꢆ ꢇꢈ
ꢹ ꢭꢢ ꢯ ꢟꢦ ꢸꢞ ꢤꢸ ꢯ ꢟꢦ ꢠ ꢳꢢꢰ ꢟꢠ ꢧꢢ ꢬꢟꢦ ꢢꢧ ꢩꢠ ꢞ ꢭꢢ ꢰꢤ ꢡꢠꢞ ꢣꢩꢠ ꢢ ꢧꢟꢬꢬ ꢢꢡꢢ ꢦꢣꢢ ꢟꢦ
ꢯ ꢡꢤ ꢯ ꢩꢮ ꢩ ꢞꢟꢤ ꢦ ꢧ ꢢꢫ ꢩꢱ ꢽꢢ ꢞꢰ ꢢꢢꢦ ꢩꢦ ꢱ ꢠꢟꢥ ꢟꢫꢩꢡ ꢧꢢ ꢫꢩꢱ ꢯꢩ ꢞꢭ ꢰ ꢟꢞꢭ ꢟꢦ ꢩ
ꢠꢟꢦ ꢮ ꢫꢢ ꢧ ꢢꢵꢟ ꢣꢢ
ꢞ
∅
ꢴ
ꢶ
2
Figure 14. Output–to–output Skew tSK(O)
Figure 15. Propagation delay (t(∅ , static phase
)
offset) test reference
ꢀ
ꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢒ
ꢖ
Bꢄ
ꢁ
ꢆ
ꢇ
ꢈ
ꢞ
ꢝ
ꢍ
ꢃ
ꢎ
ꢗ
ꢇ
ꢹ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢅ
ꢆ
ꢪ
ꢈ
ꢇ
ꢇ
ꢉ
ꢆ
ꢊ ꢋ ꢆ ꢌ
ꢂ ꣅꢆ ꢎ ꢆ ꢏꢐ ꢑ ꢒꣅ
ꢇ ꢈ
ꢄ
ꢇ
∅
ꢍ
ꢹ ꢭꢢ ꢞꢟ ꢥꢢ ꢬꢡ ꢤ ꢥ ꢞꢭ ꢢ ꢝ ꢒꢒ ꢣꢤꢦ ꢞꢡ ꢤꢫꢫꢢ ꢧ ꢢꢧ ꢮꢢ ꢞ ꢤ ꢞ ꢭꢢ ꢦꢤ ꢦ ꢣꢤꢦ ꢞꢡ ꢤꢫꢫꢢ ꢧ
ꢢ ꢧꢮ ꢢ ꢾ ꢧ ꢟꢵꢟꢧ ꢢ ꢧ ꢽ ꢱ ꢞ ꢭꢢ ꢞ ꢟꢥ ꢢ ꢽꢢ ꢞꢰ ꢢꢢ ꢦ ꢝ ꢒꢒ ꢣꢤꢦ ꢞꢡ ꢤꢫꢫꢢ ꢧ ꢢꢧ ꢮꢢꢠꢾ
ꢢ ꢪꢯ ꢡꢢ ꢠꢠ ꢢꢧ ꢩ ꢠ ꢩ ꢯꢢ ꢡꢣꢢꢦ ꢞꢩ ꢮꢢ
ꢹꢭ ꢢ ꢧ ꢢꢵꢟꢩ ꢞ ꢟꢤ ꢦ ꢟꢦ ꢞ ꢬ ꢤꢡ ꢩ ꢣꢤ ꢦꢞ ꢡꢤ ꢫꢫꢢ ꢧ ꢢ ꢧꢮ ꢢ ꢰꢟꢞ ꢭ ꢡꢢ ꢠꢯ ꢢꢣꢞ ꢞ ꢤ ꢩ ꢞ ꢥꢢ ꢩ ꢦ ꢟꢦ ꢩ
ꢡꢩ ꢦꢧ ꢤ ꢥ ꢠꢩ ꢥꢯ ꢫꢢ ꢤ ꢬ ꢣꢱꢣꢫꢢ ꢠ
ꢉ
ꢉ
Figure 16. Output Duty Cycle (DC)
Figure 17. I/O Jitter
ꢆ
ꢂ
ꣅ
ꢆ
ꢎ
ꢆ
ꣅ
ꢆ ꢂ ꣅꢆ ꢎ ꢈ ꢔꢗ ꣅ
ꢊ ꢋ ꢆ ꢌ ꢄ ꢕ ꢖ ꢍ ꢓ ꢇ
ꢊ
ꢋ
ꢆ
ꢌ
ꢁ
ꢁ
ꢍ
ꢓ
ꢓ
ꢔ
ꢈ
ꢹ
ꢹ
ꢇ ꣀ ꢊ
ꢹ
ꢇ
ꢉ
ꢹ ꢭꢢ ꢵꢩ ꢡ ꢟꢩꢞ ꢟꢤ ꢦ ꢟꢦ ꢣꢱꢣ ꢫꢢ ꢞ ꢟꢥ ꢢ ꢤꢬ ꢩ ꢠꢟꢮꢦ ꢩꢫ ꢽꢢ ꢞꢰ ꢢꢢ ꢦ ꢩꢧ ꢩꢣꢢ ꢦꢞ ꢣꢱꢣꢫꢢ ꢠꢾ ꢤ ꢵꢢꢡ ꢩ
ꢡ ꢩꢦ ꢧ ꢤꢥ ꢠꢩ ꢥꢯ ꢫꢢ ꢤ ꢬ ꢩ ꢧꢩ ꢣꢢꢦꢞ ꢣꢱꢣꢫꢢ ꢯꢩ ꢟꢡꢠ
ꢹꢭ ꢢ ꢧ ꢢꢵꢟꢩ ꢞ ꢟꢤ ꢦ ꢟꢦ ꢣꢱꢣꢫꢢ ꢞ ꢟꢥꢢ ꢤ ꢬ ꢩ ꢠꢟꢮ ꢦꢩ ꢫ ꢰꢟꢞ ꢭ ꢡꢢ ꢠꢯ ꢢꢣꢞ ꢞ ꢤ ꢞ ꢭ ꢢ ꢟꢧ ꢢꢩ ꢫ ꢯ ꢢꢡ ꢟꢤ ꢧ ꢤ ꢵꢢ ꢡ
ꢩ ꢡꢩ ꢦꢧ ꢤ ꢥ ꢠꢩ ꢥꢯ ꢫꢢ ꢤ ꢬ ꢣꢱꢣꢫꢢ ꢠ
Figure 18. Cycle–to–cycle Jitter
Figure 19. Period Jitter
ꢀ
ꢁ
ꢼ ꢅꢲ ꢅꢀ
ꢁ
ꢄ
ꢲ
ꢌ
ꢉ
ꢲ
ꢘ
ꢘ
ꢞ
ꢍ
ꢞ
ꢏ
Figure 20. Output Transition Time Test Reference
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
149
For More Information On This Product,
Go to: www.freescale.com
相关型号：
MPC941AE
941 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, PLASTIC, LQFP-48
NXP
MPC941FA
MPC900 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, PLASTIC, LQFP-48
MOTOROLA
MPC941FA
Low Skew Clock Driver, 941 Series, 27 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, LQFP-48
IDT
©2020 ICPDF网 联系我们和版权申明