MPC949FA [IDT]
Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 0.65 MM PITCH, LQFP-52;
| 型号： | MPC949FA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 0.65 MM PITCH, LQFP-52 驱动 逻辑集成电路 |
| 文件： | 总6页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MPC949
Low Voltage 1:15 PECL to CMOS
Clock Driver
The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15
outputs can be configured into a standard fanout buffer or into 1X and
1/2X combinations. The device features a low voltage PECL input, in
addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into
larger clock trees which utilize low skew PECL devices (see the
MC100EP111 data sheet) in the lower branches of the tree. The fifteen
outputs were designed and optimized to drive 50Ω series or parallel
terminated transmission lines. With output to output skews of 350ps the
MPC949 is an ideal clock distribution chip for synchronous systems
which need a tight level of skew from a large number of outputs. For a
similar product with a smaller fanout and package consult the MPC946
data sheet.
LOW VOLTAGE
1:15 PECL TO LVCMOS
CLOCK DRIVER
• Low Voltage PECL Clock Input
• 2 Selectable LVCMOS/LVTTL Clock Inputs
• 350ps Maximum Output to Output Skew
• Drives up to 30 Independent Clock Lines
• Maximum Output Frequency of 160MHz
• High Impedance Output Enable
• 52–Lead LQFP Packaging
FA SUFFIX
52–LEAD LQFP PACKAGE
CASE 848D–03
• 3.3V V
CC
Supply
With an output impedance of approximately 7Ω, in both the HIGH and
the LOW logic states, the output buffers of the MPC949 are ideal for
driving series terminated transmission lines. More specifically each of the
15 MPC949 outputs can drive two series terminated transmission lines.
With this capability, the MPC949 has an effective fanout of 1:30 in
applications using point–to–point distribution schemes.
The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are
generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability
to allow the user to select the ratio of 1X outputs to 1/2X outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH.
The MPC949 is fully 3.3V compatible. The 52 lead LQFP package was chosen to optimize performance, board space and cost
of the device. The 52–lead LQFP has a 10x10mm body size with a 0.65mm pin spacing.
IDT™ Low Voltage 1:15 PECL to CMOS Clock Driver
MPC949
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
1
MPC949
Low Voltage 1:15 PECL to CMOS Clock Driver
NETCOM
Figure 1. Logic Diagram
Figure 2. 52–Lead Pinout (Top View)
TCLK_Sel
TCLK0
0
÷1
0
1
TCLK1
÷2
1
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
25
24
23
22
21
20
19
18
17
16
15
14
NC
VCCb
Qb2
NC
PCLK
PCLK
R
0
1
2
3
4
6
41
42
43
44
45
46
47
48
49
50
51
52
VCCd
Qd4
Qa0:1
Qb0:2
PCLK_Sel
Dsela
GNDb
Qb1
GNDd
Qd3
0
1
VCCb
Qb0
VCCd
Qd2
Dselb
Dselc
MPC949
0
1
GNDb
GNDa
Qa1
GNDd
Qd1
Qc0:3
Qd0:5
VCCd
Qd0
0
1
VCCa
Qa0
GNDd
NC
Dseld
GNDa
1
2
3
4
5
6
7
8
9
10 11 12 13
MR/OE
FUNCTION TABLE
Input
PIN DESCRIPTION
Pin Name
0
1
Function
TCLK_Sel
PCLK_Sel
Dseln
TCLK0
TCLKn
÷1
TCLK1
PCLK
÷2
TCLK_Sel
(Int Pulldown)
Select pin to choose TCKL0 or TCLK1
LVCMOS/LVTTL clock inputs
True PECL clock input
TCLK0:1
(Int Pullup)
MR/OE
Enabled
Hi–Z
PCLK
(Int Pulldown)
PCLK
(Int Pullup)
Complement PECL clock input
1x or 1/2x input divide select pins
Dseln
(Int Pulldown)
MR/OE
(Int Pulldown)
Internal reset and output tristate control pin
Select Pin to choose TCLK or PCLK
PCLK_Sel
(Int Pulldown)
IDT™ Low Voltage 1:15 PECL to CMOS Clock Driver
MPC949
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
2
MPC949
Low Voltage 1:15 PECL to CMOS Clock Driver
NETCOM
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
TBD
–40
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
V
+ 0.3
V
I
DD
I
IN
TBD
125
mA
°C
T
Stor
Storage Temperature Range
*
Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
DC CHARACTERISTICS (T = 0° to 70°C, V
CC
= 3.3V ±5%)
A
Symbol
Characteristic
Min
Typ
Max
3.60
0.8
Unit
V
Condition
V
V
V
V
V
V
Input HIGH Voltage
Input LOW Voltage
(Except PECL_CLK)
(Except PECL_CLK)
2.0
IH
V
IL
Peak–to–Peak Input Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
PECL_CLK
PECL_CLK
300
1000
mV
V
PP
CMR
OH
OL
V
– 2.0
CC
2.5
V
– 0.6
Note 1.
CC
V
I
= –20mA (Note 2.)
= 20mA (Note 2.)
OH
OL
0.4
±120
4
V
I
I
IN
µA
pF
pF
mA
Note 3.
C
C
Input Capacitance
IN
pd
Power Dissipation Capacitance
25
70
Per Output
I
Maximum Quiescent Supply Current
85
CC
1. V
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
range and the input swing lies within the V specification.
CMR
the V
CMR
2. The MPC949 can drive 50Ω transmission lines on the incident edge. Each output can drive one 50Ω parallel terminated transmission line to
the termination voltage of V = V /2. Alternately, the device drives up to two 50Ω series terminated transmission lines.
PP
TT CC
3. Inputs have pull–up/pull–down resistors which affect input current.
AC CHARACTERISTICS (T = 0° to 70°C, V
CC
= 3.3V ±5%)
A
Symbol
Characteristic
Maximum Input Frequency
Propagation Delay
Min
Typ
Max
Unit
MHz
ns
Condition
Note 4.
F
160
max
t
PECL_CLK to Q
TTL_CLK to Q
4.0
4.2
6.5
7.5
9.0
10.6
Note 4.
PLH
t
Propagation Delay
PECL_CLK to Q
TTL_CLK to Q
3.8
4.0
6.2
7.2
8.6
10.5
ns
Note 4.
PHL
t
t
Output–to–Output Skew
Part–to–Part Skew
300
350
ps
ns
Note 4.
Note 5.
sk(o)
PECL_CLK to Q
TTL_CLK to Q
1.5
2.0
2.75
4.0
sk(pp)
t
,t
PZL PZH
Output Enable Time
Output Disable Time
Output Rise/Fall Time
3
3
11
11
ns
ns
ns
Note 4.
t ,t
PLZ PHZ
Note 4.
t , t
r
0.10
1.0
0.8V to 2.0V
f
4. Driving 50Ω transmission lines terminated to V /2.
CC
5. Part–to–part skew at a given temperature and voltage.
IDT™ Low Voltage 1:15 PECL to CMOS Clock Driver
MPC949
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
3
MPC949
Low Voltage 1:15 PECL to CMOS Clock Driver
NETCOM
APPLICATIONS INFORMATION
line impedances. The voltage wave launched down the two
Driving Transmission Lines
lines will equal:
The MPC949 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 10Ω
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC949 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 3 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC949 clock
driver is effectively doubled due to its capability to drive
multiple lines.
OutA
= 3.8956
OutB
= 3.9386
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
In
2
4
6
8
10
12
14
TIME (nS)
MPC949
OUTPUT
BUFFER
Figure 4. Single versus Dual Waveforms
Z
= 50Ω
O
R
= 43Ω
S
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 5 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
7Ω
IN
IN
OutA
MPC949
OUTPUT
BUFFER
Z
O
= 50Ω
= 50Ω
R
S
= 43Ω
= 43Ω
OutB0
OutB1
7Ω
Z
O
R
S
MPC949
OUTPUT
Z
O
= 50Ω
= 50Ω
R
S
= 36Ω
= 36Ω
BUFFER
7Ω
Figure 3. Single versus Dual Transmission Lines
Z
O
R
S
The waveform plots of Figure 4 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC949 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC949. The output waveform
in Figure 4 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
7Ω + 36Ω 36Ω = 50Ω 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
IDT™ Low Voltage 1:15 PECL to CMOS Clock Driver
MPC949
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
4
MPC949
Low Voltage 1:15 PECL to CMOS Clock Driver
NETCOM
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 848D–03
ISSUE C
–X–
4X
4X TIPS
X=L, M, N
0.20 (0.008) H L–M N
0.20 (0.008) T L–M N
C
L
AB
AB
G
52
40
1
39
3X VIEW Y
VIEW Y
F
–L–
–M–
B
V
BASE METAL
PLATING
B1
V1
J
U
13
27
D
14
26
M
S
S
0.13 (0.005)
T L–M
N
–N–
SECTION AB–AB
ROTATED 90 CLOCKWISE
A1
S1
A
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –L–, –M– AND –N– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –T–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
4X θ2
4X θ3
C
0.10 (0.004)
T
–H–
–T–
SEATING
PLANE
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
VIEW AA
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
MILLIMETERS
DIM MIN MAX
10.00 BSC
INCHES
MIN MAX
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
S
0.05 (0.002)
A
A1
B
5.00 BSC
10.00 BSC
5.00 BSC
W
2 X R R1
B1
C
θ1
–––
0.05
1.30
0.20
0.45
0.22
1.70
––– 0.067
C1
C2
D
E
F
0.20 0.002 0.008
1.50 0.051 0.059
0.40 0.008 0.016
0.75 0.018 0.030
0.35 0.009 0.014
0.25 (0.010)
C2
θ
GAGE PLANE
G
0.65 BSC
0.026 BSC
J
K
R1
S
S1
U
0.07
0.50 REF
0.08
12.00 BSC
6.00 BSC
0.09
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
0.20 0.003 0.008
0.020 REF
0.20 0.003 0.008
0.472 BSC
0.236 BSC
0.16 0.004 0.006
K
E
C1
Z
VIEW AA
V
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
V1
W
Z
θ
0
7
0
7
–––
REF
13
–––
REF
13
θ1
θ2
θ3
0
12
5
0
12
5
IDT™ Low Voltage 1:15 PECL to CMOS Clock Driver
MPC949
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
5
49
LVoltage1:15PECLtoCMOSClockDriver
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
+408 284 8200 (outside U.S.)
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
XX-XXXX-XXXXX
相关型号：
MPC949FAR2
Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
IDT
MPC949FAR2
MPC900 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
MOTOROLA
MPC951FA
LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
MOTOROLA
MPC951FAR2
PLL Based Clock Driver, 951 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
IDT
MPC952FA
PLL Based Clock Driver, 952 Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, LQFP-32
IDT
MPC952FA
952 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32
NXP
MPC952FA
LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32
MOTOROLA
©2020 ICPDF网 联系我们和版权申明