BTT3050EJ [INFINEON]
The power transistor is built by an N-channel vertical power MOSFET. The BTT3050EJ is monolithically integrated. The BTT3050EJ is automotive qualified and is optimized for 24 V automotive applications.;
| 型号： | BTT3050EJ |
| 厂家： | 
Infineon |
| 描述： | The power transistor is built by an N-channel vertical power MOSFET. The BTT3050EJ is monolithically integrated. The BTT3050EJ is automotive qualified and is optimized for 24 V automotive applications. |
| 文件： | 总47页 (文件大小：1591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HITFET™ +24V BTT3050EJ
Smart low-side power switch
Features
• Single channel device optimized for 24 V applications
• Electrostatic discharge protection (ESD)
• Overcurrent, active clamping and overtemperature protection
• Overtemperature latch shutdown
• Supply pin undervoltage protection
• Dedicated status signal
• Slew-rate control to adjust switching speed
• PWM switching capability of 20 KHz (duty cycle 10%-90%)
• Green product (RoHS compliant)
• AEC qualified
Potential applications
Suitable for resistive and inductive loads.
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
BTT3050EJ is a 50 mΩ single channel smart low-side power switch within a PG-TDSO-8 package providing embedded
protective functions. The power transistor is built by a N-channel vertical power MOSFET. BTT3050EJ is monolithically
integrated, automotive qualified and optimized for 24 V automotive applications.
VBAT
IN
Load
Voltage Regulator
OUT
CVDD optional:
e.g. 100nF
VDD
VDD
RSTATUS
BTT3050EJ
Micro
controller
OUT
STATUS
I/O
Status/ Reset
IC Logic
IN
I/O
PWM
SRP
GND
RSRP
GND
App_01
Datasheet
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
Description
Table 1
Product summary
Parameter
Symbol
VOUT
Values
0 … 36 V
63 V
Operating voltage range
Maximum load voltage
ON-state resistance
VBAT(OUT)
RDS(ON)_25
IL(NOM)
50 mΩ
Nominal load current
Minimum current limitation
4 A
IL(LIM)
10 A
Product type
Package
PG-TDSO-8
Marking
Ordering code
BTT3050EJ
T3050EJ
BTT3050EJXUMA1
Datasheet
2
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1
2
3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Transient thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
4
Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Resistive load output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Adjustable switching speed and slewrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Maximum load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reverse current capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
4.3.1
4.3.2
4.4
4.5
5
5.1
5.2
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description of the STATUS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
6.1
6.1.1
6.1.2
6.2
Supply and input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Supply circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supply current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overvoltage clamping on output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overcurrent limitation and short circuit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset latch condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Reset via STATUS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset via STATUS pin and IN pin connected together . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.5
Datasheet
3
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
Table of contents
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1
8.2
8.3
8.4
Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Supply and input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
Characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Supply and input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1
9.2
9.3
10
10.1
10.2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Layout recommendations and considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Datasheet
4
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
1 Block diagram
1
Block diagram
Overtemperature
Protection
Latch
Logic
Status
Feedback
ESD
Protection
STATUS
OUT
ESD
Protection
IN
Undervoltage
Protection
Overvoltage
Protection
ESD
Protection
Supply
Unit
VDD
SRP
Gate Driving
Unit
ESD
Protection
Slewrate
adjustment
Overcurrent
Protection
GND
Figure 1
Block diagram of BTT3050EJ
Datasheet
5
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
2 Pin configuration
2
Pin configuration
1
2
8
7
IN
GND
GND
VDD
OUT
3
4
6
5
STATUS
SRP
GND
NC
Figure 2
Table 2
Pin configuration
Pin definitions and functions
Pin
Symbol
I/O
Function
1
IN
I
If IN logic is high, switches ON the power DMOS
If IN logic is low, switches OFF the power DMOS
2
3
VDD
I
Logic supply voltage pin, 3.3 V to 5.5 V
STATUS
I/O
RESET thermal latch function by microcontroller and pull-up
If STATUS logic is high, device is in normal operation
If STATUS logic is low, device is in overtemperature condition
4
SRP
NC
I
Slew rate control with external resistor
5
–
Pin internally not connected
6,7,8
GND
OUT
I/O
I/O
GND; source of power DMOS and logic 1)
Load connection, drain of power DMOS
Cooling Tab
1) All GND pins must be connected together
VBAT
VBAT
VDD
IDD
VDD
RSTATUS
ZL
ISTATUS
VDD
STATUS
VSTATUS
IL, ID
IIN
OUT
IN
VIN
VOUT,
VDS
ISRP
SRP
GND
VSRP
RSRP
GND
Figure 3
Naming definition of electrical parameters
Datasheet
6
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
3 General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 3
Absolute maximum ratings
1) T = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
Output voltages
Output voltage
VOUT
-0.3
-0.3
–
–
63
36
V
V
Internally clamped
PRQ-296
PRQ-297
Battery voltage for
short circuit protection
(extended range)
VBAT(SC)
VIN = 5 V; TA = 25°C, 125°C (3
samp./temp.);
RECU (pin OUT) = 20 mΩ;
RCABLE (pin OUT) = 16 mΩ;
LCABLE (pin OUT) = 1 µH/m;
LSC (pin OUT) = 5 µH + Lcable;
l = 40 m
Power stage
Load current
IL
0
–
IL(LIM)
A
–
PRQ-298
Logic pins
Input voltage
Status voltage
SRP voltage
VIN
-0.3
-0.3
-0.3
-0.3
–
–
–
–
5.5
5.5
5.5
6.5
V
V
V
V
–
–
–
–
PRQ-299
PRQ-300
PRQ-301
PRQ-302
VSTATUS
VSRP
VDD
Supply voltage
Energy capability
Energy single pulse
EAS
–
–
–
–
100
50
mJ
mJ
IL(0) = IL(NOM); VBAT = 28 V; TJ(0)
150°C
=
=
PRQ-303
PRQ-306
Energy repetitive pulse EAR(20M)
20 M cycles
IL(0) = IL(NOM); VBAT = 28 V; TJ(0)
105°C
Temperatures
Junction temperature TJ
-40
-55
–
–
150
150
°C
°C
–
–
PRQ-308
PRQ-309
Storage temperature
TSTG
ESD susceptibility
2)
ESD susceptibility (all
pins except OUT tab, to
GND)
VESD
-2
-4
–
–
2
4
kV
kV
PRQ-310
PRQ-311
HBM
2)
ESD susceptibility (OUT VESD_OUT
tab to GND)
HBM
(table continues...)
Datasheet
7
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
3 General product characteristics
Table 3
(continued) Absolute maximum ratings
1) T = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
3)
ESD susceptibility (all
pins)
VESD_CDMA
VESD_CDMC
-500
–
500
V
PRQ-312
PRQ-313
CDM
3)
ESD susceptibility
(corner pins)
-750
–
750
V
CDM
1)
2)
3)
Not subject to production test, specified by design
ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
ESD susceptibility, Charged Device Model "CDM" according JEDEC JESD22-C101
Notes:
1.
Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2.
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
datasheet. Fault conditions are considered as outside normal operating range. Protection functions are not
designed for continuous repetitive operation.
3.2
Functional range
Table 4
Functional range
Symbol
Parameter
Values
Unit Note or condition
P-Number
Min. Typ. Max.
1)
Battery voltage range
for nominal operation
VBAT(NOR)
VDD(NOR)
VDD(EXT1)
6
–
–
–
36
V
PRQ-314
PRQ-316
PRQ-315
1)
Supply voltage range
for nominal operation
3.3
3.0
5.5
5.5
V
1)
Supply voltage range
for extended_1
operation
V
Parameter deviations possible
1)
Supply voltage range
for extended_2
operation
VDD(EXT2)
5.5
–
6.5
V
PRQ-551
VBAT < 46 V;
Parameter deviations possible
1)
Junction temperature TJ
-40
2.2
–
–
150
160
°C
PRQ-318
PRQ-319
1)
External resistor range RSRP
for adjustable slewrate
operation
kΩ
1)
Not subject to production test, specified by design
Note:
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical characteristics table.
Datasheet
8
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
3 General product characteristics
3.3
Thermal resistance
Table 5
Parameter
Thermal resistance
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
1)
Junction to case
RthJC
–
–
–
3.0
35
45
–
–
–
K/W
PRQ-320
PRQ-321
PRQ-322
2)
1)
Junction to ambient
2s2p
RthJA(2s2p)
RthJA(1s0p)
K/W
3)
1)
Junction to ambient
(1s0p + 600 mm2Cu)
K/W
4)
1)
2)
Not subject to production test, specified by design
Specified RthJC value is simulated at natural convection on a cold plate setup. Bottom of the package is fixed to
ambient temperature. TAMB = 85°C. Device loaded with 1 W power.
Specified RthJA value is according to Jedec JESD51-2, -7 at natural convection of FR4 2s2p board; the product
(chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x
35 µm Cu). TAMB = 85°C. Device loaded with 1 W power.
Specified RthJA value is according to Jedec JESD51-2, -7 at natural convection on FR4 1s0p board; the product
(chip + package) was simulated on a 76.2 × 114.3 × 1.5 mm board with additional heatspreading copper area of
600 m2 and 70 µm thickness. TAMB = 85°C. Device loaded with 1 W power.
3)
4)
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to
www.jedec.org.
Datasheet
9
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
3 General product characteristics
3.4
Transient thermal impedance
Figure 4
ZthJA = f(tp)
Typical transient thermal impedance ZthJA = f(tp), TA = 85°C.
In Figure 4 the value is according to Jedec JESD51-2, at natural convection on FR4 boards. Where applicable a thermal
via array under the exposed pad contacted the first inner copper layer. The device is dissipating 1 W power.
Datasheet
10
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
4 Power stage
4
Power stage
4.1
Output on-state resistance
Figure 5
Typical on-state resistance RDS(ON) = f(TJ); VDD = VIN = 5 V, 3 V
Figure to be updated.
The on-state resistance depends on the supply voltage (VDD) as well as on the junction temperature (TJ). Figure
5 shows these dependencies in terms of temperature and voltage for the typical on-state resistance RDS(ON). The
behavior in reverse polarity is described in Reverse current capability.
Datasheet
11
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2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
4 Power stage
4.2
Resistive load output timing
VIN
VIN(TH)H
VIN(TH)L
t
VOUT
VBAT
80 %
-(ΔV/Δt)ON
(ΔV/Δt)OFF
20 %
tDON
tF
tDOFF
tR
t
tOFF
tON
Figure 6
Definition of power output timing for resistive load
Figure 6 shows the typical timing when switching a resistive load.
Both -(ΔV/Δt)ON and (ΔV/Δt)OFF can be calculated using the following formulas:
•
•
Turn-on slew rate: -(ΔV/Δt)ON = (0.6 x VBAT) / tF
Turn-off slew rate: (ΔV/Δt)OFF = (0.6 x VBAT) / tR
NB: the coefficient 0.6 is based on 20% to 80% of VBAT, this is how the measurement of ΔV is defined.
As shown in Figure 6 tON and tOFF can be calculated from delay time (tDON, tDOFF) and falling/rising time (tF, tR) using
the following formulas:
•
•
Turn-on time: tON = tDON + tF
Turn-off time: tOFF = tDOFF + tR
4.3
Adjustable switching speed and slewrate
SRP
Driver
&
RSRP(int)
RSRP
ESD
Logic
GND
Figure 7
Simplified SRP circuit
Figure 7 shows the slew rate control circuit of BTT3050EJ. The circuit includes an ESD protection mechanism via a
zener structure.
Datasheet
12
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
4 Power stage
In order to optimize the switching speed of the MOSFET to a specific application, an external resistor can be
connected between SRP pin and GND to select the desired slew rate (see switching timings in Power stage) . The
adjustment of the slew rate also allows to balance between electromagnetic emissions and power dissipation.
To reduce the number of external components, the SRP pin can be connected directly to GND. This sets the slew rate
at its largest value enabling fast switching timings.
It is not recommended to connect directly SRP pin to VDD or to leave it floating (open).
The accuracy of the switching speed is dependent on the accuracy of the external resistor used. It is recommended to
use short connections between the SRP pin and either RSRP, GND bias.
Figure 8 shows the typical relation between switching speed and the external SRP resistor (RSRP).
Figure 8
Typical, simplified diagram representing the relation between RSRP and tON, tOFF; VDD = 5 V;
RLoad = 6.8 Ω, 10 Ω
Datasheet
13
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
4 Power stage
4.3.1
Output clamping
VBAT
VBAT
ZL
IL
OUT (DMOS Drain)
VOUT
GND ( DMOS Source)
IGND
Figure 9
Output clamp circuitry
VIN
t
IOUT
t
VOUT
VOUT(CLAMP)
VBAT
t
Figure 10
Switching an inductive load
When switching off inductive loads with low-side switches, the drain-source voltage VOUT rises above the battery
potential due to the inductance tendency to continue driving the current. To prevent unwanted high voltages the
device has a voltage clamping mechanism to keep the voltage at VOUT(CLAMP). During this clamping operation mode
the device heats up as it dissipates the energy from the inductance. Therefore the maximum allowed load inductance
is limited. See Figure 9 and Figure 10 for more details.
Note:
Repetitive switching of an inductive load by VDD instead of using the input pin IN is a not recommended
operation and may affect the device reliability and reduce the lifetime.
Datasheet
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
4 Power stage
4.3.2
Maximum load inductance
During the demagnetization of inductive loads, energy has to be dissipated by the device.
This energy can be calculated by (1):
VBAT − VOUT CLAMP
RL × IL
L
(1)
(2)
E = VOUT CLAMP
×
× ln 1 −
+ IL
×
RL
VBAT − VOUT CLAMP
RL
The (2) is simplified under the assumption of RL = 0:
VBAT
1
2
E
=
LIL × 1 −
2
VBAT − VOUT CLAMP
Figure 11 shows the inductance for a given current that the device BTT3050EJ can withstand.
For maximum single avalanche energy please refer to EAS parameter in Table 3.
Figure 11
Maximum load inductance for single pulse: L = f(IL); TJ(0) = 150°C; VBAT = 28 V
Datasheet
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Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
4 Power stage
4.4
Reverse current capability
A reverse battery situation means that the device’s drain is pulled below GND potential to -VBAT. In this situation
the load is driven by a current through the intrinsic body diode of BTT3050EJ and all protections, such as current
limitation, overtemperature or overvoltage clamping, are not active.
In inverse or reverse operation via the reverse body diode, the device is dissipating a power loss which is defined by
the driven current and the voltage drop on the body diode.
4.5
Characteristics
Please see Power stage for Electrical characteristics tables.
Datasheet
16
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
5 Diagnostics
5
Diagnostics
BTT3050EJ provides a latching digital fault feedback signal on the STATUS pin triggered by an overtemperature
shutdown.
VDD
RSTATUS
120W
Driver
STATUS
RSTATUS(int)
10KW
&
RDIAG(int)
ESD
Logic
GND
Figure 12
Simplified diagnosis circuit
Figure 12 shows the diagnosis circuit of BTT3050EJ. The circuit includes an ESD protection mechanism via a zener
structure. Note that RSTATUS(int) + RDIAG(int) = RSTATUS(LATCH)
.
5.1
Functional description of the STATUS pin
BTT3050EJ provides digital status information via the STATUS pin to give feedback to a connected microcontroller.
The readout of the diagnosis signal is only possible if the STATUS pin has a dedicated connection to the
microcontroller and the appropriate pull-up resistor RSTATUS is in place. See Figure 32 for recommended values of
the external components.
The device is able to operate via STATUS pin and IN pin connected together, however, this condition will inhibit the
readout of the diagnosis signal.
In normal operation (no thermal shutdown) the STATUS pin's logic is set "high". It is pulled up via an external resistor
(RSTATUS) to VDD.
Internally it is connected to an open drain MOSFET through an internal resistor.
In case of a thermal shutdown (fault) the internal MOSFET, connected to the STATUS pin, pulls its voltage down to
GND providing a "low" level signal to the microcontroller VSTATUS(LATCH)
.
Fault mode operation remains active independently from the INPUT pin state until it is reset.
To reset the latch fault signal of BTT3050EJ, the STATUS pin has to be externally pulled up. This behavior is shown in
Figure 15. For other configurations and how to reset the latch OFF of the DMOS, please see Reset latch condition.
5.2
Characteristics
Please see Diagnostics for Electrical characteristics tables.
Datasheet
17
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
6 Supply and input stage
6
Supply and input stage
VDD
RDD
Driver
&
ESD
Logic
IN
RIN
ESD
GND
Figure 13
Simplified supply and input circuit
Figure 13 shows the supply and input circuit of BTT3050EJ. Both terminals include an ESD protection mechanism via
a zener structure.
6.1
Supply circuit
The device's supply is not internally regulated but provided by an external supply. Therefore a reverse polarity
protected and buffered (3.3 V..5.5 V) voltage supply is required at VDD pin. To achieve the best RDS(ON) and the fastest
switching speed a 5 V supply is required.
6.1.1
Undervoltage shutdown
In order to ensure a stable device behavior under all allowed conditions the supply voltage VDD is monitored.
The output switches off if the supply voltage VDD drops below the switch-off threshold VDD(TH)L
.
If the supply voltage VDD drops below the supply voltage reset threshold VDD(RESET) a reset of the STATUS signal and the
latch-off state will occur.
The device functions are only given for supply voltages above the supply voltage threshold VDD(TH)H
.
6.1.2
Supply current consumption
The supply current consumption is determined by the state of the input voltage, being low, with the IDD(OFF) and being
high, with the IDD(ON)
.
Afer a thermal shutdown, when the device is in OFF latch mode, the current consumption values matches the normal
ON state IDD(ON) as long as input is high.
However in PWM the consumption depends on the switching frequency. The higher the frequency, the higher the
IDD(PWM)
.
Figure 14 shows the typical relation between the supply current consumption and the switching frequency
considering a duty-cycle of 50%.
Datasheet
18
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
6 Supply and input stage
Figure 14
Typical IDD(PWM) versus switching frequency at 50% duty cycle
6.2
Characteristics
Please see Supply and input stage for Electrical characteristics tables.
Datasheet
19
Rev. 1.00
2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
7 Protection functions
7
Protection functions
BTT3050EJ provides embedded protection functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in the datasheet. Fault conditions are considered as "outside"
normal operations. Protection functions are not to be used for continuous or repetitive operation. BTT3050EJ has
implemented a latched overtemperature shutdown function.
In the event of overtemperature shutdown the device will remain OFF until the latch is reset via STATUS pin.
7.1
Overvoltage clamping on output
BTT3050EJ limits the drain-source voltage VDS at a certain level VOUT(CLAMP)
.
The overvoltage clamping is overruling the other protection functions. Power dissipation has to be limited not to
exceed the maximum allowed junction temperature.
This function is also used in terms of inductive clamping. Please see also Output clamping for more details.
7.2
Thermal protection
The device is protected against overtemperature due to overload and/or bad cooling conditions by an integrated
temperature sensor.
The thermal protection is available when the device is active. In the event of overtemperature shutdown TJ(SD), the
device will remain OFF until the device is reset via STATUS pin.
Please see Figure 15 and Figure 16.
7.3
Overcurrent limitation and short circuit behavior
BTT3050EJ provides an overcurrent limitation intended to protect against short circuit or overcurrent conditions.
When the drain current reaches the current limitation level IL(LIM), the device will limit the current at that level.
While doing so, the power dissipation will heat up the device. Once the device reaches the overtemperature shutdown
threshold TJ(SD), it will automatically shutdown and remain OFF until it is reset via STATUS pin.
7.4
Reset latch condition
The reset of the latch OFF mode is done in two stages that need to be performed in the correct sequence.
During the first stage the voltage at the STATUS pin must be below the VSTATUS(RESET)L threshold for a time t
> tSTATUS(RESET)L
.
In the second stage of the reset sequence, the STATUS pin voltage needs to be pulled-up above the VSTATUS(RESET)H
threshold for a time t > tSTATUS(RESET)H
The total reset time needed is given by the sum of tSTATUS(RESET)L and tSTATUS(RESET)H
The following paragraphs explain more in detail the reset functionality in different conditions.
.
.
7.4.1
Reset via STATUS pin
If the temperature protection shutdowns the device, it will remain latched OFF independently of the input signal at IN
pin. Simultaneously, the STATUS pin signal will be signalized low VSTATUS(LATCH). In order to reset the latch condition,
the STATUS pin needs to remain below VSTATUS(RESET)L for a time t > tSTATUS(RESET)L before being externally pulled-up to
VSTATUS(RESET)H for a time t > tSTATUS(RESET)H
.
Please refer to Figure 15 and the application diagram in Figure 32.
This configuration allows the device to be driven with high frequency PWM signal via the IN pin without a risk of
resetting the device in case it goes in protection shutdown mode (latch OFF).
Datasheet
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
7 Protection functions
External pull-up
STATUS pin high
tSTATUS(RESET)H
tSTATUS(RESET)L
Overcurrent event
Thermal shutdown
No reset via IN
IN
t
VSTATUS
VSTATUS(RESET)H
VSTATUS(RESET)L
VSTATUS(LATCH)
t
ID, IL
Current limitation
IL(LIM)
t
TJ
TJ(SD)
t
VOUT
t
Total RESET time
Figure 15
Mechanism to reset latch condition via STATUS pin
7.4.2
Reset via STATUS pin and IN pin connected together
If STATUS and IN pins are connected together (no RSTATUS pull-up external resistor), the voltage provided through the
IN pin will prevent to signalize the STATUS low.
To reset the device under this condition, the STATUS – IN connection need to be pulled-down to VSTATUS(RESET)L for a
time t > tSTATUS(RESET)L before being pulled-up to VSTATUS(RESET)H for a time t > tSTATUS(RESET)H
.
Please refer to Figure 16 and the application diagram in Figure 33.
If no diagnosis of the device is required, this configuration avoids the need of a dedicated I/O from the microcontroller
for the STATUS pin. The maximum frequency allowed in PWM mode via IN pin preventing to reset the device is
constrained by the tSTATUS(RESET)L and tSTATUS(RESET)H times.
Datasheet
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
7 Protection functions
External pull-down
IN pin low
External pull-up
IN pin high
tSTATUS(RESET)H
tSTATUS(RESET)L
Overcurrent event
Thermal shutdown
VIN,
VSTATUS
VSTATUS(RESET)H
VSTATUS(RESET)L
t
ID, IL
Current limitation
IL(LIM)
t
TJ
TJ(SD)
t
t
VOUT
Total RESET time
Figure 16
Mechanism to reset latch condition with STATUS pin and IN pin connected together
Note:
For better understanding, the time scale is not linear. The real timing of this drawing is application
dependent and cannot be described.
7.5
Characteristics
Please see Protection for Electrical characteristic tables.
Datasheet
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
8 Electrical characteristics
8
Electrical characteristics
Please note that Electrical characteristics shows the deviation of a parameter at a given input voltage and junction
temperature. Typical values show the typical parameters expected from manufacturing and in typical application
condition. All voltages and currents naming and polarity in accordance to Figure 3.
8.1
Power stage
Please see Power stage for parameters description and further details.
Table 6 Power stage
TJ = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
Static characteristics
On-state resistance at RDS(ON)_5_25
–
–
–
–
50
63
mΩ
mΩ
mΩ
mΩ
IL = IL(NOM); VDD = 5 V; TJ = 25°C
PRQ-168
5 V supply and 25°C
On-state resistance at RDS(ON)_5_150
5 V supply and 150°C
85
100
78
IL = IL(NOM); VDD = 5 V; TJ = 150°C PRQ-169
On-state resistance at RDS(ON)_3_25
3 V supply and 25°C
63
IL = IL(NOM); VDD = 3 V; TJ = 25°C
PRQ-172
On-state resistance at RDS(ON)_3_150
3 V supply and 150°C
105
130
IL = IL(NOM); VDD = 3 V; TJ = 150°C PRQ-173
1) TJ < 150°C; TA = 85°C; VDD = 5 V PRQ-174
Nominal load current
IL(NOM)
–
–
4.0
0
–
1
A
OFF state load current, IL(OFF)_85
output leakage current
µA
2) TJ ≤ 85°C
PRQ-175
OFF state load current, IL(OFF)_150
Output leakage current
at 150°C
–
2
10
µA
V
TJ = 150°C
PRQ-176
Reverse diode
Reverse diode forward -VDS
voltage
–
0.6
1
VIN = 0 V
PRQ-177
Switching times. RSRP = short to GND; VBAT = 28 V; VDD = 5 V; RLoad = 10 Ω.
Turn-on delay time
tDON_5(0)
tDOFF_5(0)
tF_5(0)
1.2
1.0
0.5
2.7
2.8
1.4
6.8
5.5
2.5
µs
µs
µs
–
–
–
PRQ-178
PRQ-179
PRQ-180
Turn-off delay time
Turn-on output fall
time
Turn-off output rise
time
tR_5(0)
0.3
0.8
2.0
µs
–
PRQ-181
(table continues...)
Datasheet
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Rev. 1.00
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
8 Electrical characteristics
Table 6
(continued) Power stage
TJ = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
Switching times. RSRP = 5.8 KΩ; VBAT = 28 V; VDD = 5 V; RLoad = 10 Ω.
Turn-on delay time
tDON_5(5K8)
tDOFF_5(5K8)
tF_5(5K8)
1.7
1.4
1.1
3.1
4.5
2.1
6.9
7.6
3.6
µs
µs
µs
–
–
–
PRQ-182
PRQ-183
PRQ-184
Turn-off delay time
Turn-on output fall
time
Turn-off output rise
time
tR_5(5K8)
1.0
1.7
2.9
µs
–
PRQ-328
Switching times. RSRP = 58 KΩ; VBAT = 28 V; VDD = 5 V; RLoad = 10 Ω.
Turn-on delay time
tDON_5(58K)
tDOFF_5(58K)
tF_5(58K)
5.5
6.6
5.7
10.5 15.3 µs
20.4 40.9 µs
11.3 18.6 µs
PRQ-329
PRQ-330
PRQ-331
Turn-off delay time
Turn-on output fall
time
Turn-off output rise
time
tR_5(58K)
6.9
12.8 19.3 µs
PRQ-332
Switching times. RSRP = 1 MΩ; VBAT = 28 V; VDD = 5 V; RLoad = 10 Ω.
Turn-on delay time
tDON_5(1M)
tDOFF_5(1M)
tF_5(1M)
9.3
17.0 42.2 µs
–
–
–
PRQ-337
PRQ-338
PRQ-339
Turn-off delay time
10.4 44.2 139
µs
Turn-on output fall
time
8.9
26.7 64.7 µs
Turn-off output rise
time
tR_5(1M)
8.9
27.1 68.2 µs
–
PRQ-340
1)
2)
Not subject to production test, calculated by RthJA and RDS(ON)
Not subject to production test, specified by design
8.2
Protection
Please see Protection functions for parameter description and further details.
Note:
Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the datasheet. Fault conditions are considered as "outside" normal operating range. Protection functions
are not designed for continuous repetitive operation.
Datasheet
24
Rev. 1.00
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
8 Electrical characteristics
Table 7
Protection
TJ = -40°C to +150°C, VBAT = 28 V; all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
Thermal shutdown
1)
Thermal shutdown
TJ(SD)
150
–
175
4.5
200
–
°C
µs
V
= 5 V
PRQ-185
PRQ-189
DD
junction temperature
1)
Overtemperature
shutdown STATUS
delay at 5 V
tTJ(SD)5
Delay time to trigger STATUS
signal;
VDD = 5 V;
TAMB = 25°C
1)
Overtemperature
shutdown STATUS
delay at 3 V
tTJ(SD)3
–
4.2
–
µs
PRQ-191
Delay time to trigger STATUS
signal;
VDD = 3 V;
TAMB = 25°C
Overvoltage protection/clamping
Drain clamp voltage
VOUT(CLAMP)
63
10
72
16
83
22
V
A
VIN = 0 V; ID > 50 mA
PRQ-193
PRQ-196
Current limitation
2)
Current limitation level IL(LIM)_5
V
= 5 V
DD
1)
2)
Not subject to production test, specified by design
Parameter tested at VBAT = 5 V; specified up to VBAT = 36 V
8.3
Supply and input stage
Please see Supply and input stage for description and further details.
Table 8
Supply and input stage
TJ = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
Supply
Supply on threshold
voltage high
VDD(TH)H
VDD(TH)L
2.4
2.3
2.8
2.7
3
V
V
–
PRQ-202
PRQ-203
1)
Supply off threshold
voltage low
2.9
DMOS switches OFF below
threshold
(table continues...)
Datasheet
25
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
8 Electrical characteristics
Table 8
(continued) Supply and input stage
TJ = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
Supply current,
continuous ON
operation
IDD(ON)
–
150
250
µA
µA
ON-state; VDD = 5.5 V; VIN = 5 V; PRQ-206
IL(0) = IL(NOM)
2)
Standby supply current IDD(OFF)
–
0.3
3
V = 0 V; VDD = 5.5 V
IN
PRQ-212
Input
Input on threshold
voltage; 5.5 V supply
VIN(TH)H_5.5
1.9
1.2
1.2
0.7
20
2.4
1.5
1.5
1
2.8
1.8
1.8
1.2
80
V
VDD = 5.5 V
PRQ-213
PRQ-214
PRQ-219
PRQ-220
PRQ-222
Input off threshold
voltage; 5.5 V supply
VIN(TH)L_5.5
VIN(TH)H_3
VIN(TH)L_3
V
VDD = 5.5 V
Input on threshold
voltage; 3 V supply
V
VDD = 3 V
Input off threshold
voltage; 3 V supply
V
VDD = 3 V
Input pull down current IIN
45
µA
VIN ≤ 5.5 V; VDD ≤ 5.5 V
1)
2)
Undervoltage shutdown protection doesn't reset the OFF latch mode
Not subject to production test, specified by design
8.4
Diagnostics
Please see Diagnostics for parameters description and further details.
Table 9
Diagnostics
TJ = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
Diagnostics
6)
Status pin latch voltage VSTATUS(LATCH)
–
–
1
V
PRQ-227
1)
V
= 5 V; RSTATUS = 100
DD
kOhm; 3 V ≤ VIN ≤ 5 V; latched
fault signal
2)
Status pin reset
threshold low
VSTATUS(RESET)L_5
1
1.4
2.2
1.7
2.6
V
V
V
= 5 V
PRQ-228
PRQ-229
DD
3)
Status pin reset
threshold high
VSTATUS(RESET)H_5 1.7
tSTATUS(RESET)L_5
V = 5 V
DD
6) 4)
6) 5)
Status reset low time
1
1.6
35
2.4
70
ms
µs
V
V
= 5 V
= 5 V
PRQ-230
PRQ-231
DD
Status reset high time tSTATUS(RESET)H_5 20
DD
(table continues...)
Datasheet
26
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2022-01-18
HITFET™ +24V BTT3050EJ
Smart low-side power switch
8 Electrical characteristics
Table 9
(continued) Diagnostics
TJ = -40°C to +150°C, VBAT = 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit Note or condition
P-Number
Min. Typ. Max.
2)
Status pin reset
threshold low
VSTATUS(RESET)L_3 0.7
VSTATUS(RESET)H_3 1.2
tSTATUS(RESET)L_3 0.5
1
1.2
1.9
2.3
50
1
V
PRQ-232
PRQ-233
PRQ-234
PRQ-235
PRQ-236
VDD = 3 V
3)
Status pin reset
threshold high
1.6
1
V
VDD = 3 V
6) 4)
Status reset low time
ms
VDD = 3 V
6) 5)
Status reset high time tSTATUS(RESET)H_3
8
–
15
–
µs
VDD = 3 V
6)
Status pin leakage
current (no latch)
ISTATUS(NOLATCH)
µA
3 V ≤ VDD ≤ 5.5 V;
VSTATUS ≤ 5.5 V;
0 V ≤ VIN ≤ 5.5 V
Status pin internal
resistance (latch active)
RSTATUS(LATCH)
7
10
15
KΩ
RSTATUS(LATCH) = RSTATUS(int)
+ RDIAG(int)
PRQ-237
1)
Latch feedback signal voltage drop considering VDD = 5 V and RSTATUS = 100 kΩ.
2)
3)
4)
5)
6)
Voltage threshold needed at the STATUS pin to initialize the reset sequence of the latch OFF mode. If STATUS pin
and IN pin are connected together, same voltage threshold applies.
Voltage threshold needed at the STATUS pin to complete the reset sequence of the latch OFF mode. If STATUS
pin and IN pin are connected together, same voltage range applies.
Time needed to remain below VSTATUS(RESET)L to initialize the reset sequence of the latch OFF mode. See Chapter
6.4 for more information.
Time needed to remain above VSTATUS(RESET)H afer VSTATUS(RESET)L is applied to conlude the reset sequence.
See Chapter 6.4 for more information.
Not subject to production test, specified by design.
Datasheet
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Smart low-side power switch
9 Characterization results
9
Characterization results
Typical performance characteristics.
9.1
Power stage
Figure 17
Typical RDS(ON) vs. VDD; IL = IL(NOM); VIN = 3 V; VDD = 3.. 5.5 V; VBAT = 28 V; RSRP = 0 Ω
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Smart low-side power switch
9 Characterization results
Figure 18
Typical IL(OFF) vs. TJ at VIN = 0 V; VDD = 0 V, 5 V; VBAT = 28, 36, 58 V; TJ = -40, 25, 85, 105, 150°C
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 19
Typical destruction point EAS versus IL at TJ(0) = 150°C, VBAT = 28 V; IL(NOM), 2 x IL(NOM)
Figure 20
Typical EAR versus IL at TJ(0) = 25, 105°C, VBAT = 28 V; Nr. cycles = 20 Mio cycles; IL = IL(NOM), 2 x
IL(NOM)
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Smart low-side power switch
9 Characterization results
Figure 21
Typical EON and EOFF vs. RSRP at TA = 25°C, VDD = 3 V and 5.5 V; VBAT = 28 V; IN = 5 V; STATUS =
pulled-up to VDD; RLOAD = 6.8Ω
Dynamic characteristics
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 22
Typical tF, tR, tDON, tDOFF versus RSRP at VIN = 5 V; VDD = 5 V; VBAT = 28 V; RL= 6.8 Ω, 10 Ω; RSRP
=
(0 kΩ, 2.2 kΩ,5.8 kΩ, 10 kΩ,58 kΩ, 160 kΩ, open); TJ = -40 .. 150°C
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 23
Typical tF, tR, tDON, tDOFF versus RSRP at VIN = 3 V; VDD = 3 V; VBAT = 28 V; RL = 6.8 Ω, 10 Ω; RSRP
=
(0 kΩ, 2.2 kΩ, 5.8 kΩ, 10 kΩ,58 kΩ, 160 kΩ, open); TJ = -40 .. 150°C
Datasheet
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Smart low-side power switch
9 Characterization results
9.2
Protection
Figure 24
Typical IL(LIM) versus VDD = 3, 6.5 V; VIN = 5 V; VBAT = 0 .. 63 V; TJ = -40, 25, 85, 105, 150°C
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 25
Typical time to shut down tTJ(SD) versus IL; VBAT= 28 V; VDD = 3.3, 5 V; VIN = 5 V; RthJA(2s2p)
Datasheet
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Smart low-side power switch
9 Characterization results
9.3
Supply and input stage
Figure 26
Typical VDD(TH) versus TJ at TJ = -40 .. 150°C; VDD(TH)H and VDD(TH)L; VIN = 3 V; RLOAD = 150 kΩ;
RSRP = GND; VBAT = 28 V
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 27
Typical IDD(ON) versus RSRP at TJ = -40 .. 150°C, IL = IL(NOM); VIN = 3 V; VDD = 5 V; VBAT = 28
V; RSRP = GND
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 28
Typical IDD(ON) versus VDD at VDD = 3 .. 6.5 V; TJ = -40 .. 150°C; IL = IL(NOM); VIN = 3 V; VBAT = 28 V;
RSRP = GND
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 29
Typical IDD(LIM) versus VDD at VDD = 3 .. 6.5 V; TJ = -40 .. 150°C; VIN = 3 V; RSRP = GND; VBAT = 5 V
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 30
Typical VIN(TH) versus VDD VIN(TH)H and VIN(TH)L ; VDD = 3 .. 6.5 V; TJ =-40 ... 150°C; RLOAD = 150
kΩ; RSRP = GND; VBAT = 28 V
Datasheet
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Smart low-side power switch
9 Characterization results
Figure 31
Typical ITjSD versus VDD at VIN = 3 .. 5.5 V; VDD = 3, 6.5 V; IL = IL(NOM); VBAT = 28 V
Datasheet
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Smart low-side power switch
10 Application information
10
Application information
10.1
Layout recommendations and considerations
As consequences of the fast switching times for high currents (INOM and above), special care has to be taken to the
PCB layout. Stray inductances have to be minimized, as BTT3050EJ has no separate pin for power ground and logic
ground. Therefore, it is recommended:
•
To ensure that the offset between the ground connection of the SRP resistor and ground pins of the device
is minimized. RSRP should be placed next to the device and directly connected to the GND pins, to avoid any
influence of GND shif to SRP functionality.
•
To ensure that the offset between the ground of the VDD supply and the ground of the pins of the device is
minimized.
The maximum parasitic capacitance between the SRP line and GND (CSRP) has to be less than 10 pF to avoid any
influence on SRP functionality (e.g. switching times).
10.2
Application diagrams
Note:
The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Recommended values for VIN = VDD = 5 V: RSTATUS = 100 kΩ.
Table 10
RSRP switching modes
RSRP_min
RSRP_max Unit
Behavior
0
2.2
kΩ
kΩ
kΩ
Fast switching mode. SRP pin can be connected to GND.
Adjustable switching mode
Slow switching mode
2.2
160
160
1000
For switching timings, please refer to Power stage.
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10 Application information
VBAT
IN
Load
Voltage Regulator
OUT
CVDD optional:
e.g. 100nF
VDD
VDD
RSTATUS
BTT3050EJ
Micro
controller
OUT
STATUS
I/O
Status/ Reset
IC Logic
IN
I/O
PWM
SRP
GND
RSRP
GND
App_01
Figure 32
Application diagram to use IN pin and STATUS pin independently
Datasheet
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Smart low-side power switch
10 Application information
VBAT
IN
IN
Load
Voltage Regulator 01
Voltage Regulator 02
OUT
OUT
CVDD optional:
e.g. 100nF
VDD
VDD
BTT3050EJ
Micro
controller
OUT
STATUS
I/O
Status/ Reset
IC Logic
IN
I/O
PWM
SRP
GND
RSRP
GND
App_03
Figure 33
Application diagram to use IN pin and STATUS pin simultaneously with different supply and
microcontroller voltage class
Example given for VIN = 3.3 V; VDD = 5 V allows to maintain an optimal RDS(ON) while driving the input with a 3.3 V
microcontroller. This configuration does not make possible the readout of the fault signal and will reset the latch OFF
via IN pin (see parameters in Diagnostics ).
For RSRP recommended values, please see Table 10.
Note:
This are very simplified examples of an application circuit. The function must be verified in the real
application.
Datasheet
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Smart low-side power switch
11 Package
11
Package
Figure 34
PG-TDSO-8
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free
finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Datasheet
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HITFET™ +24V BTT3050EJ
Smart low-side power switch
Revision history
Revision history
Document
version
Date of
release
Description of changes
Rev.1.00
2022-01-18
•
Datasheet creation
Datasheet
46
Rev. 1.00
2022-01-18
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2022-01-18
Published by
Infineon Technologies AG
81726 Munich, Germany
IMPORTANT NOTICE
WARNINGS
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
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In addition, any information given in this document is
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in question please contact your nearest Infineon
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All Rights Reserved.
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Document reference
IFX-jxg1642157686944
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intended for technically trained staff. It is the
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application.
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