IPB031N08N5 [INFINEON]
Infineon’s OptiMOS™ 5 80V industrial power MOSFET IPB031N08N5 offers a RDS(on) reduction of 43% compared to previous generations and is ideally suited for high switching frequencies. The devices of this family are especially designed for synchronous rectification in telecom and server power supplies. In addition, they can also be utilized in other industrial applications such as solar, low voltage drives and adapters.;
| 型号： | IPB031N08N5 |
| 厂家： | 
Infineon |
| 描述： | Infineon’s OptiMOS™ 5 80V industrial power MOSFET IPB031N08N5 offers a RDS(on) reduction of 43% compared to previous generations and is ideally suited for high switching frequencies. The devices of this family are especially designed for synchronous rectification in telecom and server power supplies. In addition, they can also be utilized in other industrial applications such as solar, low voltage drives and adapters. |
| 文件： | 总12页 (文件大小：1162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET
MetalꢀOxideꢀSemiconductorꢀFieldꢀEffectꢀTransistor
OptiMOSTM
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
DataꢀSheet
Rev.ꢀ2.0
Final
PowerꢀManagementꢀ&ꢀMultimarket
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
D²PAK
1ꢀꢀꢀꢀꢀDescription
Features
•ꢀIdealꢀforꢀhighꢀfrequencyꢀswitchingꢀandꢀsync.ꢀrec.
•ꢀExcellentꢀgateꢀchargeꢀxꢀRDS(on)ꢀproductꢀ(FOM)
•ꢀVeryꢀlowꢀon-resistanceꢀꢀRDS(on)
•ꢀN-channel,ꢀnormalꢀlevel
•ꢀ100%ꢀavalancheꢀtested
•ꢀPb-freeꢀplating;ꢀRoHSꢀcompliant
•ꢀQualifiedꢀaccordingꢀtoꢀJEDEC1)ꢀꢀforꢀtargetꢀapplications
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
Drain
Pin 2, Tab
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Parameter
Value
Unit
VDS
80
V
Gate
Pin 1
RDS(on),max
ID
3.1
120
82
mΩ
A
Source
Pin 3
Qoss
nC
nC
QG(0V..10V)
69
Typeꢀ/ꢀOrderingꢀCode
Package
Marking
RelatedꢀLinks
IPB031N08N5
PG-TO 263-3
031N08N5
-
1) J-STD20 and JESD22
Final Data Sheet
2
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
TableꢀofꢀContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Final Data Sheet
3
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
2ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀTjꢀ=ꢀ25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
Max.
-
-
-
-
120
116
TC=25ꢀ°C
A
Continuous drain current
ID
TC=100ꢀ°C
Pulsed drain current1)
Avalanche energy, single pulse2)
Gate source voltage
ID,pulse
EAS
-
-
-
-
-
480
186
20
A
TC=25ꢀ°C
-
mJ
V
ID=100ꢀA,ꢀRGS=25ꢀΩ
VGS
Ptot
-20
-
-
Power dissipation
167
W
TC=25ꢀ°C
IEC climatic category;
DIN IEC 68-1: 55/175/56
Operating and storage temperature
Tj,ꢀTstg
-55
-
175
°C
3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
0.7
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction - case
RthJC
RthJA
-
0.9
K/W
K/W
-
-
Thermal resistance, junction - ambient,
minimal footprint
-
-
-
-
-
-
62
Thermal resistance, junction - ambient,
6 cm2 cooling area3)
RthJA
Tsold
40
K/W
°C
-
Soldering temperature, wave and
reflow soldering are allowed
260
reflow MSL1
1) See figure 3 for more detailed information
2) See figure 13 for more detailed information
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.
PCB is vertical in still air.
Final Data Sheet
4
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
80
Typ.
-
Max.
-
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS
VGS(th)
V
V
VGS=0ꢀV,ꢀID=1ꢀmA
2.2
3.0
3.8
VDS=VGS,ꢀID=108ꢀµA
-
-
0.1
10
1
100
VDS=80ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C
VDS=80ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
IDSS
µA
nA
IGSS
-
1
100
VGS=20ꢀV,ꢀVDS=0ꢀV
-
-
2.7
3.6
3.1
4.1
VGS=10ꢀV,ꢀID=100ꢀA
VGS=6ꢀV,ꢀID=50ꢀA
RDS(on)
mΩ
Gate resistance1)
Transconductance
RG
gfs
-
1.5
2.3
-
Ω
-
76
152
S
|VDS|>2|ID|RDS(on)max,ꢀID=100ꢀA
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics1)ꢀ
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance
Ciss
Coss
Crss
-
-
-
4800 6240 pF
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz
Output capacitance
790
36
1030 pF
Reverse transfer capacitance
63
-
pF
ns
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.6ꢀΩ
Turn-on delay time
Rise time
td(on)
tr
td(off)
tf
-
-
-
-
18
18
37
12
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.6ꢀΩ
-
-
-
ns
ns
ns
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.6ꢀΩ
Turn-off delay time
Fall time
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,
RG,ext=1.6ꢀΩ
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ
Values
Typ.
24
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate to drain charge1)
Switching charge
Qgs
-
-
-
-
-
-
-
-
nC
nC
nC
nC
V
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDS=0.1ꢀV,ꢀVGS=0ꢀtoꢀ10ꢀV
Qgd
15
23
-
Qsw
26
Gate charge total1)
Qg
69
87
-
Gate plateau voltage
Gate charge total, sync. FET
Output charge1)
Vplateau
Qg(sync)
Qoss
5.0
60
-
nC
nC
82
110
VDD=40ꢀV,ꢀVGS=0ꢀV
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
5
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
-
Max.
120
480
1.2
Diode continous forward current
Diode pulse current
IS
-
-
-
-
-
A
TC=25ꢀ°C
IS,pulse
VSD
trr
-
A
TC=25ꢀ°C
Diode forward voltage
0.94
73
V
VGS=0ꢀV,ꢀIF=100ꢀA,ꢀTj=25ꢀ°C
VR=40ꢀV,ꢀIF=100A,ꢀdiF/dt=100ꢀA/µs
VR=40ꢀV,ꢀIF=100A,ꢀdiF/dt=100ꢀA/µs
Reverse recovery time1)
Reverse recovery charge1)
146
332
ns
nC
Qrr
166
1) Defined by design. Not subject to production test.
Final Data Sheet
6
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
5ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
200
140
120
100
80
160
120
80
40
0
60
40
20
0
0
50
100
150
200
0
50
100
150
200
TCꢀ[°C]
TCꢀ[°C]
Ptot=f(TC)
ID=f(TC);ꢀVGS≥10ꢀV
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
103
100
1 µs
10 µs
0.5
100 µs
102
101
100
10-1
0.2
0.1
1 ms
10-1
0.05
0.02
10 ms
DC
0.01
single pulse
10-2
10-1
100
101
102
10-5
10-4
10-3
10-2
10-1
100
VDSꢀ[V]
tpꢀ[s]
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T
Final Data Sheet
7
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
480
6
5.5 V
5 V
6 V
7 V
10 V
440
400
360
320
280
240
200
160
120
80
5
4
3
2
1
0
7 V
6 V
10 V
5.5 V
5 V
40
0
0
1
2
3
4
5
0
100
200
300
400
500
VDSꢀ[V]
IDꢀ[A]
ID=f(VDS);ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
RDS(on)=f(ID);ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀforwardꢀtransconductance
400
200
350
300
250
200
150
150
100
50
100
175 °C
25 °C
50
0
0
0
2
4
6
8
0
40
80
120
160
VGSꢀ[V]
IDꢀ[A]
ID=f(VGS);ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj
gfs=f(ID);ꢀTj=25ꢀ°C
Final Data Sheet
8
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
Diagramꢀ9:ꢀDrain-sourceꢀon-stateꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
7
4.0
3.5
6
5
1080 µA
3.0
108 µA
2.5
max
4
2.0
1.5
1.0
0.5
0.0
typ
3
2
1
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
Tjꢀ[°C]
Tjꢀ[°C]
RDS(on)=f(Tj);ꢀID=100ꢀA;ꢀVGS=10ꢀV
VGS(th)=f(Tj);ꢀVGS=VDS;ꢀparameter:ꢀID
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
104
103
25 °C
175 °C
Ciss
25 °C, max
175 °C, max
Coss
103
102
101
100
Crss
102
101
0
20
40
60
80
0.0
0.5
1.0
1.5
2.0
2.5
VDSꢀ[V]
VSDꢀ[V]
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz
IF=f(VSD);ꢀparameter:ꢀTj
Final Data Sheet
9
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
103
10
40 V
8
6
4
2
0
102
101
100
25 °C
20 V
60 V
100 °C
150 °C
100
101
102
103
0
20
40
60
80
tAVꢀ[µs]
Qgateꢀ[nC]
IAS=f(tAV);ꢀRGS=25ꢀΩ;ꢀparameter:ꢀTj(start)
VGS=f(Qgate);ꢀID=100ꢀAꢀpulsed;ꢀparameter:ꢀVDD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Gate charge waveforms
90
85
80
75
-60
-20
20
60
100
140
180
Tjꢀ[°C]
VBR(DSS)=f(Tj);ꢀID=1ꢀmA
Final Data Sheet
10
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
6ꢀꢀꢀꢀꢀPackageꢀOutlines
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TOꢀ263-3,ꢀdimensionsꢀinꢀmm/inches
Final Data Sheet
11
Rev.ꢀ2.0,ꢀꢀ2014-12-17
OptiMOSª5ꢀPower-Transistor,ꢀ80ꢀV
IPB031N08N5
RevisionꢀHistory
IPB031N08N5
Revision:ꢀ2014-12-17,ꢀRev.ꢀ2.0
Previous Revision
Revision Date
2.0
Subjects (major changes since last revision)
Release of final version
2014-12-17
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aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
12
Rev.ꢀ2.0,ꢀꢀ2014-12-17
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INFINEON
IPB033N10N5LF
OptiMOS™线性FET是一种全新方法，实现了增强型MOSFET饱和区域内的导通电阻（R DS（on） ）和线性模式能力的出色平衡。它提供先进的沟槽栅MOSFET R DS（on）以及经典平面MOSFET的宽安全工作区。
INFINEON
IPB034N06L3GATMA1
Power Field-Effect Transistor, 90A I(D), 60V, 0.0034ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, GREEN, PLASTIC, TO-263, D2PAK-3
INFINEON
IPB034N06L3GXT
Power Field-Effect Transistor, 90A I(D), 60V, 0.0034ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, GREEN, PLASTIC, TO-263, D2PAK-3
INFINEON
IPB034N06N3GATMA1
Power Field-Effect Transistor, 100A I(D), 60V, 0.0034ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, GREEN, PLASTIC, TO-263, D2PAK-7
INFINEON
IPB036N12N3 G
120V OptiMOS™ 系列提供业内最低导通电阻和最快开关性能，适用于各种应用，支持实现卓越性能。120V OptiMOS™ 技术带来全新可能性，帮助实现优化解决方案。
INFINEON
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