IPD04N03LA [INFINEON]
OptiMOS 2 Power-Transistor; 的OptiMOS 2功率三极管
| 型号： | IPD04N03LA |
| 厂家： | 
Infineon |
| 描述： | OptiMOS 2 Power-Transistor |
| 文件： | 总10页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IPD04N03LA
IPU04N03LA
OptiMOS®2 Power-Transistor
Product Summary
Features
V DS
25
3.8
50
V
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target applications
R
DS(on),max (SMD version)
mΩ
A
I D
• N-channel
• Logic level
• Excellent gate charge x R DS(on) product (FOM)
P-TO252-3-11
P-TO251-3-21
• Very low on-resistance R DS(on)
• Superior thermal resistance
• 175 °C operating temperature
• dv /dt rated
Type
Package
Ordering Code Marking
IPD04N03LA
IPU04N03LA
P-TO252-3-11
P-TO251-3-21
Q67042-S4177
Q67042-S4198
04N03LA
04N03LA
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol Conditions
Unit
T C=25 °C2)
I D
Continuous drain current
50
50
A
T C=100 °C
T C=25 °C3)
I D,pulse
Pulsed drain current
350
890
E AS
I D=40 A, R GS=25 Ω
Avalanche energy, single pulse
mJ
I D=50 A, V DS=20 V,
di /dt =200 A/µs,
Reverse diode dv /dt
dv /dt
6
kV/µs
T
j,max=175 °C
Gate source voltage4)
V GS
±20
V
P tot
T C=25 °C
Power dissipation
115
W
°C
T j, T stg
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-55 ... 175
55/175/56
1) J-STD20 and JESD22
Rev. 1.5
page 1
2004-02-04
IPD04N03LA
IPU04N03LA
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Thermal characteristics
R thJC
Thermal resistance, junction - case
SMD version, device on PCB
-
-
-
-
-
-
1.3
75
50
K/W
R thJA
minimal footprint
6 cm2 cooling area5)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS
V GS(th)
V
V
GS=0 V, I D=1 mA
DS=V GS, I D=80 µA
Drain-source breakdown voltage
Gate threshold voltage
25
-
-
V
1.2
1.6
2
V
DS=25 V, V GS=0 V,
I DSS
Zero gate voltage drain current
-
-
0.1
10
1
µA
T j=25 °C
V
DS=25 V, V GS=0 V,
100
T j=125 °C
I GSS
V
V
GS=20 V, V DS=0 V
GS=4.5 V, I D=50 A
Gate-source leakage current
-
-
10
100 nA
R DS(on)
Drain-source on-state resistance
4.8
5.9
5.7
4.0
3.8
-
mΩ
V
GS=4.5 V, I D=50 A,
-
-
4.6
3.4
3.2
1.3
96
SMD version
V
GS=10 V, I D=50 A
V
GS=10 V, I D=50 A,
-
SMD version
R G
g fs
Gate resistance
-
Ω
|V DS|>2|I D|R DS(on)max
I D=50 A
,
Transconductance
48
-
S
2) Current is limited by bondwire; with an R thJC=1.3 K/W the chip is able to carry 136 A.
3) See figure 3
4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.5
page 2
2004-02-04
IPD04N03LA
IPU04N03LA
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Dynamic characteristics
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C iss
-
-
-
-
-
-
-
3909
1488
174
14
5199 pF
1979
V
GS=0 V, V DS=15 V,
C oss
Crss
t d(on)
t r
f =1 MHz
261
21
16
66
10
ns
11
V
DD=15 V, V GS=10 V,
I D=25 A, R G=2.7 Ω
t d(off)
t f
Turn-off delay time
Fall time
44
6.6
Gate Charge Characteristics6)
Gate to source charge
Gate charge at threshold
Gate to drain charge
Switching charge
Q gs
-
-
-
-
-
-
12
6.3
8.1
14
16
8.3
12
19
41
-
nC
Q g(th)
Q gd
V
V
DD=15 V, I D=25 A,
GS=0 to 5 V
Q sw
Q g
Gate charge total
31
V plateau
Gate plateau voltage
3.0
V
V
V
DS=0.1 V,
Q g(sync)
Q oss
Gate charge total, sync. FET
Output charge
-
-
28
32
37
43
nC
GS=0 to 5 V
V
DD=15 V, V GS=0 V
Reverse Diode
I S
Diode continous forward current
Diode pulse current
-
-
-
-
50
A
T C=25 °C
I S,pulse
350
V
GS=0 V, I F=50 A,
V SD
Q rr
Diode forward voltage
-
-
0.89
-
1.2
15
V
T j=25 °C
V R=15 V, I F=I S,
di F/dt =400 A/µs
Reverse recovery charge
nC
6) See figure 16 for gate charge parameter definition
Rev. 1.5
page 3
2004-02-04
IPD04N03LA
IPU04N03LA
1 Power dissipation
2 Drain current
P tot=f(T C)
I D=f(T C); V GS≥10 V
140
120
100
80
60
50
40
30
20
10
0
60
40
20
0
0
50
100
150
200
0
50
100
150
200
T
C [°C]
T
C [°C]
3 Safe operation area
I D=f(V DS); T C=25 °C; D =0
parameter: t p
4 Max. transient thermal impedance
thJC=f(t p)
Z
parameter: D =t p/T
1000
10
1 µs
limited by on-state
resistance
10 µs
1
0.5
100 µs
100
0.2
0.1
DC
1 ms
0.1
0.05
0.02
10
1
0.01
single pulse
10 ms
0.01
0
0
0
0
0
0
1
0.001
0.1
1
10
100
10-6
10-5
10-4
10-3
t p [s]
10-2
10-1
100
V
DS [V]
Rev. 1.5
page 4
2004-02-04
IPD04N03LA
IPU04N03LA
5 Typ. output characteristics
I D=f(V DS); T j=25 °C
6 Typ. drain-source on resistance
DS(on)=f(I D); T j=25 °C
R
parameter: V GS
parameter: V GS
16
120
2.8 V
3.6 V
3 V
3.4 V
3.2 V
3.8 V
4.5 V
10 V
14
12
10
8
3.8 V
3.6 V
100
80
60
40
20
0
3.4 V
3.2 V
6
4.5 V
10 V
4
3 V
2
2.8 V
0
0
20
40
60
80
100
0
1
2
3
V
DS [V]
I
D [A]
7 Typ. transfer characteristics
I D=f(V GS); |V DS|>2|I D|R DS(on)max
parameter: T j
8 Typ. forward transconductance
g fs=f(I D); T j=25 °C
100
120
100
80
60
40
20
0
80
60
40
20
175 °C
25 °C
0
0
1
2
3
4
5
0
10
20
30
40
50
60
I
D [A]
V
GS [V]
Rev. 1.5
page 5
2004-02-04
IPD04N03LA
IPU04N03LA
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
GS(th)=f(T j); V GS=V DS
R
DS(on)=f(T j); I D=50 A; V GS=10 V
V
parameter: I D
8
7
6
2.5
2
1.5
1
800 µA
5
98 %
80 µA
4
typ
3
2
1
0
0.5
0
-60
-20
20
60
100
140
180
-60
-20
20
60
T j [°C]
100
140
180
T j [°C]
11 Typ. capacitances
12 Forward characteristics of reverse diode
I F=f(V SD
C =f(V DS); V GS=0 V; f =1 MHz
)
parameter: T j
10000
1000
25 °C, 98%
Ciss
100
10
25 °C
175 °C, 98%
Coss
175 °C
1000
Crss
100
1
0
5
10
15
DS [V]
20
25
30
0.0
0.5
1.0
SD [V]
1.5
2.0
V
V
Rev. 1.5
page 6
2004-02-04
IPD04N03LA
IPU04N03LA
13 Avalanche characteristics
AS=f(t AV); R GS=25 Ω
14 Typ. gate charge
GS=f(Q gate); I D=25 A pulsed
V
I
parameter: Tj(start)
parameter: V DD
100
12
25 °C
15 V
20 V
10
8
100 °C
5 V
150 °C
10
6
4
2
1
1
0
0
10
100
1000
20
40
gate [nC]
60
80
Q
t
AV [µs]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V
BR(DSS)=f(T j); I D=1 mA
29
28
27
26
25
24
23
22
21
20
V GS
Q g
V gs(th)
Q g(th)
Q sw
Q gd
Q gate
Q gs
-60
-20
20
60
100
140
180
T j [°C]
Rev. 1.5
page 7
2004-02-04
IPD04N03LA
IPU04N03LA
Package Outline
P-TO252-3-11: Outline
Footprint:
Packaging:
Dimensions in mm
Rev. 1.5
page 8
2004-02-04
IPD04N03LA
IPU04N03LA
Package Outline
P-TO251-3-21: Outline
Dimensions in inch [mm]
Rev. 1.5
page 9
2004-02-04
IPD04N03LA
IPU04N03LA
Published by
Infineon Technologies AG
Bereich Kommunikation
St.-Martin-Straße 53
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as
warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts started herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices, please contact your
nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide
(see address list).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact your nearest Infineon Technologies office.
Infineon Technologies' components may only be used in life-support devices or systems with the
expressed written approval of Infineon Technologies if a failure of such components can reasonably
be expected to cause the failure of that life-support device or system, or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,
it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.5
page 10
2004-02-04
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