IPP13N03LBG_08 [INFINEON]

OptiMOS2 Power-Transistor; OptiMOS2功率三极管
IPP13N03LBG_08
型号: IPP13N03LBG_08
厂家: Infineon    Infineon
描述:

OptiMOS2 Power-Transistor
OptiMOS2功率三极管

文件: 总9页 (文件大小:272K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IPP13N03LB G  
OptiMOS®2 Power-Transistor  
Product Summary  
Features  
V DS  
30  
12.8  
30  
V
• Ideal for high-frequency dc/dc converters  
• Qualified according to JEDEC1) for target application  
R DS(on),max  
I D  
m  
A
• N-channel - Logic level  
• Excellent gate charge x R DS(on) product (FOM)  
• Very low on-resistance R DS(on)  
PG-TO220-3-1  
• Superior thermal resistance  
• 175 °C operating temperature  
• dv /dt rated  
• Pb-free lead plating; RoHS compliant  
Type  
Package  
Marking  
IPP13N03LB G  
PG-TO220-3-1  
13N03LB  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
T C=25 °C2)  
I D  
Continuous drain current  
30  
30  
A
T C=100 °C  
T C=25 °C3)  
I D,pulse  
Pulsed drain current  
120  
64  
E AS  
I D=30 A, R GS=25 Ω  
Avalanche energy, single pulse  
mJ  
I D=30 A, V DS=20 V,  
di /dt =200 A/µs,  
Reverse diode dv /dt  
dv /dt  
6
kV/µs  
T
j,max=175 °C  
Gate source voltage4)  
V GS  
±20  
52  
V
P tot  
T C=25 °C  
Power dissipation  
W
°C  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... 175  
55/175/56  
1) J-STD20 and JESD22  
Rev. 0.95  
page 1  
2008-05-06  
IPP13N03LB G  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Thermal characteristics  
R thJC  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
2.9  
62  
40  
K/W  
R thJA  
minimal footprint  
6 cm2 cooling area5)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS  
V GS(th)  
V
V
GS=0 V, I D=1 mA  
DS=V GS, I D=20 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
30  
-
-
V
1.2  
1.6  
2
V
DS=30 V, V GS=0 V,  
I DSS  
Zero gate voltage drain current  
-
-
0.1  
10  
1
µA  
T j=25 °C  
V
DS=30 V, V GS=0 V,  
100  
T j=125 °C  
I GSS  
V
V
V
GS=20 V, V DS=0 V  
GS=4.5 V, I D=20 A  
GS=10 V, I D=30 A  
Gate-source leakage current  
-
-
-
-
1
100 nA  
R DS(on)  
Drain-source on-state resistance  
15.2  
10.7  
1
18.9  
12.8  
-
mΩ  
R G  
g fs  
Gate resistance  
|V DS|>2|I D|R DS(on)max  
I D=60 A  
,
Transconductance  
57  
-
S
2) Current is limited by bondwire; with anR thJC=2.9 K/W the chip is able to carry 47 A.  
3) See figure 3  
4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V  
2
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
5 Diagrams are related to straight lead versions.  
Rev. 0.95  
page 2  
2008-05-06  
IPP13N03LB G  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Dynamic characteristics  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
-
-
-
-
-
-
-
1019  
364  
49  
1355 pF  
485  
V
GS=0 V, V DS=15 V,  
C oss  
Crss  
t d(on)  
t r  
f =1 MHz  
74  
4
7
6
ns  
4
V
DD=15 V, V GS=10 V,  
I D=20 A, R G=2.7 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
16  
24  
4.2  
2.8  
Gate Charge Characteristics6)  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge  
Switching charge  
Q gs  
-
-
-
-
-
-
4.0  
1.6  
2.3  
5
5
2.2  
3.5  
7
nC  
Q g(th)  
Q gd  
V
V
DD=15 V, I D=40 A,  
GS=0 to 5 V  
Q sw  
Q g  
Gate charge total  
8
10  
-
V plateau  
Gate plateau voltage  
3.9  
V
V
V
DS=0.1 V,  
Q g(sync)  
Q oss  
Gate charge total, sync. FET  
Output charge  
-
-
7
8
9
nC  
GS=0 to 5 V  
V
DD=15 V, V GS=0 V  
11  
Reverse Diode  
I S  
Diode continous forward current  
Diode pulse current  
-
-
-
-
78  
A
T C=25 °C  
I S,pulse  
120  
V
GS=0 V, I F=80 A,  
V SD  
Q rr  
Diode forward voltage  
-
-
1.23  
-
1.2  
10  
V
T j=25 °C  
V R=15 V, I F=I S,  
di F/dt =400 A/µs  
Reverse recovery charge  
nC  
6) See figure 16 for gate charge parameter definition  
Rev. 0.95  
page 3  
2008-05-06  
IPP13N03LB G  
1 Power dissipation  
2 Drain current  
P
tot=f(T C)  
I D=f(T C); V GS10 V  
60  
50  
40  
30  
20  
10  
40  
30  
20  
10  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
I D=f(V DS); T C=25 °C; D =0  
parameter: t p  
4 Max. transient thermal impedance  
thJC=f(t p)  
Z
parameter: D =t p/T  
1000  
10  
0.5  
1
0.2  
1 µs  
limited by on-state  
resistance  
100  
0.1  
10 µs  
0.05  
0.02  
0.1  
single pulse  
0.01  
100 µs  
DC  
10  
1 ms  
10 ms  
0.01  
1
0.001  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
0
t
p [s]  
V
DS [V]  
Rev. 0.95  
page 4  
2008-05-06  
IPP13N03LB G  
5 Typ. output characteristics  
I D=f(V DS); T j=25 °C  
6 Typ. drain-source on resistance  
DS(on)=f(I D); T j=25 °C  
R
parameter: V GS  
parameter: V GS  
100  
100  
3.2 V  
3 V  
3.8 V  
4.1 V  
4.5 V  
10 V  
90  
90  
2.8 V  
80  
70  
60  
50  
40  
30  
20  
10  
80  
70  
60  
50  
40  
30  
20  
10  
0
4.5 V  
4.1 V  
3.8 V  
3.5 V  
3.2 V  
10 V  
3 V  
2.8 V  
0
0
20  
40  
60  
80  
100  
0
1
2
3
V
DS [V]  
I
D [A]  
7 Typ. transfer characteristics  
I D=f(V GS); |V DS|>2|I D|R DS(on)max  
parameter: T j  
8 Typ. forward transconductance  
g fs=f(I D); T j=25 °C  
70  
60  
50  
40  
30  
20  
10  
0
100  
80  
60  
40  
20  
175 °C  
25 °C  
0
0
1
2
3
4
5
0
20  
40  
60  
80  
I
D [A]  
V
GS [V]  
Rev. 0.95  
page 5  
2008-05-06  
IPP13N03LB G  
9 Drain-source on-state resistance  
10 Typ. gate threshold voltage  
GS(th)=f(T j); V GS=V DS  
R
DS(on)=f(T j); I D=50 A; V GS=10 V  
V
parameter: I D  
2.5  
24  
22  
20  
18  
2
1.5  
1
200 µA  
16  
98 %  
14  
12  
20 µA  
typ  
10  
8
6
0.5  
4
2
0
0
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
11 Typ. Capacitances  
12 Forward characteristics of reverse diode  
I F=f(V SD  
C =f(V DS); V GS=0 V; f =1 MHz  
)
parameter: T j  
10000  
1000  
Ciss  
1000  
100  
10  
100  
10  
175 °C  
25 °C  
175°C 98%  
Coss  
25°C 98%  
Crss  
1
0
5
10  
15  
20  
25  
30  
0.0  
0.5  
1.0  
SD [V]  
1.5  
2.0  
V
DS [V]  
V
Rev. 0.95  
page 6  
2008-05-06  
IPP13N03LB G  
13 Avalanche characteristics  
AS=f(t AV); R GS=25 Ω  
14 Typ. gate charge  
GS=f(Q gate); I D=40 A pulsed  
V
I
parameter: Tj(start)  
parameter: V DD  
100  
12  
15 V  
10  
8
5 V  
20 V  
25 °C  
100 °C  
150 °C  
10  
6
4
2
1
1
0
0
10  
100  
1000  
10  
gate [nC]  
20  
Q
t
AV [µs]  
15 Drain-source breakdown voltage  
16 Gate charge waveforms  
V
BR(DSS)=f(T j); I D=1 mA  
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
V GS  
Q g  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
Rev. 0.95  
page 7  
2008-05-06  
IPP13N03LB G  
PG-TO220-3-1  
Rev. 0.95  
page 8  
2008-05-06  
IPP13N03LB G  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© 2008 Infineon Technologies AG  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of  
conditions or characteristics. With respect to any examples or hints given herein, any typical  
values stated herein and/or any information regarding the application of the device,  
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,  
including without limitation, warranties of non-infringement of intellectual property rights  
of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please  
contact the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances. For information  
on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with  
the express written approval of Infineon Technologies, if a failure of such components can  
reasonably be expected to cause the failure of that life-support device or system or to affect  
the safety or effectiveness of that device or system. Life support devices or systems are  
intended to be implanted in the human body or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user  
or other persons may be endangered.  
Rev. 0.95  
page 9  
2008-05-06  

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