IPTC014N10NM5 [INFINEON]

IPTC014N10NM5 属于TOLT 封装 OptiMOS™ 5 功率 MOSFET 系列:采用 TO-Leaded 顶部散热封装,热性能优越。这种创新型封装结合了 OptiMOS™ 5 技术的主要特征,使英飞凌的 100 V 产品成为同类产品中的佼佼者 >300 A 而且可以为高功率密度设计提供高额定电流。;
IPTC014N10NM5
型号: IPTC014N10NM5
厂家: Infineon    Infineon
描述:

IPTC014N10NM5 属于TOLT 封装 OptiMOS™ 5 功率 MOSFET 系列:采用 TO-Leaded 顶部散热封装,热性能优越。这种创新型封装结合了 OptiMOS™ 5 技术的主要特征,使英飞凌的 100 V 产品成为同类产品中的佼佼者 >300 A 而且可以为高功率密度设计提供高额定电流。

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IPTC014N10NM5  
MOSFET  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
PG-HDSOP-16  
16  
9
16  
Features  
9
•ꢀN-channel  
•ꢀVeryꢀlowꢀon-resistanceꢀRDS(on)  
•ꢀSuperiorꢀthermalꢀresistance  
•ꢀ100%ꢀavalancheꢀtested  
•ꢀPb-freeꢀleadꢀplating;ꢀRoHSꢀcompliant  
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21  
1
8
8
1
Productꢀvalidation  
FullyꢀqualifiedꢀaccordingꢀtoꢀJEDECꢀforꢀIndustrialꢀApplications  
Drain  
Pin 9-16, Tab  
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters  
Parameter  
Value  
100  
1.4  
Unit  
Gate  
Pin 8  
VDS  
V
Source  
Pin 1-7  
RDS(on),max  
ID  
m  
A
365  
213  
168  
Qoss  
nC  
nC  
QG  
Typeꢀ/ꢀOrderingꢀCode  
Package  
Marking  
RelatedꢀLinks  
IPTC014N10NM5  
PG-HDSOP-16  
14N10NM5  
-
Final Data Sheet  
1
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
TableꢀofꢀContents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Final Data Sheet  
2
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
1ꢀꢀꢀꢀꢀMaximumꢀratings  
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
-
-
-
-
-
-
-
-
365  
258  
216  
37  
VGS=10ꢀV,ꢀTC=25ꢀ°C  
VGS=10ꢀV,ꢀTC=100ꢀ°C  
Continuous drain current1)  
ID  
A
VGS=6ꢀV,ꢀTC=100ꢀ°C  
VGS=10V,TA=25°C,RthJA=40°C/W2)  
Pulsed drain current3)  
Avalanche energy, single pulse4)  
ID,pulse  
EAS  
-
-
-
-
1460  
775  
20  
A
TA=25ꢀ°C  
-
mJ  
V
ID=150ꢀA,ꢀRGS=25ꢀΩ  
Gate source voltage  
VGS  
-20  
-
-
-
-
-
375  
3.8  
TC=25ꢀ°C  
Power dissipation  
Ptot  
W
TA=25ꢀ°C,ꢀRthJA=40ꢀ°C/W2)  
IEC climatic category; DIN IEC 68-1:  
55/175/56  
Operating and storage temperature  
Tj,ꢀTstg  
-55  
-
175  
°C  
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Values  
Typ.  
0.2  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Thermal resistance, junction - case  
RthJC  
RthJA  
-
0.4  
°C/W -  
°C/W -  
Thermal resistance, junction - ambient,  
6 cm² cooling area2)  
-
-
-
-
40  
62  
Thermal resistance, junction - ambient,  
minimal footprint  
RthJA  
°C/W -  
1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature  
as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual  
environmental conditions.  
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
3) See Diagram 3 for more detailed information  
4) See Diagram 13 for more detailed information  
Final Data Sheet  
3
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics  
atꢀTj=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics  
Values  
Typ.  
-
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
100  
2.2  
Max.  
-
Drain-source breakdown voltage  
Gate threshold voltage  
V(BR)DSS  
VGS(th)  
V
V
VGS=0ꢀV,ꢀID=1ꢀmA  
3.0  
3.8  
VDS=VGS,ꢀID=280ꢀµA  
-
-
0.1  
10  
5.0  
100  
VDS=100ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C  
VDS=100ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C  
Zero gate voltage drain current  
Gate-source leakage current  
Drain-source on-state resistance  
IDSS  
µA  
nA  
IGSS  
-
10  
100  
VGS=20ꢀV,ꢀVDS=0ꢀV  
-
-
1.3  
1.6  
1.4  
2.0  
VGS=10ꢀV,ꢀID=150ꢀA  
VGS=6ꢀV,ꢀID=75ꢀA  
RDS(on)  
mΩ  
Gate resistance1)  
Transconductance  
RG  
gfs  
-
1.4  
2.1  
-
-
140  
280  
S
|VDS|2|ID|RDS(on)max,ꢀID=100ꢀA  
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Input capacitance1)  
Output capacitance1)  
Reverse transfer capacitance1)  
Ciss  
Coss  
Crss  
-
-
-
12000 16000 pF  
1800 2300 pF  
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=50ꢀV,ꢀf=1ꢀMHz  
80  
36  
140  
-
pF  
ns  
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
Turn-on delay time  
Rise time  
td(on)  
tr  
td(off)  
tf  
-
-
-
-
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
30  
85  
30  
-
-
-
ns  
ns  
ns  
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
Turn-off delay time  
Fall time  
VDD=50ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ  
Values  
Typ.  
53  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge1)  
Switching charge  
Gate charge total1)  
Gate plateau voltage  
Output charge1)  
Qgs  
-
-
-
-
-
-
-
-
nC  
nC  
nC  
nC  
nC  
V
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=50ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDS=50ꢀV,ꢀVGS=0ꢀV  
Qg(th)  
Qgd  
36  
-
34  
51  
-
Qsw  
51  
Qg  
168  
4.4  
211  
-
Vplateau  
Qoss  
213  
285  
nC  
1) Defined by design. Not subject to production test.  
2) See Gate charge waveformsfor parameter definition  
Final Data Sheet  
4
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode  
Values  
Typ.  
-
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
320  
1460  
1.0  
Diode continuous forward current  
Diode pulse current  
IS  
-
-
-
-
-
A
TC=25ꢀ°C  
IS,pulse  
VSD  
trr  
-
A
TC=25ꢀ°C  
Diode forward voltage  
0.88  
103  
316  
V
VGS=0ꢀV,ꢀIF=150ꢀA,ꢀTj=25ꢀ°C  
VR=50ꢀV,ꢀIF=100ꢀA,ꢀdiF/dt=100ꢀA/µs  
VR=50ꢀV,ꢀIF=100ꢀA,ꢀdiF/dt=100ꢀA/µs  
Reverse recovery time1)  
Reverse recovery charge1)  
206  
632  
ns  
nC  
Qrr  
1) Defined by design. Not subject to production test.  
Final Data Sheet  
5
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams  
Diagramꢀ1:ꢀPowerꢀdissipation  
Diagramꢀ2:ꢀDrainꢀcurrent  
400  
400  
350  
300  
250  
200  
150  
100  
50  
350  
300  
250  
200  
150  
100  
50  
0
0
0
25  
50  
75  
100  
125  
150  
175  
200  
0
25  
50  
75  
100  
125  
150  
175  
200  
TCꢀ[°C]  
TCꢀ[°C]  
Ptot=f(TC)  
ID=f(TC);ꢀVGS10ꢀV  
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea  
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance  
104  
101  
single pulse  
0.01  
0.02  
0.05  
0.1  
0.2  
1 µs  
103  
102  
101  
100  
10-1  
10-2  
10 µs  
100  
0.5  
100 µs  
1 ms  
10-1  
10-2  
10-3  
10 ms  
DC  
10-1  
100  
101  
102  
103  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
VDSꢀ[V]  
tpꢀ[s]  
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp  
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T  
Final Data Sheet  
6
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics  
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
1500  
4.0  
7 V  
8 V  
3.5  
10 V  
1250  
4.5 V  
3.0  
1000  
2.5  
5 V  
6 V  
6 V  
750  
500  
250  
0
2.0  
1.5  
1.0  
0.5  
0.0  
7 V  
8 V  
10 V  
5 V  
4.5 V  
0
1
2
3
4
5
0
100  
200  
300  
400  
500  
600  
700  
800  
VDSꢀ[V]  
IDꢀ[A]  
ID=f(VDS),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
RDS(on)=f(ID),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics  
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
1500  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
1250  
1000  
750  
175 °C  
500  
25 °C  
250  
175 °C  
0.5  
0.0  
25 °C  
0
0
1
2
3
4
5
6
7
0
3
6
9
12  
15  
VGSꢀ[V]  
VGSꢀ[V]  
ID=f(VGS),ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj  
RDS(on)=f(VGS),ꢀID=150ꢀA;ꢀparameter:ꢀTj  
Final Data Sheet  
7
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance  
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage  
2.4  
4.0  
3.5  
3.0  
2.5  
2.0  
1.6  
1.2  
0.8  
0.4  
0.0  
2800 µA  
280 µA  
2.0  
1.5  
1.0  
0.5  
0.0  
-75 -50 -25  
0
25 50 75 100 125 150 175 200  
-75 -50 -25  
0
25 50 75 100 125 150 175 200  
Tjꢀ[°C]  
Tjꢀ[°C]  
RDS(on)=f(Tj),ꢀID=150ꢀA,ꢀVGS=10ꢀV  
VGS(th=f(Tj),ꢀVGS=VDS;ꢀparameter:ꢀID  
Diagramꢀ11:ꢀTyp.ꢀcapacitances  
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode  
105  
104  
25 °C  
25 °C, max  
175 °C  
175 °C, max  
104  
103  
102  
101  
Ciss  
103  
102  
101  
Coss  
Crss  
0
20  
40  
60  
80  
100  
0.00  
0.25  
0.50  
0.75  
1.00  
1.25  
1.50  
1.75  
VDSꢀ[V]  
VSDꢀ[V]  
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz  
IF=f(VSD);ꢀparameter:ꢀTj  
Final Data Sheet  
8
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
Diagramꢀ13:ꢀAvalancheꢀcharacteristics  
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge  
103  
10  
20 V  
50 V  
80 V  
8
6
4
2
0
102  
25 °C  
100 °C  
150 °C  
101  
100  
100  
101  
102  
103  
0
25  
50  
75  
100  
125  
150  
175  
tAVꢀ[µs]  
Qgateꢀ[nC]  
IAS=f(tAV);ꢀRGS=25ꢀ;ꢀparameter:ꢀTj,start  
VGS=f(Qgate),ꢀID=100ꢀAꢀpulsed,ꢀTj=25ꢀ°C;ꢀparameter:ꢀVDD  
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage  
Diagram Gate charge waveforms  
108  
106  
104  
102  
100  
98  
96  
94  
-75 -50 -25  
0
25 50 75 100 125 150 175 200  
Tjꢀ[°C]  
VBR(DSS)=f(Tj);ꢀID=1ꢀmA  
Final Data Sheet  
9
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
5ꢀꢀꢀꢀꢀPackageꢀOutlines  
PACKAGE - GROUP  
NUMBER:  
PG-HDSOP-16-U01  
DATE: 18.12.2020  
REVISION: 01  
MILLIMETERS  
DIMENSIONS  
MIN.  
MAX.  
2.35  
A
A1  
b
2.25  
0.01  
0.60  
0.40  
9.70  
8.20  
14.80  
10.00  
5.57  
0.16  
0.80  
c
0.60  
D
10.10  
8.40  
D1  
E
15.20  
10.30  
5.77  
E1  
E2  
e
1.20  
8.40  
e1  
L
1.40  
2.90  
1.60  
3.10  
P
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-HDSOP-16,ꢀdimensionsꢀinꢀmm  
Final Data Sheet  
10  
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
1.2  
14×  
0.8  
16×  
0.8  
16×  
0.6  
Solder mask  
clearance  
1.2  
14×  
0.6  
Pin1  
10.2  
copper  
solder mask  
stencil apertures  
Based on stencil thickness 0.20 mm  
All dimensions are in units mm  
Figureꢀ2ꢀꢀꢀꢀꢀOutlineꢀFootprintꢀ(PG-HDSOP-16),ꢀdimensionsꢀinꢀmm  
Final Data Sheet  
11  
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
12  
4
0.3  
2.85  
10.3  
All dimensions are in units mm  
The drawing is in compliance with ISO 128-30, Projection Method 1 [  
]
Figureꢀ3ꢀꢀꢀꢀꢀOutlineꢀTapeꢀ(PG-HDSOP-16),ꢀdimensionsꢀinꢀmm  
Final Data Sheet  
12  
Rev.ꢀ2.0,ꢀꢀ2022-05-24  
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ100ꢀV  
IPTC014N10NM5  
RevisionꢀHistory  
IPTC014N10NM5  
Revision:ꢀ2022-05-24,ꢀRev.ꢀ2.0  
Previous Revision  
Revision Date  
Subjects (major changes since last revision)  
Release of final version  
2.0  
2022-05-24  
Trademarks  
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Final Data Sheet  
13  
Rev.ꢀ2.0,ꢀꢀ2022-05-24  

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