IR1150S [INFINEON]
UPFC ONE CYCLE CONTROL PFC IC; 统一潮流控制器的单周期控制PFC IC
| 型号： | IR1150S |
| 厂家： | 
Infineon |
| 描述： | UPFC ONE CYCLE CONTROL PFC IC |
| 文件： | 总16页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data ShIeRet N1o1. P5D060S23(0PrbevFAa)
IR1150IS(PbF)
µPFC ONE CYCLE CONTROL PFC IC
Features
• Open loop protection
•
PFC with IR proprietary “One Cycle Control”
• Maximum duty cycle limit of 98%
• Continuous conduction mode (CCM) boost type PFC
• No line voltage sense required
•
•
User programmable fixed frequency operation
Min. off time of 150-350ns over freq range
•
Programmable switching frequency (50kHz-200kHz)
CC
• V under voltage lockout
• Internally clamped 13V gate drive
• Fast 1.5A peak gate drive
• Programmable output overvoltage protection
•
•
•
Brownout and output undervoltage protection
Cycle-by-cycle peak current limit
Soft start
•
Micropower startup (<200 µA)
• Latch immunity and ESD protection
• Parts also available Lead-Free
• User initiated micropower “Sleep Mode”
Description
Package
The µPFC IR1150 is a power factor correction (PFC) control IC designed to operate in continuous
conduction mode (CCM) over a wide range input line voltages. The IR1150 is based on IR's
proprietary "One Cycle Control" (OCC) technique providing a cost effective solution for PFC.
The proprietary control method allows major reductions in component count, PCB area and
design time while delivering the same high system performance as traditional solutions.
The IC is fully protected and eliminates the often noise sensitive line voltage sensing requirements
of existing solutions.
The IR1150 features include programmable switching frequency, programmable dedicated
over voltage protection, soft start, cycle-by-cycle peak current limit, brownout, open loop,
UVLO and micropower startup current.
8-Lead SOIC
In addition, for low standby power requirements (Energy Star, 1W Standby, Blue Angel, etc.), the IC can be driven into sleep
mode with total current consumption below 200µA, by pulling the OVP pin below 0.62V.
IR1150 Application Diagram
V OUT
BRIDGE
AC LINE
+
V cc
AC NEUTRAL
IR1150
1
2
3
4
8
7
6
5
COM
FREQ
ISNS
OVP
GATE
VCC
VFB
COMP
+
RTN
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1
IR1150S/IR1150IS(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are
absolute voltages referenced to COM. Thermal resistance and power dissipation are measured under board mounted and
still air conditions.
Parameters
CC
Freq. voltage
Symbols
Min. Max. Units Remarks
V
voltage
V
-0.3
-0.3
-10
-0.3
-0.3
-0.3
-5
-1.5
-40
-55
—
22
10.5
3
10.5
10
18
5
1.5
150
150
128
V
Not internally clamped
CC
V
V
V
V
V
V
mA
A
oC
oC
FREQ.
I
V
voltage
voltage
V
ISNS
SNS
V
FB
FB
COMP voltage
Gate voltage
V
COMP
V
GATE
Continuous gate current
Max peak gate current
Junction temperature
Storage temperature
Thermal resistance
Package power dissipation
I
GATE
I
GATEPK
T
J
T
S
R
θJA
° C/W SOIC-8
P
—
—
675
2
mW
kV
SOIC-8 T
Human body model*
= 25oC
AMB
D
V
ESD
ESD protection
Recommended Operating Conditions
Recommended operating conditions for reliable operation with margin
Parameters
Symbols
Min. Typ. Max. Units Remarks
Supply voltage
V
15
-25
0
18
—
—
—
—
20
125
70
V
CC
Junction temperature
Ambient temperature
Ambient temperature
Switching frequency
T
°C
°C
°C
kHz
J
A
A
T
T
IR1150S
IR1150IS
-25
50
85
200
F
SW
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction
temperature range TJ from – 25 ° C to 125°C. Typical values represent the median values, which are related to 25°C. If not
otherwise stated, a supply voltage of V
=15V is assumed for test condition
CC
Supply Section
Parameters
Symbols
CC ON
Min. Typ. Max. Units Remarks
V
V
turn-on threshold
turn-off threshold
V
V
12.2
10.2
12.7
10.7
13.2
11.2
V
V
CC
CC
CC UVLO
(under voltage lock out)
turn-off hysteresis
V
V
1.8
—
2.2
V
CC
CC HYST
*Per EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5KΩ series resistor)
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2
IR1150S/IR1150IS(PbF)
Electrical Characteristics cont.
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction
temperature range TJ from – 25° C to 125°C. Typical values represent the median values, which are related to 25°C. If not
otherwise stated, a supply voltage of V
=15V is assumed for test condition.
CC
Parameters
Operating current
Symbols
CC
Min. Typ. Max. Units Remarks
I
—
—
—
18
36
8
22
40
10
mA
mA
mA
C
C
=1nF f =200kHZ
SW
LOAD
=10nF f =200kHZ
LOAD
SW
Standby mode - inactive gate
Internal oscillator running
Startup current
Sleep current
Sleep mode threshold
I
—
—
0.565
—
125
0.615
175
200
0.665
uA
uA
V
V
V
V
=V
-0.1V
CCSTART
CC
CC ON
I
<0.5V (typ),V
OVP
=15V
CC
SLEEP
V
=15V
SLEEP
CC
Oscillator Section
Parameters
Switching frequency
Symbols
Min. Typ. Max. Units Remarks
f
50
—
200
kHz
R
= 165kΩ -37kΩ approx.
SET
SW
Initial accuracy
Voltage stability
f
—
—
—
—
—
93
—
200
—
0.2
2
10
0.1
—
5
3
%
%
%
%
%
%
%
ns
T = 25oC
A
SW ACC
V
STAB
13V <V
<20V
CC
Temperature stability
Total variation
Long term stability
Maximum duty cycle
Minimum duty cycle
Minimum off time
T
STAB
—
—
0.5
98
0
-25oC ≤T ≤125oC
J
f
Line & temperature
VT
F
T
= 125oC, 1000Hrs
STABLT
AMB
D
fSW=200kHz
MAX
D
MIN
—
300
T
400
fSW=50kHz to 200kHz
offmin
Protection Section
Parameters
Symbols
Min. Typ. Max. Units Remarks
Open loop protection (OLP)
Vfb threshold
V
OLP
17
49
19
51
21
53
%V
REF
Output under voltage
protection (OUV)
Output over voltage
protection (OVP)
V
V
%V
%V
Brown out protection
OUV
REF
104
350
105.5
450
107
550
OVP
REF
OVP hysteresis
—
mV
Peak current limit protection
PKLMT SNS
(I
) I
voltage threshold
V
ISNS
-1.11
-1.04
-0.96
V
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3
IR1150S/IR1150IS(PbF)
Internal Voltage Reference Section
Parameters
Reference voltage
Line regulation
Temp stability
Symbols Min. Typ. Max. Units Remarks
V
6.9
—
7.0
12
7.1
25
V
T = 25oC
REF
A
R
T
∆V
mV
%
V
13.5V <V
< 20V
CC
REG
—
6.8
0.4
—
—
7.1
-25oC ≤T
≤125oC
STAB
AMB
Total variation
Over V
and T ranges
CC j
TOT
Voltage Error Amplifier Section
Parameters
Symbols Min. Typ. Max. Units Remarks
Transconductance
g
30
40
55
µS
µA
µA
-25oC ≤T
≤125oC
m
AMB
Source/sink current
30
20
±40
45
65
90
TAMB = 25oC
IOVEA
-25oC ≤TAMB≤125oC
Soft start delay time
(calculated)
t
—
40
—
ms
R
=1kΩ, C
=0.01µF, f =28Hz
XO
=0.33µF
ss
GAIN
ZERO
C
POLE
V
COMP
voltage (fault)
VCOMP FLT
—
1.2
1.5
0.2
V
V
@ 1mA (max) initial
@ 25µA steady state
Effective V
Input bias current
Open loop bandwidth
voltage
VCOMP EFF
6.05
-0.2
1
V
µA
MHz
COMP
I
IB
—
—
-0.5
—
VFB=0V, -25oC ≤T
≤125oC
AMB
BW
Input offset voltage temp
coefficient
Common mode rejection ratio
TC
IOV
CMRR
—
—
—
100
10
—
µV/oC
dB
Output low voltage
Output high voltage
V
V
—
5.71
300
—
6.15
500
0.5
6.8
700
V
V
mV
OL
OH
V
COMP
start voltage
V
COMP START
Current Amplifier Section
Parameters
DC gain
Corner frequency
Input offset voltage
Symbols Min. Typ.
Max. Units Remarks
g
—
2.5
—
—
V/V
kHz
mV
µA
DC
f
200
—
280
4
300
C
V
1
IO
I
bias current
Ι
IB
—
200
VFB=0V,-25oC ≤T
≤125oC
SNS
AMB
Input offset voltage temp
coefficient
TC
—
—
10
—
µV/oC
dB
IOV
Common mode rejection ratio
Blanking time
CMRR
BLANK
—
230
100
350
TAMB = 25oC
T
450
ns
-25oC ≤T ≤125oC
AMB
150
600
ns
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4
IR1150S/IR1150IS(PbF)
Gate Driver Section
Parameters
Gate low voltage
Gate high voltage
Gate high voltage
Rise time
Symbols Min. Typ.
Max. Units Remarks
V
—
—
9.5
—
—
—
—
1.5
—
1.2
13
—
20
70
20
70
—
1.5
18
—
—
—
—
—
—
V
I
=200mA
=20V
GLO
GATE
V
V
V
V
V
V
C
C
C
C
C
GTH
CC
=11.5V
GTH
CC
ns
ns
ns
ns
A
= 1nF, V =16V
CC
= 10nF, V =16V
CC
= 1nF, V =16V
CC
= 10nF, V =16V
CC
LOAD
LOAD
LOAD
LOAD
LOAD
t
r
Fall time
t
f
Out peak current
Gate voltage @ fault
I
V
= 10nF, V =16V
CC
OPK
—
1.8
V
I =20mA
GATE
G fault
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5
IR1150S/IR1150IS(PbF)
Block Diagram
BIAS &
7
2
VCC
UVLO
REFERENCES
SLEEP
0.5V
4
OVP/EN
1.055VREF
CLOCK
FREQ
1.0V
3
ISNS
MAX
DUTY CYCLE
-
LIMIT
+
Vm
S
Q
VREF
8
1
GATE
COM
FAULT
R
Q
VFB
6
5
COMP
RESET
FAULT
FAULT PROTECTION
FAULT
OPEN LOOP PROTECTION
OUTPUT UNDER VOLTAGE
Lead Assignments & Definitions
Lead Assignment
Pin#
1
Symbol
COM
Description
Ground
IR1150S
Frequency Set
2
FREQ
ISNS
GATE
1
8
COM
Current Sense
3
4
V
2
3
7
6
FREQ
CC
OVP/EN
Overvoltage Fault Detect / Enable
Voltage Loop Compensation
Output Voltage Sense
IC Supply Voltage
V
I
SNS
FB
5
6
7
8
COMP
VFB
5
COMP
OVP/EN
4
VCC
8 LEAD SOIC
GATE
Gate Drive Output
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6
IR1150S/IR1150IS(PbF)
General Description
The µPFC IR1150 is intended for boost converters
for power factor correction operating at a fixed
frequency in continuous conduction mode. The IC
operates with two loops; an inner current loop and
an outer voltage loop. The inner current loop is fast,
reliable and does not require sensing of the input
voltage in order to create a current reference.
IC Supply
The UVLO circuit monitors the VCC pin and maintains
the gate drive signal inactive until the VCC pin voltage
reaches the UVLO turn on threshold, (VCC ON). As soon
as the VCC voltage exceeds this threshold, provided
that the V pin voltage is greater than 20%VREF, the
gate driveFwB ill begin switching (under Soft Start) and
increase the pulse width to its maximum value as
demanded by the output voltage error amplifier. If
the voltage on the VCC pin falls below the UVLO turn
This inner current loop sustains the sinusoidal profile
of the average input current based on the dependency
of the pulse width modulator duty cycle on the input
line voltage in order to determine the analogous input
line current. Thus, the current loop uses the
embedded input voltage signal to control the average
input current to follow the input voltage.
off threshold, (V
), the IC turns off, gate drive is
terminated, andCtChUeVLtOurn on threshold must again be
exceeded in order to re-start the process and move
into Soft Start mode.
Soft Start
The IR1150 enables excellent THD performance. In
light load conditions, a small distortion occurs at zero-
crossing due to the finite boost inductance but this is
negligible and well within EN61000-3-2 Class D
specifications.
Soft Start controls the rate of rise of the output voltage
error amplifier in order to obtain a linear control of
the increasing duty cycle as a function of time. The
Soft Start time is controlled by voltage error amplifier
compensation components selected, and is user
programmable based on desired loop crossover
frequency.
The outer voltage loop controls the DC bus voltage.
This voltage is fed into the voltage error amplifier to
control the slope of the integrator ramp and sets the
amplitude of the average input current.
Frequency Select
The switching frequency of the IC is programmable
by an external resistor at the FREQ pin. The design
incorporates min/max restrictions such that the
minimum and maximum operating frequency fall
within the range of 50-200kHz.
The two loops combine to control the amplitude,
phase and shape of the input current, with respect to
the input voltage, giving near-unity power factor.
The IC is designed for robust operation and pro-
vides protection from system level over current, over
voltage, under voltage, and brownout conditions.
Gate Drive
The gate drive is a totem pole driver with 1.5A
capability. If higher currents are required, additional
external drivers can be used.
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7
IR1150S/IR1150IS(PbF)
Detailed Pin Description
I
: Current Sense input
COM: Ground
SNS
This pin is the inverting Current Sense Input & Peak
Current Limit. The voltage at this pin is the negative
voltage drop, sensed across the system current
sense resistor, representing the inductor current.
This voltage is fed into the Peak Current Limit pro-
tection comparator with threshold arond -1V. This pro-
tection circuit incorporates a leading edge blanking
circuit following the comparator to improve noise
immunity of the protection process.
This is the ground potential pin of the integrated con-
trol circuit. All internal devices are referenced to this
point.
V
: Output Voltage Feedback
FB
The output voltage of the boost converter is sensed
via a resistive divider and fed into this pin, which is
the inverting input of the output voltage error amplifier.
The impedance of the divider string must be low
enough so as to not introduce substantial error due
to the input bias currents of the amplifier, yet high
enough so as to minimize power dissipation. A typical
value of external divider impedance is 1MΩ.
The current sense signal is also fed into the current
sense amplifier. The signal is amplified, filtered of
high frequency noise and then injected into a sum-
ming node where it is subtracted from the compen-
sation voltage VCOMP
.
The error amplifier is a transconductance type which
yields high output impedance, thus increasing the
noise immunity of the error amplifier output. This also
eliminates input divider string interaction with
compensation feedback capacitors and reducing the
loading of divider string due to a low impedance
output of the amplifier.
The signal on this pin must be previously filtered
with an RC cell to provide additional noise immunity.
The input impedance of this pin is 5kΩ.
V
: Supply Voltage
CC
This is the supply voltage pin of the IC and it is
monitored by the under voltage lockout circuit. It is
possible to turn off the IC by pulling this pin below
the minimum turn off threshold voltage, without
damage to the IC.
COMP: Voltage Loop Compensation
External circuitry from this pin to ground
compensates the system voltage loop and soft start
time. This is the output of the voltage error amplifier.
This pin will be discharged via internal resistance
when a fault mode occurs.
To prevent noise problems, a bypass ceramic
capacitor connected to VCC and COM should be
placed as close as possible to the IR1150S.
This pin is not internally clamped, therefore damage
will occur if the maximum voltage is exceeded.
GATE: Gate Drive Output
This is the gate drive output of the IC. Drive voltage is
internally limited and provides ±1.5A peak with
matched rise and fall times.
OVP/EN: Over Voltage Protection / Enable
This pin is the input to the over voltage protection
comparator the threshold of which is internally pro-
grammed to 105.5% of VREF
.
FREQ: Frequency Set
A resistive divider feeds this pin from the output volt-
age to COM and inhibits the gate drive whenever the
threshold is exceeded. Normal operation resumes
when the voltage level on this pin decreases to be-
low the pin threshold.
This is the user programmable frequency pin. An
external resistor from this pin to the COM pin pro-
grams the frequency. The operational switching fre-
quency range for the device is 50kHz – 200kHz.
This pin is also used to activate “sleep” mode by
pulling the voltage level below 0.62V (typ).
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8
IR1150S/IR1150IS(PbF)
Operating States
UVLO Mode
Normal Mode
The IC remains in the UVLO condition until the voltage
on the VCC pin exceeds the VCC turn on threshold
voltage, VCC ON.
The IC enters normal operating mode once the soft
start transition has been completed. At this point the
gate drive is switching and the IC draws a maximum
of ICC from the supply voltage source. The device
will initiate another soft start sequence in the event
of a shutdown due to a fault, which activates the
protection circuitry, or if the supply voltage drops below
the UVLO turn off threshold of VCC UVLO.
During the time the IC remains in the UVLO state,
the gate drive circuit is inactive and the IC draws a
quiescent current of ICC START. The UVLO mode is
accessible from any other state of operation whenever
the IC supply voltage condition of VCC < VCC UVLO
occurs.
Fault Protection Mode
Standby Mode
The fault mode will be activated when any of the
protection circuits are activated. The IC protection
circuits include Supply Voltage Under Voltage Lockout
(UVLO), Output Over Voltage Protection (OVP), Open
Loop Protection (OLP), Output Undervoltage
Protection (OUV), and Peak Current Limit Protection
(IPK LIMIT).
The IC is in this state if the supply voltage has
exceeded VCC ON and the VFB pin voltage is less
than 20% of VREF . The oscillator is running and all
internal circuitry is biased in this state but the gate is
inactive. This state is accessible from any other state
of operation except OVP. The IC enters this state
whenever the VFB pin voltage has decreased to 50%
of VREF when operating in normal mode or during a
peak current limit fault condition, or 20% VREF when
operating in soft start mode.
Sleep Mode
The sleep mode is initiated by pulling the OVP pin
below 0.62V (typ). In this mode the IC draws a very
low quiescent supply current.
Soft Start Mode
This state is activated once the VCC voltage has
exceeded VCCON and the VFB pin voltage has
exceeded 20% of VREF
.
The soft start time, which is defined as the time
required for the duty cycle to linearly increase from
zero to maximum, is dependent upon the values
selected for compensation of the voltage loop pin
COMP to pin COM. Throughout the soft start cycle,
the output of the voltage error amplifier (pin COMP)
charges through the compensation network. This
forces a linear rise of the voltage at this node which
in turn forces a linear increase in the gate drive duty
cycle from 0. This controlled duty cycle reduces
system component stress during start up conditions
as the input current amplitude is increasing linearly.
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9
IR1150S/IR1150IS(PbF)
AC POWER ON
Gate Inactive
Oscillator Inactive
STATE & TRANSITIONS
DIAGRAM
UVLO
< VCCon
VCC
Gate Inactive
Oscillator Inactive
ICC MAX = 200uA
Sleep
VOVP <0.7V
Gate Inactive
> VCCon
VCC
Oscillator Inactive
ICC max = 200uA
VCC < VCC UVLO
STAND BY
-
Gate Inactive
Oscillator Active
ICC MAX =4mA
VOVP >0.7V
VFB <20 VREF
%
V
OVP <0.7V
VFB >20%V
REF
VFB < 50%V
VFB <20%V
REF
VCC < VCC UVLO
REF
VCC < VCC UVLO
VISNS
SOFT START
IPK LIMIT
FAULT
VFB <80%V
REF
V
OVP <0.7V
-1
<
.0V
Gate Active
Oscillator Active
V
-1
<
.0V
ISNS
Pulse Width Increasing
Present PulseTerminated
V
ISNS > -1.0V
0- 97% Duty Cycle
Oscillator Active
VFB >80%V
REF
VCC < VCC UVLO
VFB <50%V
REF
NORMAL
Gate Active
V
< -1
.0V
ISNS
Oscillator Active
V
OVP <0.7V
V
ICC MAX =28
mA
ISNS > -1.0V
V
OVP <0.7V
VOVP 101%V
<
REF
OVP1F05A%UV LT
Gate Inactive
Oscillator Active
VOVP
>
REF
105%V
VOVP
>
VCC < VCC UVLO
REF
V
OVP <0.7V
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10
IR1150S/IR1150IS(PbF)
13 V
12 V
11 V
100
10
1
V
10 V
CC ON
0.1
0.01
VCC UVLO
9 V
-50 °C
0 °C
50 °C
Temperature
100 °C
150 °C
5 V
10 V
15 V
20 V
25 V
Supply voltage
Fig. 2 - Under Voltage Lockout vs.
Temperature
Fig.1 - Supply Current
300 kHz
250 kHz
200 kHz
150 kHz
100 kHz
50 kHz
250 kHz
200 kHz
150 kHz
100 kHz
50 kHz
0 kHz
R
=37k
F
R
=78k
F
R
=165k
F
0 kHz
0 k
50 k
100 k
150 k
200 k
-50 °C
0 °C
50 °C
Temperature
100 °C
150 °C
Programming Resistor
Fig. 3 - Oscillator Frequency vs.
Programming Resistor
Fig. 4 - Oscillator Frequency vs.
Temperature
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11
IR1150S/IR1150IS(PbF)
7.10 V
7.05 V
7.00 V
6.95 V
6.90 V
6.85 V
50 uS
45 uS
40 uS
35 uS
30 uS
-50 °C
0 °C
50 °C
Temperature
100 °C
150 °C
-50 °C
0 °C
50 °C
Temperature
100 °C
150 °C
Fig. 5 - Reference Voltage
Fig. 6 - Voltage Error Amplifier
Transconductance
60 uA
50 uA
40 uA
30 uA
20 uA
10 uA
2.70
2.60
2.50
2.40
2.30
IO (source)
IO (sink)
-50 °C
0 °C
50 °C
Temperature
100 °C
150 °C
-50 °C
0 °C
50 °C
Temperature
100 °C
150 °C
Fig.7 - Voltage Error Amplifier
Source/Sink Current
Fig. 8 - Current Sense Amplifier DC Gain
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12
IR1150S/IR1150IS(PbF)
IR1150 Timing Diagrams
Vcc
13.0V (typ)
11.0V (typ)
t
NORMAL
UVLO
UVLO
V
Under Voltage Lockout
cc
106% VREF
100% VREF
82% VREF
51% VREF
19% VREF
t
OLP
SOFT START
OLP
NORMAL
OUV
OVP
Output Protection
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13
IR1150S/IR1150IS(PbF)
Case outline
IN C HES
MIN MAX
.0532 .0688
MILLIMETERS
DIM
A
D
B
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
FOOTPRINT
8X 0.72 [.028]
5
A
A1 .0040 .0098
b
c
D
E
e
.013
.0075 .0098
.189 .1968
.020
8
1
7
2
6
3
5
6
H
E
.1497 .1574
.050 BASIC
0.25 [.010]
A
1.27 BASIC
0.635 BASIC
6.46 [.255]
4
e 1 .025 BASIC
H
K
L
.2284 .2440
.0099 .0196
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.016
0°
.050
8°
3X 1.27 [.050]
e
6X
8X 1.78 [.070]
y
K x 45°
e1
A
A
C
y
0.10 [.004]
8X c
8X L
A1
B
8X b
7
0.25 [.010]
C
NOTES:
5
6
7
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
D IM EN SIO N IS TH E LE NG TH OF L EAD FO R SO LDE RING TO
A SUBSTRATE.
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. C O NTRO LL ING DIM EN SIO N: M ILL IM ETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
www.irf.com
14
IR1150S/IR1150IS(PbF)
Tape & Reel Information
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
2. CONTROLLING DIMENSION : MILLIMETER.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
www.irf.com
15
IR1150S/IR1150IS(PbF)
PART MARKING INFORMATION
?
?
P
MARKING CODE
LOT CODE
Lead Free Released
Non-Lead Free
(
)
Released
ORDER INFORMATION
Basic Part
Lead-free Part
8-Lead SOIC IR1150STR order IR1150STR
8-Lead SOIC IR1150ISTR order IR1150ISTR
8-Lead SOIC IR1150S order IR1150STRPbF
8-Lead SOIC IR1150ISTR order IR1150ISTRPbF
The IR1150S(PbF) has been designed and qualified for the Consumer Market
The IR1150IS(PbF) has been designed and qualified for the Industrial Market
Qualification Standards can be found on IR’s Web site.
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
http://www.irf.com/ Data and specifications subject to change without notice.
6/13/2005
www.irf.com
16
相关型号：
IR1152STRPBF
FIXED 66kHz FREQUENCY, μPFC ONE CYCLE CONTROL PFC IC WITH BROWN-OUT PROTECTION
INFINEON
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