IR1152STRPBF [INFINEON]
FIXED 66kHz FREQUENCY, μPFC ONE CYCLE CONTROL PFC IC WITH BROWN-OUT PROTECTION; FIXED 66kHz频率， μPFC单周期控制PFC与欠压保护IC
| 型号： | IR1152STRPBF |
| 厂家： | 
Infineon |
| 描述： | FIXED 66kHz FREQUENCY, μPFC ONE CYCLE CONTROL PFC IC WITH BROWN-OUT PROTECTION |
| 文件： | 总20页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Feb 21, 2011
IR1152S
FIXED 66kHz FREQUENCY, µPFC ONE CYCLE CONTROL PFC
IC WITH BROWN-OUT PROTECTION
Features
• VCC under voltage lockout
• Programmable soft start
• Micropower startup
• User initiated micropower “Sleep Mode”
• 750mA peak gate drive
• PFC IC with IR proprietary “One Cycle Control”
• Continuous conduction mode boost type PFC
• Fixed 66kHz switching frequency
• Average current mode control
• Input line sensed brownout protection
• Output overvoltage protection
• Latch immunity and ESD protection
• Open loop protection
• Cycle by cycle peak current limit
Description
Package
µPFC IR1152 power factor correction IC, based on IR proprietary "One
Cycle Control" (OCC) technique, provides for high PF and excellent DC
Bus regulation while enabling drastic reduction in component count,
PCB area and design time as compared to traditional solutions. The IC
is designed to operate in 85-264VAC universal input, continuous
conduction mode Boost PFC at fixed 66kHz switching frequency.
IR1152 features include input-line sensed brown-out protection,
overvoltage protection, cycle by cycle peak current limit, open loop
protection, VCC UVLO, soft-start and micropower startup current of less
than 75µA. In addition, for standby power requirements, the IC can be
driven into a micropower sleep mode by pulling the OVP/EN pin low
where the current consumption is less than 75uA. The IR1152 is
available in SO-8 packages.
IR1152 Application Diagram
ACIN1
-
+
VOUT
VCC
ACIN2
1
2
3
4
8
7
6
5
+
COM
COMP VCC
ISNS VFB
GATE
BOP OVP/EN
IR1152
RTN
www.irf.com
© 2011 International Rectifier
IR1152S
Qualification Information
Industrial
Comments: This family of ICs has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by extension
Qualification Level
of the higher Industrial level.
MSL2 260°C
(per IPC/JEDEC J-STD-020)
Class A
Moisture Sensitivity Level
Machine Model
ESD
(per JEDEC standard JESD22-A115)
Class 1A
Human Body Model
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I, Level A
IC Latch-Up Test
RoHS Compliant
(per JESD78)
Yes
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these conditions is not
implied. All voltages are absolute voltages referenced to COM. Thermal resistance and power dissipation
are measured under board mounted and still air conditions.
Parameters
VCC Voltage
ISNS voltage
ISNS Current
VFB voltage
VOVP voltage
VBOP voltage
COMP voltage
Symbol
VCC
VISNS
IISNS
Min.
-0.3
-10
Max.
20
0.3
2
6.5
6.5
9
6.5
18
Units
V
V
mA
V
V
V
V
V
Remarks
Not internally clamped
-2
VFB
-0.3
-0.3
-0.3
-0.3
-0.3
VOVP
VBOP
VCOMP
VGATE
Gate Voltage
Junction Temperature Operating
Range
Storage Temperature
Thermal Resistance
TJ
-40
-55
150
°C
TS
RθJA
PD
150
128
976
°C
°C/W
mW
Package Power Dissipation
TAMB=25°C
© 2011 International Rectifier
www.irf.com
2
IR1152S
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and
junction temperature range TJ from – 25° C to 125°C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition
Supply Section
Parameters
Supply Voltage Operating
Range
Symbol
VCC
Min.
Typ.
14
Max.
17
Units
V
Remarks
VCC Turn On Threshold
VCC Turn Off Threshold
(Under Voltage Lock Out)
VCC ON
VCC UVLO
12.2
9.4
13.1
10.1
14
V
10.8
V
VCC Turn On/Off Hysteresis VCC HYST
2.4
3
3.6
9
14
5
75
75
V
C
C
LOAD =1nF
LOAD =4.7nF
mA
mA
mA
µA
µA
Operating Current
ICC
3.5
26
26
Stand-by Mode – Inactive gate
VCC=VCC ON - 0.5V
Pin OVP/EN=0.4V
Start-up Current
Sleep current
ICC START
ISLEEP
Sleep Mode Threshold
VSLEEP
0.55
0.8
V
Bias on OVP/EN pin
Oscillator Section
Parameters
Symbol
Min.
58
Typ.
Max.
72.5
73
99
0
Units
Remarks
66
TAMB=25°C
Fixed Oscillator Frequency
fSW
kHz
%
%
53.8
93
-25°C < TAMB < 125°C
VCOMP=5V
Pulse Skipping
DMAX
DMIN
Maximum Duty Cycle
Minimum Duty Cycle
Protection Section
Parameters
Open Loop Protection
(OLP)Threshold
Output Overvoltage
Protection (OVP)
Threshold
Symbol Min.
Typ. Max. Units
Remarks
%
VREF
VOLP
17
19
21
Bias on VFB pin
%
VREF
VOVP
104
106
108
Bias on VFB and/or OVP/EN pins
Bias on VFB and/or OVP/EN pins
Output Overvoltage
Protection Reset Threshold
%
VREF
VOVP(RST) 101
IOVP(Bias)
103
105
OVP Input Bias Current
-0.2
0.88
1.66
µA
V
Brown-out Protection
(BOP) Threshold
Brown-out Protection
Enable Threshold
VBOP
VBOP(EN)
IBOP(Bias)
0.68
1.46
0.78
1.56
Bias on BOP pin
Bias on BOP pin
V
BOP Input Bias Current
-0.2
µA
V
Peak Current Limit
Protection ISNS Voltage
Threshold (IPK LIMIT)
VISNS(PK) -0.82 -0.75 -0.68
Bias on ISNS pin
© 2011 International Rectifier
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3
IR1152S
Internal Voltage Reference Section
Parameters
Symbol
Min.
Typ.
Max.
Units
Remarks
Regulation Voltage on VFB pin,
TAMB=25°C
14V < VCC < 17V
-25°C < TAMB < 125°C
Line & Temperature
Reference Voltage
Line Regulation
Temp Stability
VREF
RREG
TSTAB
ΔVTOT
4.9
5
10
0.4
5.1
20
V
mV
%
Total Variation
4.85
5.1
V
Voltage Error Amplifier Section
Parameters
Symbol
Min.
35
Typ.
49
Max.
59
Units
µS
Remarks
Transconductance
gm
30
17
-58
-80
44
58
80
-30
-17
TAMB=25°C
-25°C < TAMB < 125°C
TAMB=25°C
Source Current (Normal
Mode)
IOVEA(SRC)
µA
-44
60
IOVEA(SNK)
tSS
µA
msec
V
Sink Current (Normal Mode)
Soft Start Delay Time
(calculated)
-25°C < TAMB < 125°C
RGAIN=1.1kΩ, CZERO=0.56μF,
C
POLE=10nF
VCOMP Voltage (Fault)
VCOMP FLT
1
1.4
@100uA steady state
VCOMP EFF
IFB(Bias)
VOL
Effective VCOMP voltage
VFB Input Bias Current
Output Low Voltage
Output High Voltage
4.7
4.9
5.1
-0.2
0.25
5.4
V
µA
V
VFB=4.9V
VOH
5
V
VCOMP
START
VCOMP Start Voltage
260
375
485
mV
© 2011 International Rectifier
www.irf.com
4
IR1152S
Current Amplifier Section
Parameters
DC Gain
Corner Frequency
Input Offset Voltage
ISNS Input Bias Current
Blanking Time
Symbol Min.
Typ. Max. Units
Remarks
gDC
2.65
3.1
5
3.55
V/V
kHz Average Current Mode, Note 1
fC
VIO
4
16
-13
470
mV
µA
ns
Note 1
IISNS(Bias)
-57
VFB=0V, VISNS=-1V
170
320
TBLANK
Gate Driver Section
Parameters
Symbol Min.
Typ. Max. Units
Remarks
Gate Low Voltage
VGLO
0.8
14
V
IGATE = 200mA
VCC=17V, Internally Clamped
VCC=11.5V
12
10
13
Gate High Voltage
Rise Time
VGTH
V
25
60
35
65
ns
ns
ns
ns
mA
V
CLOAD = 1nF, VCC=15V
tr
C
LOAD = 4.7nF, VCC=15V
CLOAD = 1nF, VCC=15V
LOAD = 4.7nF, VCC=15V
Fall Time
tf
C
Output Peak Current
Gate Voltage at Fault
IOPK
VG fault
750
CLOAD = 4.7nF, VCC=15V, Note 1
IGATE = 20mA
0.08
Note 1: Guaranteed by design, but not tested in production
© 2011 International Rectifier
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5
IR1152S
Block Diagram
OVP/EN
ISNS
VBIAS
SLEEP
VSLEEP
(POWER OFF)
ENABLE
Comparator
OVP (OVP)
Comparator
V BIAS
VBIAS
VOVP
VOVP(RST)
OVP (OVP)
VISNS(PK)
V BIAS
IPK LIMIT
Comparator
gDCVISNS
fC
OVP (VFB)
OVP (OVP)
Current
Amplifier
-
OVP (VFB)
Comparator
VOVP
VOVP(RST)
Vm
VBIAS
+
OVP (VFB)
V BIAS
VCOMP
V BIAS
START
V BIAS
S
R
Q
INTEGRATED
RAMP +
OSCILLATOR
GATE
VM
0
V BIAS
VREF
VFB
MAX DUTY
CYCLE LIMIT
Voltage Error
Amplifier
COMP
UVLO
Block
UVLO
(POWER OFF)
VCC
VCOMP
Discharge
Bias & Internal
References
V BIAS
COM
UVLO/SLEEP
OLP
VOLP
STAND-BY
BOP
OPEN LOOP
Comparator
VBIAS
BOP
VBOP(EN)
VBOP
BROWN OUT
Comparator
© 2011 International Rectifier
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6
IR1152S
Lead Assignments & Definitions
PIN
1
SYMBOL
COM
DESCRIPTION
Ground
IR1152
GATE
COM
COMP
ISNS
2
COMP
ISNS
Voltage Loop Compensation
Current sense
3
VCC
VFB
4
BOP
Brown-out Fault Detect
Overvoltage Fault Detect/Enable
Output Voltage Sense
IC Supply voltage
5
OVP/EN
VFB
6
BOP
OVP/EN
7
VCC
8
GATE
Gate Drive Output
© 2011 International Rectifier
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7
IR1152S
The current sense signal is amplified by the current
amplifier by a factor gDC and fed into the summing
node where it is subtracted from Vm to generate the
summer voltage (= Vm–gDC*VISNS). The summer
voltage is compared with the PWM ramp by the
PWM comparator of the IC to determine the gate
drive duty cycle. The instantaneous duty is
mathematically given by:
IR1152 General Description
The µPFC IR1152 IC is intended for power factor
correction in continuous conduction mode Boost PFC
converters operating at fixed switching frequency with
average current mode control. The IC operates
based on IR's proprietary "One Cycle Control" (OCC)
PFC algorithm based on the concept of resettable
integrator.
D = (Vm - gDC.VISNS)/Vm
Assuming steady state conditions where the voltage
feedback loop is well regulated (Vm & VOUT are DC
signals) & hence instantaneous duty cycle follows
the boost-converter equation (D = 1 – VIN(t)/VOUT),
the control equation can be re-written as:
Theory of Operation
The OCC algorithm based on the resettable
integrator concept works using two loops - a slow
outer voltage loop and a fast inner current loop. The
outer voltage loop monitors the VFB pin and
generates an error signal which controls the
amplitude of the input current admitted into the PFC
converter. In this way, the outer voltage loop
maintains output voltage regulation. The voltage loop
bandwidth is kept low enough to not track the 2xfAC
ripple in the output voltage and thus generates an
almost DC error signal under steady state conditions.
The inner current loop maintains the sinusoidal profile
of the input current and thus is responsible for power
factor correction. This loop exploits the fact that, in a
power factor corrected system, by definition, the
information about the sinusoidal variation in input
voltage is inherently available in the input line current
(or boost inductor current). Thus there is no need to
sense the input voltage to generate a current
reference. The current loop employs the boost
inductor current information to generate PWM signals
with a proportional sinusoidal variation. This controls
the shape of the input current to be proportional to
and in phase with the input voltage. Average current
mode operation is envisaged by filtering the switching
frequency ripple from the current sense signal using
an appropriately sized on-chip RC filter. This filter
also contributes to the bandwidth of the current
control loop. Thus the filter bandwidth has to be high
enough to track the 120Hz rectified, sinusoidal
current waveform and also filter out the switching
frequency ripple in the inductor current. In IR1152
this averaging function can effectively filter high ripple
current ratios (as high as 40% at maximum input
current) to accommodate designs with small boost
inductances.
Vm = gDC.VISNS/(VIN(t)/VOUT
)
Further, recognizing that VISNS = IL(t).RSNS and re-
arranging yields:
gDC.IL(t).RSNS = VmVIN(t)/VOUT
Since Vm, VOUT & gDC are constant terms:
IL(t) α VIN(t)
Thus the inductor current follows the input voltage
waveform & by definition power factor correction is
achieved.
Feature set
Fixed Frequency Operation
The IC is programmed to operate at a fixed
frequency of 66kHz (Typ). Internalization of the
oscillator offers excellent noise immunity even in the
noisy PFC environment while integration of the
oscillator into the OCC core of the IC eliminates
need for digital calibration circuits. Both these
factors render the gate drive jitter free thus
contributing to elimination of audible noise in PFC
magnetics.
IC Supply Circuit & Low start-up current
The IR1152 UVLO circuit maintains the IC in UVLO
mode during start-up if VCC pin voltage is less than
the VCC turn-on threshold, VCC,ON and current
consumption is less than 75uA. Should VCC pin
voltage should drop below VCC,UVLO during normal
operation, the IC is pushed back into UVLO mode
and VCC pin has to exceed VCC,ON again for normal
operation. There is no internal voltage clamping of
the VCC pin.
The IC determines the boost converter instantaneous
duty cycle based on the resettable integrator concept.
The required signals are the voltage feedback loop
error signal Vm (which is the VCOMP pin voltage minus
a DC offset of VCOMP,START) and the current sense
signal VISNS. The resettable integrator generates a
cycle-by-cycle, saw-tooth signal called the PWM
Ramp which has an amplitude Vm and period 1/fSW
User initiated Micropower Sleep mode
The IC can be actively pushed into a micropower
Sleep Mode where current consumption is less than
75uA by pulling OVP/EN pin below the Sleep
threshold, VSLEEP even while VCC is above VCC,ON
.
This allows the user to disable PFC during
application stand-by situations in order to meet
stand-by regulations. Since VSLEEP is less than 1V,
even logic level signals can be employed.
hence a slope of Vm*fSW
.
© 2011 International Rectifier
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8
IR1152S
- OVP feature in IR1152 is "dual" and "dedicated".
There are 2 overvoltage comparators in IR1152 -
marked OVP(OVP) and OVP(VFB) in the block
diagram. Both these are identical in design, reference
the exact same thresholds and thus identical in
operation. The non-inverting input of OVP(VFB)
comparator is on the VFB pin while that of the
OVP(OVP) comparator is on the OVP/EN pin. When
either or both of the pin voltages exceeds VOVP, an
overvoltage situation is detected and the gate drive is
immediately terminated. The gate drive is re-enabled
only after both pin voltages are below VOVP(RST). The
redundancy offered by the 2 comparators and use of
a dedicated OVP/EN pin ensures the best possible
system overvoltage protection against extremes of
situations such as component failures, pin-to-pin
shorts etc.
IR1152 General Description
Programmable Soft Start
The soft start process controls the rate of rise of the
voltage feedback loop error signal thus providing a
linear increase of the RMS input current that the
PFC converter will admit. The soft start time is
essentially controlled by voltage error amplifier
compensation components selected and is
therefore user programmable to some degree
based on desired voltage feedback loop crossover
frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 750mA peak current drive
capability. The gate drive is internally clamped at
13V (Typ). Gate drive buffer circuits can be easily
driven with the GATE pin of the IC to suit any
system power level.
- Soft-current limit is an output voltage fold-back type
protection feature encountered when the PFC
converter input current exceeds to a point where the
Vm voltage saturates. As mentioned earlier, the
amplitude of input current is directly proportional to
Vm, the error voltage of the feedback loop. Vm is
clamped to a certain maximum voltage inside the IC
(given by VCOMP,EFF parameter in datasheet). If the
input current causes the Vm voltage to saturate at its
maximum value, then any further increase in input
current will cause the duty cycle to droop which
immediately forces the VOUT voltage of the PFC
converter to fold-back. Since the highest current is at
the peak of the AC sinusoid, the droop in duty cycle
commences at the peak of the AC sinusoid when the
soft-current limit is encountered. In most converters,
the design of the current sense resistor is performed
based on soft-current limit (i.e. Vm saturation) and at
the system condition which demands highest input
current (minimum VAC & maximum POUT).
System Protection Features
IR1152 protection features include Brown-out
protection (BOP), Open-loop protection (OLP),
Overvoltage protection (OVP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and VCC
under voltage lock-out (UVLO).
- BOP is based on direct input line sensing using a
resistor divider/RC filter network. If BOP pin falls
below the Brown-out protection threshold VBOP, a
Brown-out situation is immediately detected and
the following response is executed - the gate drive
pulse is disabled, VCOMP is actively discharged
and IC is pushed into Stand-by Mode. The IC re-
enters normal operation only after BOP pin
exceeds VBOP(EN). During start-up the IC is held in
Stand-by Mode until this pin exceeds VBOP(EN)
.
-
Cycle-by-cycle peak current limit protection
- OLP is activated whenever the VFB pin voltage
falls below VOLP threshold. Once open loop is
detected the following response is immediately
executed - the gate drive is immediately disabled,
VCOMP is actively discharged and the IC is
pushed into Stand-by mode. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by Mode until VFB
instantaneously turns-off the gate output whenever
the ISNS pin voltage exceeds VISNS(PK) threshold in
magnitude. The gate drive is held in the low state as
long as the overcurrent condition persists. The gate
drive is re-enabled when the magnitude of ISNS pin
voltage falls below the VISNS(PK) threshold. This
protection feature incorporates a leading edge
blanking circuit to improve noise immunity.
exceeds VOLP
.
© 2011 International Rectifier
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9
IR1152S
Pin OVP/EN: The OVP/EN pin is connected to the
non-inverting input of the OVP(OVP) overvoltage
comparator shown in the block diagram and thus is
used to detect output overvoltage situations. The
output voltage information is communicated to the
OVP pin using a resistive divider. This pin also
serves the second purpose of an ENABLE pin. The
OVP/EN pin can be used to activate the IC into
“micropower sleep” mode by pulling the voltage on
this pin below the VSLEEP threshold. The OVP/EN
pin can be used to activate the IC into “micropower
sleep” mode by pulling the voltage on this pin below
the VSLEEP threshold.
IR1152 Pin Description
Pin COM: This is ground potential pin of the IC.
All internal devices are referenced to this point.
Pin COMP: External circuitry from this pin to
ground compensates the system voltage loop and
programs the soft start time. The COMP pin is
essentially the output of the voltage error amplifier.
The voltage loop error signal Vm used in the control
algorithm is derived from VCOMP (Vm =VCOMP
–
VCOMP,START). VCOMP is actively discharged using an
internal resistance to below VCOMP,START threshold
whenever the IC is pushed into Stand-by mode
(BOP or OLP condition) or UVLO/Sleep mode. The
gate drive output and logic functions of the IC are
inactive if VCOMP is less than VCOMP,START. Also
during start-up, the VCOMP voltage has to be less
than VCOMP,START in order to commence operation
(i.e. a pre-bias on VCOMP will not allow IC to
commence operation).
Pin VFB: The converter output voltage is sensed
via a resistive divider and fed into this pin. VFB pin
is the inverting input of the output voltage error
amplifier. The non-inverting input of this amplifier is
connected to an internal 5V reference. The
impedance of the divider string must be low enough
that it does not introduce substantial error due to the
input bias currents of the amplifier, yet high enough
to minimize power dissipation. Typical value of
external divider impedance will be 2MΩ. The VFB
pin is also connected to the non-inverting input of
the OVP(VFB) overvoltage comparator as shown in
the block diagram and is used to detect output
overvoltage situations. Finally, VFB pin is also the
inverting input to the Open Loop comparator. The IC
is held in Stand-by Mode whenever VFB pin voltage
is below VOLP threshold. IC current consumption is
a few mA in this mode.
Pin ISNS: ISNS pin is tied to the input of the
current sense amplifier of the IC. The voltage at
this pin, which provides the current sense
information to the IC, has to be a negative voltage
wrt the COM pin. Also since the IC is based on
average current mode, the entire inductor current
information is necessary. A current sense resistor,
located below system ground along the return path
to the bridge rectifier, is the preferred current
sensing method. ISNS pin is also the inverting input
to the cycle-by-cycle peak current limit comparator.
Whenever VISNS exceeds VISNS(PK) threshold in
magnitude, the gate drive is instantaneously
disabled. Any external filtering of the ISNS pin must
be performed carefully in order to ensure that the
integrity of the current sense signal is maintained
for cycle-by-cycle peak current limit protection.
Pin VCC: This is the supply voltage pin of the IC
and sense node for the undervoltage lock out circuit.
It is possible to turn off the IC by pulling this pin
below the minimum turn off threshold voltage,
VCC(UVLO) without damage to the IC. This pin is
not internally clamped.
Pin BOP (Brown-out Protection): This pin is used
to sense the rectified AC input line voltage through
a resistor divider/capacitor network which is in
effect a voltage division and averaging network,
representing a scaled down signal of the average
rectified input voltage (average DC voltage + 2xfAC
ripple). During start-up the BOP pin voltage has to
exceed VBOP(EN) in order to enable the IC to exit
Stand-by mode and enter normal operation. A
Brown-out situation is detected whenever the pin
voltage falls below VBOP and the IC is pushed into
Stand-by mode. Subsequently the pin has to
exceed VBOP(EN) for the IC to exit Stand-by and
resume normal operation.
Pin GATE: This is the gate drive output of the IC.
This drive voltage is internally clamped to 13V(Typ)
and provides a drive current of ±0.75A peak with
matched rise and fall times.
© 2011 International Rectifier
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10
IR1152S
IR1152 Modes of operation
As VCOMP voltage rises gradually, the IC allows
a higher and higher RMS current into the PFC
converter. This controlled increase of the input
current amplitude contributes to reducing system
component stress during start-up.
Referenced to States & Transition Diagram
UVLO/Sleep Mode: The IC is in the UVLO/Sleep
mode when VCC pin voltage is below VCC,ON at
start-up or when VCC pin voltage drops below
VCC,UVLO during normal operation or when OVP/EN
pin voltage is below VSLEEP The UVLO/Sleep
.
Normal Mode: The IC enters the normal
operating mode once the soft start transition has
been completed (for all practical purposes there is
essentially no difference between the soft-start
and normal modes). At this point the gate drive is
switching and all protection functions of the IC are
active. If, from the normal mode, the IC is pushed
into either a Stand-by mode or UVLO/Sleep mode
then COMP pin is actively discharged below
VCOMP,START and system will go through soft-start
upon resumption of operation.
mode is accessible from any other state of
operation. This mode can be actively invoked by
pulling the OVP/EN pin below VSLEEP even if VCC
pin voltage is above VCC,ON. In the UVLO/Sleep
state, the gate drive circuit is inactive, most of the
internal circuitry is unbiased and the IC draws a
quiescent current of ISLEEP which is less than
75uA. Also, the internal logic of the IC ensures
that whenever the Sleep mode is actively invoked,
the COMP pin is actively discharged below
VCOMP,START threshold prior to entering the sleep
mode, in order to facilitate soft-start upon
resumption of operation.
OVP Mode: The IC enters OVP mode whenever
an overvoltage condition is detected. A system
overvoltage condition is recognized when VFB
and/or OVP/EN pin voltage exceeds VOVP
threshold. When this happens the IC immediately
disables the gate drive and holds it in that state.
The gate drive is re-enabled only when both
OVP/EN and VFB pin voltages are less than
VOVP(RST) threshold. This state is accessible from
both the soft start and normal modes of operation.
Stand-by Mode: The IC is placed in Stand-by
mode whenever an Open-loop and/or a Brown-out
situation is detected. A Brown-out situation is
sensed when BOP pin voltage is less than
VBOP(EN) prior to system start-up and when BOP
pin voltage drops below VBOP after start-up. An
Open-loop situation is sensed anytime VFB pin
voltage is less than VOLP. All internal circuitry is
biased in the Stand-by Mode, but the gate is
inactive and the IC draws a few mA of current.
This state is accessible from any other state of
operation of the IC. COMP pin is actively
discharged to below VCOMP,START whenever this
state is entered from normal operation in order to
facilitate soft-start upon resumption of operation.
IPK LIMIT Mode: The IC enters IPK LIMIT mode
whenever the magnitude of ISNS pin voltage
exceeds the VISNS(PK) threshold triggering cycle-by-
cycle peak over-current protection. When this
happens, the IC immediately disables the gate
drive and holds it in that state. Gate drive is re-
enabled when magnitude of ISNS pin voltage
drops below VISNS(PK) threshold. This state is
accessible from both the soft start and normal
modes of operation.
Soft Start Mode: During system start-up, the soft-
start mode is activated once the VCC voltage has
exceeded VCC,ON, the VFB pin voltage has
exceeded VOLP and BOP pin voltage has
exceeded VBOP(EN) and VCOMP voltage is less
than VCOMP,START i.e. a pre-bias on COMP pin
greater than VCOMP,START threshold will not allow IC
to commence operation. The soft start time is the
time required for the VCOMP voltage to charge
through its entire dynamic range i.e. through
VCOMP,EFF. As a result, the soft-start time is
dependent upon the component values selected
for compensation of the voltage loop on the
COMP pin. To an extent, keeping in mind the
voltage feedback loop considerations, the soft-
system start time is programmable.
© 2011 International Rectifier
www.irf.com
11
IR1152S
State & Transitions Diagram
AC POWER ON
Gate Inactive
Internal Circuits
Unbiased
UVLO/SLEEP
MODE
Gate Inactive
Internal Circuits Biased
Vcomp Discharged
VCC > VCCON
AND
VOVP > VSLEEP
VCC < VCC UVLO
OR
VOVP < VSLEEP
STAND – BY
MODE
Gate Inactive
Internal Circuits Biased
Vcomp Discharged
VFB > VOLP
VCC < VCC UVLO
OR
VOVP < VSLEEP
AND
VBOP > VBOP(EN)
AND
VFB < VOLP
OR
VBOP < VBOP (VTH)
VCOMP < VCOMP,START
VFB < VOLP
OR
VBOP < VBOP (VTH)
V
CC < VCC UVLO
OR
VOVP < VSLEEP
IPK LIMIT
SOFT START
FAULT
Gate Active
Present PulseTerminated
Gate Inactive
|VISNS| > |VISNS(PK)
|
Oscillator Active
CZ Charging
Oscillator Active
VCOMP Rising
|VISNS| < |VISNS(PK)
|
Cz fully charged
VCC < VCC UVLO
OR
VOVP <VSLEEP
|VISNS| > |VISNS(PK)
|VISNS| < |VISNS(PK)
|
V
FB < VOLP
OR
NORMAL
Gate Active
|
V
BOP < VBOP (VTH)
Oscillator Active
VOVP > VOVP (VTH)
OR
VFB > VOVP (VTH)
VOVP < VOVP(RST)
AND
VFB < VOVP(RST)
OVP FAULT
Present PulseTerminated
Gate Inactive
VCC < VCC UVLO
OR
VBOP < VBOP (VTH)
Oscillator Active
VOVP < VSLEEP
© 2011 International Rectifier
www.irf.com
12
IR1152S
IR1152 Timing Diagrams
VCC(ON)
VCC(UVLO)
UVLO
NORMAL
UVLO
VCC Undervoltage Lockout
1.56V
0.76V
STAND-BY
NORMAL
STAND-BY
Brown-out Protection
© 2011 International Rectifier
www.irf.com
13
IR1152S
Figure 1: Supply Current vs.
Supply Voltage
Figure 2: Undervoltage Lockout vs.
Temperature
Figure 4: Startup Current and Sleep
Current vs. Temperature
Figure 3: Icc Current vs. Temperature
© 2011 International Rectifier
www.irf.com
14
IR1152S
Figure 6: Reference Voltage vs.
Temperature
Figure 5: Switching Frequency vs.
Temperature
Figure 8: Voltage Error Amplifier Source
& Sink Current vs. Temperature
Figure 7: Voltage Error Amplifier
Transconductance vs. Temperature
© 2011 International Rectifier
www.irf.com
15
IR1152S
Figure 10: Peak Current Limit Threshold
Figure 9: Current Amplifier DC Gain vs.
Temperature
VISNS(PK) vs. Temperature
Figure 12: Brown-Out Protection
Thresholds vs. Temperature
Figure 11: Over Voltage Protection
Thresholds vs. Temperature
© 2011 International Rectifier
www.irf.com
16
IR1152S
Package Details: SOIC8N
© 2011 International Rectifier
www.irf.com
17
IR1152S
Tape and Reel Details: SOIC8N
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric
Imperial
Min
0.311
0.153
0.46
Code
A
B
C
D
E
F
G
H
Min
7.90
3.90
11.70
5.45
6.30
5.10
1.50
1.50
Max
8.10
4.10
12.30
5.55
6.50
5.30
n/a
Max
0.318
0.161
0.484
0.218
0.255
0.208
n/a
0.214
0.248
0.200
0.059
0.059
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
329.60
20.95
12.80
1.95
98.00
n/a
14.50
12.40
Max
330.25
21.45
13.20
2.45
102.00
18.40
17.10
14.40
Min
12.976
0.824
0.503
0.767
3.858
n/a
Max
13.001
0.844
0.519
0.096
4.015
0.724
0.673
0.566
0.570
0.488
© 2011 International Rectifier
www.irf.com
18
IR1152S
Part Marking Information
© 2011 International Rectifier
www.irf.com
19
IR1152S
Ordering Information
Standard Pack
Base Part Number Package Type
Complete Part Number
Form
Quantity
95
Tube/Bulk
IR1152SPBF
SOIC8N
IR1152S
Tape and Reel 2500
IR1152STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement
of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or
otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to
change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
© 2011 International Rectifier
www.irf.com
20
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