IR1153STRPBF [INFINEON]
FIXED 22.2kHz FREQUENCY; 固定频率22.2kHz
| 型号： | IR1153STRPBF |
| 厂家： | 
Infineon |
| 描述： | FIXED 22.2kHz FREQUENCY |
| 文件： | 总20页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Feb 21, 2011
IR1153S
FIXED 22.2kHz FREQUENCY, µPFC ONE CYCLE CONTROL
IC WITH BROWN-OUT PROTECTION
Features
• Cycle by cycle peak current limit
• VCC under voltage lockout
• Programmable soft start
• Micropower startup
• User initiated micropower “Sleep Mode”
• 750mA peak gate drive
• PFC IC with IR proprietary “One Cycle Control”
• Continuous conduction mode boost type PFC
• Fixed 22.2kHz switching frequency
• Average current mode control
• Input line sensed brownout protection
• Output overvoltage protection
• Latch immunity and ESD protection
• Open loop protection
Description
Package
The μPFC IR1153 power factor correction IC, based on IR proprietary
"One Cycle Control" (OCC) technique, provides for high PF, low THD
and excellent DC Bus regulation while enabling drastic reduction in
component count, PCB area and design time as compared to traditional
solutions. The IC is designed to operate in continuous conduction mode
Boost PFC converters with average current mode control at a fixed
22.2kHz switching frequency. The IR1153 features include input-line
sensed brown-out protection, dedicated pin for over voltage protection,
cycle by cycle peak current limit, open loop protection, VCC UVLO, soft-
start and micropower startup current of less than 75µA. In addition, for
standby power requirements, the IC can be driven into a micropower
sleep mode by pulling the OVP/EN pin low where the current
consumption is less than 75uA. IR1153 is available in SO-8 package.
IR1153 Application Diagram
ACIN1
-
+
VOUT
ACIN2
VCC
1
2
3
4
8
7
6
5
COM GATE
COMP VCC
ISNS VFB
BOPOVP/EN
IR1153
RTN
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© 2011 International Rectifier
IR1153S
Qualification Information
Industrial
Comments: This family of ICs has passed JEDEC’s Industrial qualification.
IR’s Consumer qualification level is granted by extension of the higher
Qualification Level
Industrial level.
MSL2 260°C
(per IPC/JEDEC J-STD-020)
Class A
Moisture Sensitivity Level
Machine Model
ESD
(per JEDEC standard JESD22-A115)
Class 1A
Human Body Model
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I, Level A
IC Latch-Up Test
RoHS Compliant
(per JESD78)
Yes
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these conditions is not implied.
All voltages are absolute voltages referenced to COM. Thermal resistance and power dissipation are
measured under board mounted and still air conditions.
Parameters
VCC Voltage
ISNS voltage
ISNS Current
VFB voltage
VOVP voltage
VBOP voltage
COMP voltage
Symbol
VCC
VISNS
IISNS
Min.
-0.3
-10
Max.
20
0.3
2
6.5
6.5
9
6.5
18
Units
V
V
mA
V
V
V
V
V
Remarks
Not internally clamped
-2
VFB
-0.3
-0.3
-0.3
-0.3
-0.3
VOVP
VBOP
VCOMP
VGATE
Gate Voltage
Junction Temperature Operating
Range
Storage Temperature
Thermal Resistance
TJ
TS
RθJA
PD
-40
-55
150
150
128
976
°C
°C
°C/W
mW
SOIC-8
TAMB=25°C SOIC-8
Package Power Dissipation
© 2011 International Rectifier
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2
IR1153S
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and
junction temperature range TJ from – 25° C to 125°C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Supply Section
Parameters
Supply Voltage Operating
Range
Symbol
VCC
Min.
Typ.
14
Max.
17
Units
V
Remarks
VCC Turn On Threshold
VCC Turn Off Threshold
(Under Voltage Lock Out)
VCC ON
VCC UVLO
12.2
9.4
13.1
10.1
14
V
10.8
V
VCC Turn On/Off Hysteresis VCC HYST
2.4
3
3.6
7
8
5
75
75
V
C
C
LOAD =1nF
LOAD =4.7nF
mA
mA
mA
µA
µA
Operating Current
ICC
3.5
26
26
OVP Mode, Inactive gate
VCC=VCC ON - 0.2V
Start-up Current
Sleep current
ICC START
ISLEEP
Pin OVP/EN=VSLEEP-0.2V
Bias on OVP/EN pin
Sleep Mode Threshold
VSLEEP
0.5
0.8
V
Oscillator Section
Parameters
Symbol
Min.
20.2
18.3
93
Typ.
Max.
24.2
25
99
0
Units
Remarks
TAMB=25°C
-25°C < TAMB < 125°C
VCOMP=5V
22.2
Fixed Oscillator Frequency
Maximum Duty Cycle
Minimum Duty Cycle
fSW
DMAX
DMIN
kHz
%
%
Pulse Skipping
Protection Section
Parameters
Open Loop Protection
(OLP)Threshold
Output Overvoltage
Protection (OVP)
Threshold
Symbol Min.
Typ. Max. Units
Remarks
%
VREF
VOLP
17
19
21
Bias on VFB pin
%
VREF
VOVP
104
106
108
Bias on OVP/EN pin
Bias on OVP/EN pin
Output Overvoltage
Protection Reset Threshold
%
VREF
VOVP(RST) 101
IOVP(Bias)
103
105
-0.2
0.86
OVP Input Bias Current
µA
V
Brown-out Protection
(BOP) Threshold
Brown-out Protection
Enable Threshold
VBOP
0.66
1.46
0.76
1.56
Bias on BOP pin
Bias on BOP pin
VBOP(EN)
IBOP(Bias)
1.66
-0.2
V
BOP Input Bias Current
µA
Peak Current Limit
Protection ISNS Voltage
Threshold (IPK LIMIT)
VISNS(PK) -0.58 -0.51 -0.44
V
Bias on ISNS pin
© 2011 International Rectifier
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3
IR1153S
Internal Voltage Reference Section
Parameters
Symbol
Min.
Typ.
Max.
Units
Remarks
Regulation Voltage on VFB pin,
TAMB=25°C
14V < VCC < 17V
-25°C < TAMB < 125°C, Note 1
Line & Temperature
Reference Voltage
Line Regulation
Temp Stability
VREF
RREG
TSTAB
ΔVTOT
4.9
5
10
0.4
5.1
20
V
mV
%
Total Variation
4.83
5.12
V
Voltage Error Amplifier Section
Parameters
Symbol
Min.
35
Typ.
49
Max.
59
Units
µS
Remarks
Transconductance
gm
30
17
-58
-80
44
58
80
-30
-17
TAMB=25°C
-25°C < TAMB < 125°C
TAMB=25°C
Source Current (Normal
Mode)
IOVEA(SRC)
µA
-44
35
IOVEA(SNK)
tSS
µA
msec
V
Sink Current (Normal Mode)
Soft Start Delay Time
(calculated)
-25°C < TAMB < 125°C
RGAIN=8kΩ, CZERO=0.33μF,
C
POLE=2nF
VCOMP Voltage (Fault)
VCOMP FLT
1
1.5
@100uA steady state
VCOMP EFF
IFB(Bias)
VOL
Effective VCOMP voltage
VFB Input Bias Current
Output Low Voltage
Output High Voltage
4.7
4.9
5.1
V
µA
V
-0.2
0.25
5.45
VOH
5
V
VCOMP
START
VCOMP Start Voltage
210
325
435
mV
© 2011 International Rectifier
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4
IR1153S
Current Amplifier Section
Parameters
DC Gain
Corner Frequency
Input Offset Voltage
ISNS Input Bias Current
Blanking Time
Symbol Min.
Typ. Max. Units
Remarks
gDC
5.65
2
V/V
kHz Average Current Mode, Note 1
fC
VIO
4
16
-13
470
mV
µA
ns
Note 1
IISNS(Bias)
TBLANK
-57
170
320
Gate Driver Section
Parameters
Symbol Min.
Typ. Max. Units
Remarks
Gate Low Voltage
VGLO
0.8
V
IGATE = 200mA
13.1
9.5
14.1
15.1
VCC=17V, Internally Clamped
VCC=11.5V
CLOAD = 1nF, VCC=15V
Gate High Voltage
Rise Time
VGTH
V
25
60
35
65
ns
ns
ns
ns
mA
V
tr
C
LOAD = 4.7nF, VCC=15V
CLOAD = 1nF, VCC=15V
LOAD = 4.7nF, VCC=15V
Fall Time
tf
C
Output Peak Current
Gate Voltage at Fault
IOPK
750
CLOAD = 4.7nF, VCC=15V, Note 1
IGATE = 20mA
VG fault
0.08
Note 1: Guaranteed by design, but not tested in production
© 2011 International Rectifier
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5
IR1153S
Block Diagram
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IR1153S
Lead Assignments & Definitions
IR1153
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7
IR1153S
The current sense signal is amplified by the current
amplifier by a factor gDC and fed into the summing
node where it is subtracted from Vm to generate the
summer voltage (= Vm–gDC*VISNS). The summer
voltage is compared with the PWM ramp by the
PWM comparator of the IC to determine the gate
drive duty cycle. The instantaneous duty is
mathematically given by:
IR1153 General Description
The μPFC IR1153 IC is intended for power factor
correction in continuous conduction mode Boost PFC
converters operating at fixed switching frequency with
average current mode control. The IC operates based
on IR's proprietary "One Cycle Control" (OCC) PFC
algorithm based on the concept of resettable
integrator.
D = (Vm - gDC.VISNS)/Vm
Assuming steady state condition where the voltage
feedback loop is well regulated (Vm & VOUT are DC
signals) & hence instantaneous duty cycle follows
the boost-converter equation (D = 1 – VIN(t)/VOUT),
the control equation can be re-written as:
Theory of Operation
The OCC algorithm based on the resettable integrator
concept works using two loops - a slow outer voltage
loop and a fast inner current loop. The outer voltage
loop monitors the VFB pin and generates an error
signal which controls the amplitude of the input current
admitted into the PFC converter. In this way, the outer
voltage loop maintains output voltage regulation. The
voltage loop bandwidth is kept low enough to not track
the 2xfAC ripple in the output voltage and thus
generates an almost DC error signal under steady
state conditions.
Vm = gDC.VISNS/(VIN(t)/VOUT
)
Further, recognizing that VISNS = IL(t).RSNS and re-
arranging yields:
gDC.IL(t).RSNS = VmVIN(t)/VOUT
Since Vm, VOUT & gDC are constant terms:
IL(t) α VIN(t)
Thus the inductor current follows the input voltage
waveform & by definition power factor correction is
achieved.
The inner current loop maintains the sinusoidal profile
of the input current and thus is responsible for power
factor correction. The information about the sinusoidal
variation in input voltage is inherently available in the
input line current (or boost inductor current). Thus
there is no need to sense the input voltage to
generate a current reference. The current loop
employs the boost inductor current information to
generate PWM signals with a proportional sinusoidal
variation. This controls the shape of the input current
to be proportional to and in phase with the input
voltage. Average current mode operation is envisaged
by filtering the switching frequency ripple from the
current sense signal using an appropriately sized on-
chip RC filter. This filter also contributes to the
bandwidth of the current control loop. Thus the filter
bandwidth has to be high enough to track the 120Hz
rectified, sinusoidal current waveform and also filter
out the switching frequency ripple in the inductor
current. In IR1153 this averaging function can
effectively filter high ripple current ratios (as high as
40% at maximum input current) to accommodate
designs with small boost inductances.
Feature set
Fixed Frequency Operation
The IC is programmed to operate at a fixed
frequency of 22.2kHz (Typ). Internalization of the
oscillator offers excellent noise immunity even in
the noisy PFC environment while integration of the
oscillator into the OCC core of the IC eliminates
need for digital calibration circuits. Both these
factors render the gate drive jitter free thus
contributing to elimination of audible noise in PFC
magnetics.
IC Supply Circuit & Low start-up current
The IR1153 UVLO circuit maintains the IC in UVLO
mode during start-up if VCC pin voltage is less than
the VCC turn-on threshold, VCC,ON and current
consumption is less than 75uA. Should VCC pin
voltage should drop below VCC,UVLO during normal
operation, the IC is pushed back into UVLO mode
and VCC pin has to exceed VCC,ON again for normal
operation. There is no internal voltage clamping of
the VCC pin.
User initiated Micropower Sleep mode
The IC determines the boost converter instantaneous
duty cycle based on the resettable integrator concept.
The required signals are the voltage feedback loop
error signal Vm (which is the VCOMP pin voltage minus a
DC offset of VCOMP,START) and the current sense signal
VISNS. The resettable integrator generates a cycle-by-
cycle, saw-tooth signal called the PWM Ramp which
has an amplitude Vm and period 1/fSW hence a slope of
The IC can be actively pushed into a micropower
Sleep Mode where current consumption is less
than 75uA by pulling OVP/EN pin below the Sleep
threshold, VSLEEP even while VCC is above VCC,ON
.
This allows the user to disable PFC during
application stand-by situations in order to meet
stand-by regulations. Since VSLEEP is less than 1V,
even logic level signals can be employed.
Vm*fSW
.
© 2011 International Rectifier
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8
IR1153S
- The OVP pin is a dedicated pin for overvoltage
protection that safeguards the system even if
there is a break in the VFB feedback loop due to
resistor divider failure etc. An overvoltage fault is
triggered when OVP pin voltage exceeds the VOVP
threshold of 106%VREF. The response of the IC
is to immediately terminate the gate drive output
and hold it in that state. The gate drive is re-
enabled only after OVP pin voltage drops below
VOVP(RST) threshold of 103% VREF. The exact
voltage level at which overvoltage protection is
triggered can be programmed by the user by
carefully designing the OVP pin resistor divider. It
is recommended NOT to set the OVP voltage
trigger limit less than 106% of DC bus voltage,
since this can endanger the situation where the
OVP reset limit will be less than the DC bus
voltage regulation point – in this condition the
voltage loop can become unstable.
IR1153 General Description
Programmable Soft Start
The soft start process controls the rate of rise of the
voltage feedback loop error signal thus providing a
linear increase of the RMS input current that the
PFC converter will admit. The soft start time is
essentially controlled by voltage error amplifier
compensation components selected and is
therefore user programmable to some degree
based on desired voltage feedback loop crossover
frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 750mA peak current drive
capability. The gate drive is internally clamped at
14.1V (Typ). Gate drive buffer circuits (especially
cost-effective base-followers) can be easily driven
with the GATE pin of the IC to suit any system
power level.
- Soft-current limit is an output voltage fold-back
type protection feature encountered when the
PFC converter input current exceeds to a point
where the Vm voltage saturates. As mentioned
earlier, the amplitude of input current is directly
proportional to Vm, the error voltage of the
feedback loop. Vm is clamped to a certain
maximum voltage inside the IC (given by
VCOMP,EFF parameter in datasheet). If the input
current causes the Vm voltage to saturate at its
maximum value, then any further increase in input
current will cause the duty cycle to droop which
immediately forces the VOUT voltage of the PFC
converter to fold-back. Since the highest current
is at the peak of the AC sinusoid, the droop in
duty cycle commences at the peak of the AC
sinusoid when the soft-current limit is
encountered. In most converters, the design of
the current sense resistor is performed based on
soft-current limit (i.e. Vm saturation) and at the
system condition which demands highest input
current (minimum VAC & maximum POUT).
System Protection Features
IR1153 protection features include Brown-out
protection (BOP), Open-loop protection (OLP),
Overvoltage protection (OVP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and VCC
under voltage lock-out (UVLO).
- BOP is based on direct input line sensing using a
resistor divider/RC filter network. If BOP pin falls
below the Brown-out protection threshold VBOP, a
Brown-out situation is immediately detected the
following response is executed - the gate drive
pulse is disabled, VCOMP is actively discharged
and IC is pushed into Stand-by Mode. The IC re-
enters normal operation only after BOP pin
exceeds VBOP(EN). During start-up the IC is held in
Stand-by Mode until this pin exceeds VBOP(EN)
.
- OLP is activated whenever the VFB pin voltage
falls below VOLP threshold. Once open loop is
detected the following response is immediately
executed - the gate drive is immediately disabled,
VCOMP is actively discharged and the IC is
pushed into Stand-by mode. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by Mode until VFB
- Cycle-by-cycle peak current limit protection
instantaneously turns-off the gate output
whenever the ISNS pin voltage exceeds VISNS(PK)
threshold in magnitude. The gate drive is held in
the low state as long as the overcurrent condition
persists. The gate drive is re-enabled when the
magnitude of ISNS pin voltage falls below the
VISNS(PK) threshold. This protection feature
incorporates a leading edge blanking circuit to
improve noise immunity.
exceeds VOLP
.
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9
IR1153S
IR1153 Pin Description
Pin COM: This is ground potential pin of the IC.
All internal devices are referenced to this point.
Subsequently the pin has to exceed VBOP(EN) for
the IC to exit Stand-by and resume normal
operation.
Pin COMP: External circuitry from this pin to
ground compensates the system voltage loop and
programs the soft start time. The COMP pin is
essentially the output of the voltage error
amplifier. The voltage loop error signal Vm used in
the control algorithm is derived from VCOMP (Vm
=VCOMP–VCOMP,START). VCOMP is actively discharged
using an internal resistance to below VCOMP,START
threshold whenever the IC is pushed into Stand-
by mode (BOP or OLP condition) or UVLO/Sleep
mode. The gate drive output and logic functions of
the IC are inactive if VCOMP is less than
Pin OVP/EN: The OVP/EN pin is connected to the
non-inverting input of the OVP(OVP) overvoltage
comparator shown in the block diagram and thus
is used to detect output overvoltage situations.
The output voltage information is communicated
to the OVP pin using a resistive divider. This pin
also serves the second purpose of an ENABLE
pin. The OVP/EN pin can be used to activate the
IC into “micropower sleep” mode by pulling the
voltage on this pin below the VSLEEP threshold.
V
COMP,START. Also during start-up, the VCOMP
Pin VFB: The converter output voltage is sensed
via a resistive divider and fed into this pin. VFB
pin is the inverting input of the output voltage error
amplifier. The non-inverting input of this amplifier
is connected to an internal 5V reference. The
impedance of the divider string must be low
enough that it does not introduce substantial error
due to the input bias currents of the amplifier, yet
high enough to minimize power dissipation.
Typical value of external divider total impedance
will be around 2MΩ. VFB pin is also the inverting
input to the Open Loop comparator. The IC is held
in Stand-by Mode whenever VFB pin voltage is
below VOLP threshold.
voltage has to be less than VCOMP,START in order to
commence operation (i.e. a pre-bias on VCOMP
will not allow IC to commence operation).
Pin ISNS: ISNS pin is tied to the input of the
current sense amplifier of the IC. The voltage at
this pin, which provides the current sense
information to the IC, has to be a negative voltage
wrt the COM pin. Also since the IC is based on
average current mode, the entire inductor current
information is necessary. A current sense resistor,
located below system ground along the return
path to the bridge rectifier, is the preferred current
sensing method. ISNS pin is also the inverting
input to the cycle-by-cycle peak current limit
comparator. Whenever VISNS exceeds VISNS(PK)
threshold in magnitude, the gate drive is
instantaneously disabled. Any external filtering of
the ISNS pin must be performed carefully in order
to ensure that the integrity of the current sense
signal is maintained for cycle-by-cycle peak
current limit protection.
Pin VCC: This is the supply voltage pin of the IC
and sense node for the undervoltage lock out
circuit. It is possible to turn off the IC by pulling
this pin below the minimum turn off threshold
voltage, VCC(UVLO) without damage to the IC. This
pin is not internally clamped.
Pin GATE: This is the gate drive output of the IC.
It provides a drive current of ±0.75A peak with
matched rise and fall times. The gate drive output
of the IC is clamped at 14.1V(Typ).
Pin BOP (Brown-out Protection): This pin is
used to sense the rectified AC input line voltage
through a resistor divider/capacitor network which
is in effect a voltage division and averaging
network, representing a scaled down signal of the
average rectified input voltage (average DC
voltage + 2xfAC ripple). During start-up the BOP
pin voltage has to exceed VBOP(EN) in order to
enable the IC to exit Stand-by mode and enter
normal operation.
detected whenever the pin voltage falls below
BOP and the IC is pushed into Stand-by mode.
A
Brown-out situation is
V
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10
IR1153S
IR1153 Modes of operation
As VCOMP voltage rises gradually, the IC allows
a higher and higher RMS current into the PFC
converter. This controlled increase of the input
current amplitude contributes to reducing system
component stress during start-up.
Referenced to States & Transition Diagram
UVLO/Sleep Mode: The IC is in the UVLO/Sleep
mode when VCC pin voltage is below VCC,ON at
start-up or when VCC pin voltage drops below
V
CC,UVLO during normal operation or when OVP/EN
Normal Mode: The IC enters the normal
operating mode once the soft start transition has
been completed (for all practical purposes there is
essentially no difference between the soft-start
and normal modes). At this point the gate drive is
switching and all protection functions of the IC are
active. If, from the normal mode, the IC is pushed
into either a Stand-by mode or UVLO/Sleep mode
then COMP pin is actively discharged below
VCOMP,START and system will go through soft-start
upon resumption of operation.
pin voltage is below VSLEEP The UVLO/Sleep
.
mode is accessible from any other state of
operation. This mode can be actively invoked by
pulling the OVP/EN pin below VSLEEP even if VCC
pin voltage is above VCC,ON. In the UVLO/Sleep
state, the gate drive circuit is inactive, most of the
internal circuitry is unbiased and the IC draws a
quiescent current of ISLEEP which is less than
75uA. Also, the internal logic of the IC ensures
that whenever the Sleep mode is actively invoked,
the COMP pin is actively discharged below
VCOMP,START threshold prior to entering the sleep
mode, in order to facilitate soft-start upon
resumption of operation.
OVP Mode: The IC enters OVP mode whenever
an overvoltage condition is detected. A system
overvoltage condition is recognized when
OVP/EN pin voltage exceeds VOVP threshold.
When this happens the IC immediately disables
the gate drive and holds it in that state. The gate
drive is re-enabled only when OVP/EN pin
voltages are less than VOVP(RST) threshold. This
state is accessible from both the soft start and
normal modes of operation.
Stand-by Mode: The IC is placed in Stand-by
mode whenever an Open-loop and/or a Brown-out
situation is detected. A Brown-out situation is
sensed when BOP pin voltage is less than
VBOP(EN) prior to system start-up and when BOP
pin voltage drops below VBOP after start-up. An
Open-loop situation is sensed anytime VFB pin
voltage is less than VOLP. All internal circuitry is
biased in the Stand-by Mode, but the gate is
inactive and the IC draws a few mA of current.
This state is accessible from any other state of
operation of the IC. COMP pin is actively
discharged to below VCOMP,START whenever this
state is entered from normal operation in order to
facilitate soft-start upon resumption of operation.
IPK LIMIT Mode: The IC enters IPK LIMIT mode
whenever the magnitude of ISNS pin voltage
exceeds the VISNS(PK) threshold triggering cycle-by-
cycle peak overcurrent protection. When this
happens, the IC immediately disables the gate
drive and holds it in that state. Gate drive is re-
enabled when magnitude of ISNS pin voltage
drops below VISNS(PK) threshold. This state is
accessible from both the soft start and normal
modes of operation.
Soft Start Mode: During system start-up, the soft-
start mode is activated once the VCC voltage has
exceeded VCC,ON, the VFB pin voltage has
exceeded VOLP and BOP pin voltage has
exceeded VBOP(EN) and VCOMP voltage is less
than VCOMP,START i.e. a pre-bias on COMP pin
greater than VCOMP,START threshold will not allow IC
to commence operation. The soft start time is the
time required for the VCOMP voltage to charge
through its entire dynamic range i.e. through
VCOMP,EFF. As a result, the soft-start time is
dependent upon the component values selected
for compensation of the voltage loop on the
COMP pin. To an extent, keeping in mind the
voltage feedback loop considerations, the soft-
system start time is programmable.
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11
IR1153S
State & Transitions Diagram
AC POWER ON
Gate Inactive
Internal Circuits
Unbiased
UVLO/SLEEP
MODE
Gate Inactive
Internal Circuits Biased
Vcomp Discharged
VCC > VCCON
AND
VOVP > VSLEEP
VCC < VCC UVLO
OR
VOVP < VSLEEP
STAND – BY
MODE
Gate Inactive
Internal Circuits Biased
Vcomp Discharged
VFB > VOLP
VCC < VCC UVLO
OR
VOVP < VSLEEP
AND
VBOP > VBOP(EN)
AND
VFB < VOLP
OR
VBOP < VBOP (VTH)
VCOMP < VCOMP,START
VFB < VOLP
OR
VBOP < VBOP (VTH)
VCC < VCC UVLO
OR
VOVP < VSLEEP
SOFT START
IPK LIMIT
Gate Active
Oscillator Active
CZ Charging
FAULT
Present PulseTerminated
Gate Inactive
|VISNS| > |VISNS(PK)
|
|
VCOMP Rising
Oscillator Active
|VISNS| < |VISNS(PK)
CZ Fully Charged
VCC < VCC UVLO
OR
VOVP <VSLEEP
|VISNS| > |VISNS(PK)
|VISNS| < |VISNS(PK)
|
VFB < VOLP
OR
VBOP < VBOP (VTH)
NORMAL
|
Gate Active
Oscillator Active
VOVP > VOVP (VTH)
VOVP < VOVP(RST)
OVP FAULT
Present PulseTerminated
Gate Inactive
VCC < VCC UVLO
OR
VBOP < VBOP (VTH)
Oscillator Active
VOVP < VSLEEP
© 2011 International Rectifier
www.irf.com
12
IR1153S
IR1153 Timing Diagrams
VCC(ON)
VCC(UVLO)
UVLO
NORMAL
UVLO
VCC Undervoltage Lockout
1.5V
0.7V
STAND-BY
NORMAL
STAND-BY
Brown-out Protection
VSLEEP
SLEEP
NORMAL
SLEEP
Micropower Sleep
© 2011 International Rectifier
www.irf.com
13
IR1153S
Figure 2: Undervoltage Lockout vs.
Temperature
Figure 1: Supply Current vs.
Supply Voltage
Figure 3: Icc Currrent vs. Temperature
Figure 4: Startup Current and Sleep
Current vs. Temperature
© 2011 International Rectifier
www.irf.com
14
IR1153S
Figure 6: Reference Voltage vs.
Temperature
Figure 5: Switching Frequency vs.
Temperature
Figure 8: Voltage Error Amplifier Source
& Sink Current vs. Temperature
Figure 7: Voltage Error Amplifier
Transconductance vs. Temperature
© 2011 International Rectifier
www.irf.com
15
IR1153S
Figure 10: Peak Current Limit Threshold
Figure 9: Current Amplifier DC Gain vs.
Temperature
VISNS(PK) vs. Temperature
Figure 12: Brown-Out Protection
Thresholds vs. Temperature
Figure 11: Over Voltage Protection
Thresholds vs. Temperature
© 2011 International Rectifier
www.irf.com
16
IR1153S
Package Details: SOIC8N
© 2011 International Rectifier
www.irf.com
17
IR1153S
Tape and Reel Details: SOIC8N
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric
Imperial
Min
0.311
0.153
0.46
Code
A
B
C
D
E
F
G
H
Min
7.90
3.90
11.70
5.45
6.30
5.10
1.50
1.50
Max
8.10
4.10
12.30
5.55
6.50
5.30
n/a
Max
0.318
0.161
0.484
0.218
0.255
0.208
n/a
0.214
0.248
0.200
0.059
0.059
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
329.60
20.95
12.80
1.95
98.00
n/a
14.50
12.40
Max
330.25
21.45
13.20
2.45
102.00
18.40
17.10
14.40
Min
12.976
0.824
0.503
0.767
3.858
n/a
Max
13.001
0.844
0.519
0.096
4.015
0.724
0.673
0.566
0.570
0.488
© 2011 International Rectifier
www.irf.com
18
IR1153S
Part Marking Information
© 2011 International Rectifier
www.irf.com
19
IR1153S
Ordering Information
Standard Pack
Base Part Number Package Type
Complete Part Number
Form
Quantity
95
Tube/Bulk
IR1153SPBF
SOIC8N
IR1153S
Tape and Reel 2500
IR1153STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement
of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or
otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to
change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
© 2011 International Rectifier
www.irf.com
20
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