IR1161LPBF_15_技术文档

IR1161LPBF

SMARTRECTIFIER^TMControl IC

Product Summary

Features

Flyback,

Resonant Half-bridge



Secondary side synchronous rectification

Topology

controller



DCM, CrCM Flyback and resonant half-bridge

topologies

VD

200V



Direct sensing of MOSFET drain voltage up to 200V

Max 500kHz switching frequency

Anti-bounce logic and UVLO protection

Micropower start-up & ultra-low quiescent current

50ns turn-off propagation delay

Programmable Minimum On Time

Vcc Operating voltage range 4.75V to 18V

Cycle by Cycle MOT Check Circuit

Lead-free

V_CC

4.75V ~ 18V

+1A & -2.5A

50ns (typical)

I_o+& I _o-

Turn on Propagation

Delay

Turn off Propagation

Delay

Compatible with 0.3W Standby, Energy Star, CECP,

etc.

Package Options

Applications



Charger, AC-DC adapters

5-Pin SOT-23

Application Diagram

+

-

LOAD

Primary

Controller

MOT

GND

VCC

VD

4

3

2

1

GATE

5

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Quantity

Form

IR1161LPBF

5L-SOT-23

Tape and Reel

3000

IR1161LTRPBF

1

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Table of Contents

Ordering Information

Page

1

3

Description

Absolute Maximum Ratings

Electrical Characteristics

Functional Block Diagram

Input/Output Pin Equivalent Circuit Diagram

Pin Definitions

4

5

7

8

9

Pin Assignments

9

Application Information and Additional Details

Package Details

11

18

19

21

22

Tape and Reel Details

Part Marking Information

Qualification Information

2

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Description

The IR1161 is a synchronous rectification control IC designed to drive an N-Channel power MOSFET in a

secondary output rectifier circuit. The MOSFET gate is switched on and off to bypass its body diode during the of

the conduction period to minimize power dissipation, remaining off during the blocking period. The drain to source

voltage is accurately sensed to determine the direction and magnitude of the current allowing the IR1161 to turn

the MOSFET on and off at close to zero current.

An integrated cycle-by-cycle minimum on time (MOT) protection circuit automatically detects a no load condition

and turns off the gate driver output preventing negative current from flowing through the MOSFET.

Ruggedness and noise immunity are accomplished using an advanced blanking scheme and double-pulse

suppression, which allows reliable operation in all operating modes.

3

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Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to GND, all currents are defined positive into any pin. The thermal

resistance and power dissipation ratings are measured under board mounted and still air conditions.

†

—



†

—

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.

Symbol

Definition

Supply voltage

Drain Sense Voltage

Min.

Max.

18

Units

V_CC

4.75

V

-3 ^††

-40

—

V_D

200

125

††

V_D

≤

Recommended Component Values

Symbol

R_MOT

Component

MOT pin resistor value

V_CCdecoupling capacitor value

Min.

5

1

Max.

100

—

Units

k

µF

CV_CC

4

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Electrical Characteristics

V_CC=12V and T_A=25°C unless otherwise specified. The output voltage and current (V_Oand I_O) parameters are

referenced to GND pin.

—

C_LOAD=1nF,

f_SW=300kHz

—

RMOT=50k

V_CC= V_{CC ON}- 0.1V

—

-10

—

230

-7.5

7

—

30

t_BLANK

Blanking Pulse Duration

Reset Threshold

8

13

24

µs

V

1.18

400

Blanking Time of Reset

—

ns

RMOT=5k

RMOT=24k

RMOT=50k

5

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Electrical Characteristics

V_CC=12V and T_A=25°C unless otherwise specified. The output voltage and current (V_Oand I_O) parameters are

referenced to GND pin.

Gate Driver Section

I_GATE=100mA,

—

V_CC=12V

V_CC=12V, I_GATE=5mA

V_CC=5V, I_GATE=5mA

—

C_LOAD=1nF, V_CC=12V

V_DSto V_GATE– V_DS

goes down from 6V to

-1V

V_DSto V_GATE– V_DS

goes up from

-1V to 6V

—

I_GATE=100mA

I_GATE=-100mA



GBD – parameter is guaranteed by design and is not tested.

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Functional Block Diagram

VCC

MOT

UVLO

Cycle by Cycle

MOT Check

Circuit

VCC

VD

S

R

Q

Min ON Time

VTH2

RESET

VGATE

DRIVER

VTH1

GND

Arming Logic

& Blanking

SET

VTH3

7

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I/O Pin Equivalent Circuit Diagram

VCC

ESD

Diode

MOT

GATE

ESD

Diode

GND

VD

R_ESD

ESD

Diode

200V

Diode

GND

8

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Pin Definitions

PIN#

Symbol

VCC

Description

Supply Voltage

1

2

3

4

5

GND

MOT

VD

Ground

Minimum On Time Program Input

FET Drain Sensing

Gate Drive Output

GATE

Pin Assignments

1

2

3

5

GATE

VD

VCC

GND

MOT

4

Detailed Pin Description

VCC: Power Supply

The supply voltage pin is monitored by the under voltage lockout circuit. It is possible to turn off the IC entering

UVLO mode by pulling this pin below the minimum turn off threshold voltage for micro power consumption.

To avoid noise problems a bypass ceramic capacitor connected to Vcc and GND is needed, which should be

placed as close as possible to the IC. A low value series resistor to Vcc may also be added if extra filtering is

required. This pin is internally clamped to 20V.

GND: Ground

This is the IC ground reference connected to the SR MOSFET source.

MOT: Minimum On Time

The MOT programming pin controls the amount of minimum on time. Once V_TH2is crossed for the first time, the

gate signal will transition high and turn on the power MOSFET. Spurious ringing and oscillations can falsely trigger

the input comparator to switch the output off. The MOT prevents this by blanking the input comparator to keep the

SR MOSFET on for a minimum time. The MOT is typically programmed between 500ns and 2us by using an

external resistor referenced to GND.

VD: Drain Voltage Sense

VD is the voltage sense pin for the SR MOSFET drain. This is a high voltage pin therefore particular care must be

taken in properly routing the connection.

An additional RC filter can be placed at this input to improve noise immunity, however only small values (e.g. 100Ω

+ 100pF) may be used to avoid introducing significant delay to the control input.

GATE: Gate Drive Output

The gate drive output provides 1A source and 2.5A sink current capability. Although this output may be directly

connected to the power MOSFET gate the use of a minimal gate resistor is recommended, especially when using

multiple MOSFETs in parallel.

Care must be taken to keep the gate loop as short and as small as possible in order to minimize inductance and

achieve optimal switching performance.

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Application Information and Additional Details

State Diagram

POWER ON

Gate Inactive

UVLO MODE

VCC < VCC on

ICC < ICC start

Gate Inactive

VCC > VCCon,

& V_DS>V_TH3

VCC < VCCuvlo

NORMAL

Gate Active

Gate PW ≥ MOT

Cycle by Cycle MOT Check Enabled

V_DS>V_TH1@ MOT

V_DS<V_TH1@ MOT

MOT PROTECTION

MODE

Gate Output Disabled

UVLO Mode

The IC remains in the under-voltage lockout condition until VCC exceeds the turn on threshold voltage, V_{CC ON}

During the time the IC remains in the UVLO state, the gate drive circuit is inactive and only a very small quiescent

.

current I_{CC START}is consumed. UVLO mode is accessible from any other operating state whenever VCC < V_{CC UVLO}

.

Normal Mode and Synchronized Enable Function

The IC enters into normal operating mode once the UVLO voltage has been exceeded. When the IC enters the

Normal Mode, the GATE output remains disabled (stays low) for a start-up delay time in the range of 100us, then

V_DSmust transition above V_TH3two times to enable synchronous rectification. This ensures that the GATE output

can never be enabled in the middle of a switching cycle. The first gate pulse after activation is blocked and the

cycle by cycle MOT protection circuit is enabled. This logic avoids reverse currents through the SR MOSFET from

occurring during startup. The gate will continuously drive the SR MOSFET after completing this startup sequence.

MOT Protection Mode

If the secondary current conduction time is shorter than the MOT (Minimum On Time), the following driver output

pulse is disabled. This function can avoid reverse current from occurring when the system is switching at very low

duty-cycles under very light or zero load conditions. System standby power consumption is reduced by disabling

the GATE output. The cycle by cycle MOT check circuit is always activated under Normal Mode and MOT

Protection Mode so that the IC will automatically resume normal operation only once the load increases to a level

where the secondary current conduction time exceeds MOT.

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General Description

The direction of the rectified current in the SR MOSFET is sensed by the IR1161 through its high voltage drain

sensing input VD, which monitors the drain to source voltage drop. Conduction occurs through the body diode

when the MOSFET is switched off and when it is switched on, the R_DSonacts as a shunt resistance. The GATE

drive to the MOSFET is switched on only when current is flowing from source to drain. Internal blanking logic is

used to prevent spurious transitions and guarantee correct operation under different load conditions.

The IR1161 is suitable for DCM or CrCM Flyback and Resonant Half-Bridge topologies.

V_Gate

V_DS

V_TH2

V_TH1

V_TH3

Figure 1: Input comparator thresholds

Flyback Application

The typical application circuit of IR1161 in Flyback converter is shown on page 1.

Turn-on phase

When the conduction phase of the SR MOSFET is initiated, current will start flowing through its body diode

producing a negative V_DSvoltage across it. The body diode has a much higher forward voltage drop than that

created by the MOSFET on resistance and will therefore becoming more negative than the turn-on threshold V_TH2

.

At that point the IR1161 will drive the gate high, which will in turn cause V_DSto transition to a much smaller

negative voltage. This voltage step is usually accompanied by some amount of ringing that could potentially trigger

the IR1161 to turn off prematurely. To prevent this, a Minimum On Time (MOT) blanking period is maintains the

SR MOSFET on for a minimum period of time, which is externally adjustable.

Turn-off phase

At the end of the conduction period the current reduces to zero, causing V_DSto cross the turn-off threshold V_TH1

.

The IR1161 will then turn the SR MOSFET gate off and current will start flowing again through the body diode

causing a negative going V_DSvoltage step. Depending on the amount of residual current, V_DScould potentially

trigger the turn on threshold once again. For this reason V_TH2is blanked for a certain amount of time (T_BLANK) after

V_TH1has been triggered. The blanking time is internally set and is reset only by V_DScrossing the positive threshold

V_TH3and remaining above this threshold for more than reset blanking time t_BRST. Once reset the IR1161 is ready for

next conduction cycle.

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I_PRIM

V_PRIM

time

T3

T1

T2

I_SEC

V_SEC

time

Figure 2: Flyback Primary and secondary currents and voltages for DCM mode

I_PRIM

V_PRIM

time

T2

T1

I_SEC

V_SEC

time

Figure 3: Flyback Primary and secondary currents and voltages for CrCM mode

V_TH3

I_SEC

V_DS

T1

T2

time

V_TH1

V_TH2

TDoff

TDon

Gate Drive

Blanking

time

MOT

Tblanking

Figure 4: Flyback secondary side DCM/CrCM operation

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IR1161LPBF

Resonant Half-Bridge Application

The typical application circuit of IR1161 in LLC half-bridge is shown in Figure 5.

MOT

4

3

VD

GND

2

GATE

5

1

VCC

LOAD

VCC

1

5

GATE

2

3

GND

MOT

VD

4

Figure 5: Resonant half-bridge application circuit

In the resonant half-bridge converter the turn-on phase and turn-off phase are similar to the Flyback except that

the current shape is sinusoidal. The typical operating waveform is seen below in figure 6.

V_TH3

I_DS

V_DS

T1

T2

V_TH1

V_TH2

Gate Drive

Blanking

MOT

t_BLANK

time

Figure 6: Resonant half-bridge operation waveform

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Setting the MOT Time

The MOT time is set by an external resistor connected from the MOT pin to GND.

T_MOT= 2 x 10^-11x R_MOT

MOT Protection Mode

The MOT protection function is designed to avoid reverse current occurring in the SR MOSFET. This could

happen at light load if the MOT time is set longer that the actual conduction time. The IR1161 disables the gate

drive output in MOT protection mode as described in the previous section and automatically resumes normal

operation when the load increases to a level where the current conduction time is longer than MOT.

This function works in both Flyback and resonant half-bridge topologies. Figure 7 illustrates operation in a DCM

Flyback converter.

V_DS

I_SEC

Gate Drive

time

MOT

Sensed VD>V_TH1at

Disable the next gate output

the end of MOT

Figure 7: MOT Protection Mode

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Synchronized Enable Function

This function guarantees that the GATE drive always switches high at the beginning of a switching cycle. This is

essential since mid-cycle switch on with the MOT function would force the MOSFET to remain on past the

conduction period leading to reverse conduction.

This function works in both Flyback and resonant half-bridge topologies. Figure 8 is an example in resonant half-

bridge converter.

VGATE

VDS

UVLO

Idrain

V_th3

IC activated in the middle

of a conduction cycle,

VGATE stays low.

The first GATE pulse is blanked.

Enable MOT protection.

Vgate has output

from the 4th cycle

VD exceeds Vth3

for 2 cycles

Figure 8: Synchronized Enable Function (resonant half-bridge)

Driving a Logic Level MOSFET

An external gate drive pull down circuit is recommended when driving a logic level MOSFET.

This is because during power up and power down the drain may be switching while the IR1161 remains in UVLO.

SR MOSFET drain to gate capacitance causes voltage pulses to appear at the gate that could have sufficient

amplitude to reach the turn on threshold because the IR1161 gate sink capability is limited when VCC < 2V.

The following circuit ensures that the gate voltage remains below 1V under all conditions:

GATE

5

Dg

Rg

VCC

GND

SR MOSFET

1

2

3

CVcc

VD

4

MOT

Qsink

Rb

RMOT

Figure 9: Gate drive circuit for logic level SR MOSFET

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Vcc Clamping Circuit

The IR1161 can be directly biased by the converter output voltage V_OUTif this falls within the recommended range

of Vcc although a low value series resistor may be required for optimal noise filtering. For higher system output

voltages a clamping circuit is recommended to limit Vcc. This also lowers the gate drive voltage and reduces

losses if V_OUTis above 15V.

Many clamping circuits are available from simple zener diode clamping to bipolar linear regulators. Figure 10 is

one example; in this circuit the Vcc voltage will be clamped to a voltage of V_OUT- V_ZD1- V_BE. The circuit also

provides turn-on delay to the IR1161, which will activate only when the output voltage exceeds V_CCON+ V_ZD1+ V_BE.

R1 and R2 are optional for more precise control of the Vcc clamping voltage.

Vout

R1

Optional

ZD1

GATE

VCC

1

2

3

5

R2

R3 CVcc

GND

MOT

VD

4

Figure 10: Vcc clamping circuit

Shutdown Circuit

The IR1161 can be disabled by pulling V_CCbelow the V_{CC UVLO}threshold.

Vout

R1

ZD1

GATE

5

VCC

GND

MOT

Shutdown

1

2

3

CVcc

R3

VD

4

Figure 11: IR1161 Enable/Disable circuit

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General Timing Waveform

V_TH1

V_DS

V_TH2

t_Don

t_Doff

V_Gate

90%

10%

t_rise

t_fall

Figure 12: Timing waveform

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4.7

4.6

4.5

4.4

4.3

I_QCC

0.70

0.65

0.60

0.55

0.50

VCC ON

VCC UVLO

-50 °C

0 °C

50 °C

Temperature

100 °C

150 °C

-50 °C

0 °C

50 °C

100 °C

150 °C

Temperature

Figure 13: Undervoltage Lockout vs. Temperature

Figure 14: Icc Quiescent Current vs. Temperature

Icc @300KHz, C_LOAD=1nF

5.6

I_{CC START}

13.0

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

12.0

11.0

10.0

9.0

8.0

7.0

6.0

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

100 °C

150 °C

Temperature

Figure 15: Icc Supply Current @1nF Load vs.

Temperature

Figure 16: Icc Startup Current vs. Temperature

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-2.0

-3.0

-4.0

-5.0

-6.0

-200.0

-210.0

-220.0

-230.0

-240.0

-250.0

-260.0

-50 °C

0 °C

50 °C

Temperature

100 °C

150 °C

-50 °C

0 °C

50 °C

Temperature

100 °C

150 °C

Figure 17: V_TH1vs. Temperature

Figure 18: V_TH2vs. Temperature

3

2

1

1.20

RMOT=100k

RMOT=50k

RMOT=24k

1.18

1.16

1.14

1.12

1.10

0

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

Temperature

100 °C

150 °C

Temperature

Figure 19: V_TH3vs. Temperature

Figure 20: MOT Time vs. Temperature

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13.5

13.0

12.5

12.0

30 ns

25 ns

20 ns

15 ns

10 ns

5 ns

Tr

Tf

0 ns

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

100 °C

150 °C

Temperature

Figure 22: Tr and Tf vs. Temperature

Figure 21: Blanking Time vs. Temperature

75 ns

70 ns

65 ns

60 ns

55 ns

50 ns

45 ns

14

12

10

8

6

Rup

Rdown

4

Turn-on Propagation Delay

40 ns

2

Turn-off Propagation Delay

35 ns

0

-50 °C

0 °C

50 °C

100 °C

150 °C

-50 °C

0 °C

50 °C

Temperature

100 °C

150 °C

Temperature

Figure 24: R_UPand R_DOWNvs. Temperature

Figure 23: T_DONand T_DOFFvs. Temperature

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Package Details: 5 Lead SOT23

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Tape and Reel Details: 5 Lead SOT23

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Tape and Reel Details: 5 Lead SOT23

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Part Marking Information: 5 Lead SOT23

Top Marking

YW LC

Lot Code

Date Code

Bottom Marking

G

IR Logo

Part no.

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Qualification Information^†

Industrial^††

Comments: This family of ICs has passed JEDEC’s

Industrial qualification. IR’s Consumer qualification level is

granted by extension of the higher Industrial level.

Qualification Level

MSL3^†††

SOT-23 5L

Moisture Sensitivity Level

(per IPC/JEDEC J-STD-020)

Class A

Machine Model

Human Body Model

(per JEDEC standard JESD22-A115)

ESD

Class 1A

(per EIA/JEDEC standard EIA/JESD22-A114)

Class I, Level A

(per JESD78)

Yes

IC Latch-Up Test

RoHS Compliant

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information.

††† Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no

responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement

of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or

otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to

change without notice. This document supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

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型号：	IR1161LPBF_15
厂家：	Infineon
描述：	Secondary side synchronous rectification controller
文件：	总25页 (文件大小：991K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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