IR22381Q_技术文档

Data Sheet PD60232 revC

IR22381QPBF/IR21381Q(PbF)

3-PHASE AC MOTOR CONTROLLER IC

Features

Product Summary

•

Floating channel up to +600V or +1200V

V_OFFSET(max)

600V or 1200V

220mA / 460mA

12.5V-20V

“soft” over-current shutdown turns off desaturated output

Integrated desaturation circuit

I_{O +/-}(min.)

V_OUT

Active biasing on sensing desaturation input

Two stage turn on output for di/dt control

Integrated brake IGBT driver with protection

Voltage feedback sensing function

Separate pull-up/pull-down output drive pins

Matched delay outputs

Under voltage lockout with hysteresis band

Programmable deadtime

Hard shutdown function

Brake (I_{O +/-}min.)

Deadtime Asymmetry

Skew (max.)

40mA/80mA

125nsec

1µsec

Deadtime (typ. with

RDT=39KΩ)

DESAT Blanking time (typ.)

4.5µsec

3.0µsec

DESAT filter time (typ.)

Active bias on Desat input

DSH, DSL input voltage

threshold (typ.)

90Ω

8.0V

Description

The IR22381Q and IR21381Q are high voltage, 3-phase IGBT

driver best suited for AC motor drive applications. Integrated

desaturation logic provides all mode of overcurrent protection,

including ground fault protection. The sensing desaturation input is

provided by active bias stage to reject noise. Soft shutdown is

predominantly initiated in the event of overcurrent followed by turn-

off of all six outputs. A shutdown input is provided for a customized

shutdown function. The DT pin allows external resistor to program

the deadtime. Output drivers have separate turn on/off pins with

two stage turn-on output to achieve the desired di/dt switching level

of IGBT. Voltage feedback provides accurate volt x second

measurement.

Soft shutdown duration

time (typ.)

Voltage feedback matching

delay time (max.)

6.0µsec

400nsec

Package

64-Lead MQFP w/o 13 leads

Typical Connection

15V

VCC

VB1,2,3

DSH1,2,3

3

LIN1,2,3

3

HIN1,2,3

HOP1,2,3

HOQ1,2,3

FAULT

BRIN

SD

HON1,2,3

U

V

VFH1,2,3

VFL1,2,3

W

VS1,2,3

DSB

DSL1,2,3

LOP1,2,3

BR

(Refer to Lead

LOQ1,2,3

LON1,2,3

DT

Assignments for

correct pin

VSS

COM

configuration. This

diagram shows

electrical

connections only)

1

IR22381QPBF/IR21381Q(PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to V_SS, all currents are defined positive into any lead. The thermal

resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol

V_S

Definition

High side offset voltage

High side floating supply voltage

Min.

Max.

Units

V_{B 1,2,3}- 25

V_{B 1,2,3}+ 0.3

1225

(IR22381)

(IR21381)

-0.3

V_S1,2,3- 0.3

-0.3

V_CC- 25

V_COM-0.3

-0.3

V_B

625

High side floating output voltage (HOP, HON, HOQ)

Low side and logic fixed supply voltage

Power ground

Low side output voltage (LOP, LON, LOQ)

Logic input voltage (HIN/N, LIN, BRIN/N, SD)

V_HO

V_CC

COM

V_LO

V_{B 1,2,3}+ 0.3

25

V_CC+ 0.3

V

V_IN

V_CC+ 0.3 or V_SS+15

Which ever is lower

FAULT/N output voltage

Feedback output voltage

High side desat/feedback input voltage

Low side desat/feedback input voltage

Brake output voltage

Allowable offset voltage slew rate

Package power dissipation @ TA ≤ +25°C

Thermal resistance, junction to ambient

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

V_FLT

V_F

V_DSH

V_DSL

V_BR

dVs/dt

P_D

R_thJA

T_J

T_S

-0.3

V_{B 1,2,3}- 25

V_CC- 25

V_COM-0.3

—

V_CC+ 0.3

V_{B 1,2,3}+ 0.3

V_CC+ 0.3

50

V/ns

W

°C/W

—

2.0

—

60

—

125

°C

-55

150

T_L

—

300

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions. All voltage parameters are

absolute voltages referenced to V_SS. The V_Soffset rating is tested with all supplies biased at 15V differential.

Symbol

Definition

Min.

Max.

Units

High side floating supply voltage (Note 1)

High side floating supply offset voltage

V_S1,2,3+ 20

V_{B 1,2,3}

V_S1,2,3

V_S1,2,3+12.5

Note 2

V_S1,2,3

V_COM

0

(IR21381)

(IR22381)

600

1200

V_S1,2,3+ VB

V_CC

High side (HOP/HOQ/HON) output voltage

Low side (LOP/LOQ/LON) output voltage

Logic input voltage (HIN/N, LIN, BRIN/N SD)

Low side supply voltage (Note 1)

Power ground

FAULT/N output voltage

Feedback output voltage

V_{HO 1,2,3}

V_LO1,2,3

V_IN

V_SS+ 5

V

V_CC

12.5

20

COM

V_FLT

V_F

- 5

0

+ 5

V_CC

High side desat/feedback input voltage

Low side desat/feedback input voltage

BR output voltage

V_DSH

V_DSL

V_BR

V_{B 1,2,}₃- 20

V_CC- 20

V_COM

-40

V_{B 1,2,3}

V_CC

115

Ambient temperature

T_A

°C

Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV

thresholds are not reached.

Note 2: Logic operational for V_Sfrom V_SS-5V to V_SS+600V (IR21381) or 1200V (IR22381). Logic state held for V_Sfrom V_SS-5V to V_SS

-

V_BS. (Please refer to the Design Tip DT97-3 for more details).

2

IR22381QPBF/IR21381Q(PbF)

Static Electrical Characteristics

V_BIAS(V_CC,V_BS1,2,3) = 15V and T_A= 25 °C unless otherwise specified.

I/O diagrams don’t show ESD protection circuits.

Pin: V_CC, V_SS, V_B, V_S

Symbol

Definition

Min Typ Max Units

10.3 11.2 12.5

Test

Conditions

V_CCUV+

V_CCUV-

V_CCUVH

V_BSUV+

V_BSUV-

V_BSUVH

V_cc1supply undervoltage positive going threshold

V_cc1supply undervoltage negative going threshold 9.5 10.2 11.3

V_cc1supply undervoltage lockout hysteresis

V_BSsupply undervoltage positive going threshold

V_BSsupply undervoltage negative going threshold

V_BSsupply undervoltage lockout hysteresis

(IR21381Q)

Offset supply leakage current

(IR22381Q)

-

1.0

-

V

10.3 11.2 11.9

9.5 10.2 10.9

-

1.0

-

50

V_B1,2,3=V_S1,2,3

600V

=

I_LK

-

50

V

_B1,2,3=V_S1,2,3

=

µA

1200V

I_QBS

I_QCC

Quiescent VBS supply current

Quiescent Vcc supply current

150 300

V_LIN=0V,V_HIN=5V,

DSH_1,2,3= V_S1,2,3

3

6

mA V_LIN=0V,V_HIN=5V

DT=1µsec

Comparator

V_CC/V_B

UV

V_CCUV/V_BSUV

V_SS/V_S

Figure 1: Undervoltage diagram

Pin: HIN/N, LIN, BRIN/N, SD

The V_IN, V_THand I_INparameters are referenced to V_SSand are applicable to all six channels (HOP/HOQ/ HON_1,2,3

and LOP/LOQ/LON_1,2,3).

Test

Symbol

Definition

Min Typ Max Units Conditions

V_IH

Logic "0" input voltage

2.0

-

(HIN/N, LIN, BRIN/N, SD)(OUT=LO)

Logic "1" input voltage

V_IL

V_t+

V_t-

-

0.8

(HIN/N, LIN, BRIN/N, SD)(OUT=HI)

Logic input positive going threshold

(HIN/N, LIN, BRIN/N, SD)

V

_CC= 12.5V to

V

1.2 1.6 2.0

0.8 1.2 1.6

20V

Logic input negative going threshold

(HIN/N, LIN, BRIN/N, SD)

Logic input hysteresis(HIN/N, LIN, BRIN/N, SD)

-

0.4

-

0

∆V_T

Logic "1" input bias current (HIN/N, BRIN/N)

I_IN+

-2

-

V_IN= 0V

V_IN= 5V

V_IN= 0V

Logic "1" input bias current (LIN, SD)

85 140

µA

I_IN-

Logic "0" input bias current (HIN/N, BRIN/N)

Logic "0" input bias current (LIN, SD)

-

85 140

-2

-

0

3

IR22381QPBF/IR21381Q(PbF)

Figure 2: HIN/N, LIN and BRIN/N diagram

Pin: FAULT/N, VFH, VFL

V_OLVFis referenced to V_ss

Symbol

Definition

Min Typ Max Units Test Conditions

V_OLVF

VFH or VFL low level output voltage

-

0.8

V

I_VF= 10mA

VFH or VFL output on resistance

FAULT/N low on resistance

R_ON,VF

-

60

-

Ω

R_ON,FLT

______

FAULT /

VFL/VFH

R_ON

Internal signal

V_SS

Figure 3: FAULT/N, VFH, VFL diagram

Pin: DSL, DSH, DSB

V_DESATand I_DESATparameters are referenced to COM and V_S1,2,3

Symbol

Definition

Min Typ Max Units Test Conditions

V_DESAT+

High DSH_1,2,3and DSL_1,2,3and DSB

input threshold voltage

-

8.0

-

V

VDESAT-

Low DSH_1,2,3and DSL_1,2,3or DSB

input threshold voltage

-

7.0

-

DS input voltage hysteresis

V_DSTH

I_DS+

I_DS-

I_DSBR-

I_DSB

-

1.0

15

-150

-250

-11.1

-

High DSH, DSL, DSB input bias current

Low DSH, DSL input bias current

Low DSB input bias current

V_DESAT= 15V

V_DESAT= 0V

µA

DSH or DSL input bias current

mA

V_DESAT

=

(V_CCor V_BS) – 1V

Figure 4: DSH, DSL and DSB diagram

4

IR22381QPBF/IR21381Q(PbF)

Pin: HOP, LOP, HOQ, LOQ

The V_Oand I_Oparameters are referenced to COM and VS_1,2,3and are applicable to the respective output leads:

HO_1,2,3and LO_1,2,3

.

Symbol

Definition

Min Typ Max Units Test Conditions

V_OH

High level output voltage, VBIAS – VO (normal

switching). HOP=HOQ, LOP=LOQ.

-

2

V

I_O= -20mA

-

350

V

_O=0V, V_IN=1

(Note 1) PW≤t_on1

I_O1+

Output high first stage short circuit pulsed current.

HOP=HOQ, LOP=LOQ

200

Figure 16

mA

I_O2+

Output high second stage short circuit pulsed current. 100 200

-

V_O=0V, V_IN=1

(Note 1)

HOP=HOQ, LOP=LOQ

PW≤10µs

Note 1: for HOx Æ HINx/N = 0V, for LOx Æ LIN = 5V

Figure 5: HOP/HOQ and LOP/LOQ diagram

Pin: HON, LON, SSDH, SSDL

The V_Oand I_Oparameters are referenced to COM and VS_1,2,3and are applicable to the respective output leads:

HO_1,2,3and LO_1,2,3

.

Symbol

Definition

Min Typ Max Units Test Conditions

V_OL

Low level output voltage, VO (normal switching)

HON, LON

-

2

V

I_O= 20mA

Soft shutdown on resistance (see Note 2)

Output low short circuit pulsed current

Ω

R_ON,SS

I_O-

-

500

-

PW ≤ t_SS

250 540

mA V_O=15V, V_IN=0

(Note 3)

PW≤10µs

Note 2: SSD operation only

Note 3: for HOx Æ HINx/N = 5V, for LOx Æ LIN = 0V

Figure 6: HON, LON diagram

5

IR22381QPBF/IR21381Q(PbF)

Pin: BR

The V_Oand I_Oparameters are referenced to COM and are applicable to BR output .

Symbol

V_OHB

Definition

BR high level output voltage, V_CC- V_BR

Min Typ Max Units Test Conditions

-

6

3

-

I

_BR= -20mA

V

V_OLB

I_OBR+

BR low level output voltage, V_BR

-

I

_BR= 20mA

BR output high short circuit pulsed current

40 70

80 125

V_BR=15V, V_BRIN/N=0V

PW≤10µs

mA

I_OBR-

BR output low short circuit pulsed current

-

V_BR=0V, V_BRIN/N=5V

PW≤10µs

AC Electrical Characteristics

V_BIAS(V_CC,V_BS) = 15V, VS_1,2,3=V_SS, T_A= 25 °C and CL= 1000pF unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

Propagation Delay Characteristics

t_on1

Turn-on first stage duration time

—

200

—

VIN = 0 & 5V

RL(HOQ/LOQ)=10Ω

VIN = 0 & 5V

t_on

t_off

t_r

Turn-on propagation delay

Turn-off propagation delay

Turn-on rise time

Turn-off fall time

DSH to HO soft shutdown propagation delay at

HO turn-on

250 550 750

—

VS_1,2,3= 0 to 600 or

1200V

80

25

—

HOP=HON,LOP=LON

Figure 7

t_f

—

t_DESAT1

— 4500

— 3000

^VD^VF^E^Hi^Sg^I^A^Nu^Tr⁼e⁼⁰1¹^V1⁵^,^V,

t_DESAT2

DSH to HO soft shutdown propagation delay

after blanking

—

t_DESAT3

t_DESAT4

t_DESAT5

DSL to LO soft shutdown propagation delay at

LO turn-on

— 4500

— 3000

— 3300

—

VLIN = 5V

^VDF^Ei^Sg^Au^Tre⁼1¹1^5V,

DSL to LO soft shutdown propagation delay

after blanking

DSB to HO hard shutdown propagation delay

DSB to LO hard shutdown propagation delay

DSB to BR hard shutdown propagation delay

^VD^VF^E^Hi^Sg^I^A^Nu^Tr⁼e⁼⁰1¹^V1⁵^,^V,

VLIN = 5V

ns

t_DESAT6

— 3300

— 3000

—

^VDF^Ei^Sg^Au^Tre⁼1¹1^5V,

VBRIN = 0V

t_DESAT7

VDSB = 15V,

Figure 11

t_VFHL1,2,3

t_VFHHL1,2,3

t_VFLH1,2,3

t_VFLL1,2,3

t_PWVF

VFH high to low propagation delay

VFH low to high propagation delay

VFL low to high propagation delay

VFL high to low propagation delay

Minimum pulse width of VFH and VFL

—

550

400

—

VDESAT = 15V to 0V

Figure 12

VDESAT = 0V to 15V

Figure 12

VDESAT = 0V to 15V

Figure 12

VDESAT = 15V to 0V

Figure 12

^VDEo^Sr^A0^TV⁼t¹o⁵1^V5^tV^{o 0V}

Figure 12

6

IR22381QPBF/IR21381Q(PbF)

AC Electrical Characteristics cont.

V_BIAS(V_CC,V_BS) = 15V, V_S1,2,₃=V_SS, T_A= 25 °C and C_L= 1000pF unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

Propagation Delay Characteristics cont.

t_DS

Soft shutdown minimum pulse width of desat

— 3000

—

CL=1000pF,

V_DS=15V Figure 8-9

VHIN = 0V,

t_SS

t_FLT,DESAT1

t_FLT,DESAT2

Soft shutdown duration period

DSH to FAULT propagation delay at HO turn-on

— 6000

— 4800

— 3300

—

VDS=15V, Figure 11

DSH to FAULT propagation delay after

V_LIN= 5V,

blanking

ns

V_DS=15V, Figure 11

t_FLT,DESAT3

t_FLT,DESAT4

DSL to FAULT propagation delay at LO turn-on

— 4500

— 3000

—

DSL to FAULT propagation delay after

blanking

t_FLTDSB

DSB to FAULT propagation delay

— 3000

—

V_BRIN/N= 0V

V_DESAT= 15V,

Figure 11

t_FLTCLR

t_fault

LIN1=LIN2=LIN3=0 to FAULT

Minimum FAULT duration period

V_DESAT=15V,

Figure 11

9.0

—

µs

9.0 15.0 21.0

V_DESAT=15V,

Figure 15

FLTCLR pending

V_IN= on

t_BL

DS blanking time at turn on

— 4500

—

V_DESAT=15V,

Figure 11

t_SD

t_EN

SD to output shutdown propagation delay

SD disable propagation delay

—

600 900

V_IN= on

V

_DESAT=0V, Figure 14

V_IN= on

ns

V_DESAT=0V, Figure 14

t_onBR

t_offBR

t_rBR

BR output turn-on propagation

BR output turn-off propagation

BR output turn-on rise time

BR output turn-off fall time

—

110 200

125 200

235 400

130 250

Figure 7

t_fBR

Dead-time/Delay Matching Characteristics

DT

Deadtime

800 1000 1200

76 100 124

4500 5000 5500

Figure 12, External

resistor=39kΩ

Figure 12,External

resistor=0kΩ

Figure 12, External

resistor=220kΩ

Deadtime asymmetry skew, any of

DTL_off1,2,3-DTH_off1,2,3

PWM propagation delay matching max {ton/toff}

-min {ton/toff}, (ton/toff are applicable to all six

channels)

—

125

DT=1000ns

Figure 12

MDT

PM

ns

DT=1000ns

Figure 12

Voltage feedback delay matching, I any of

—

400

Input pulse width

>400nsec, Figure 13

VM

t

_VFHL1,2,3, t_VFHHL1,2,3, t_VFLL1,2,3, t_VFLH1,2,3

- any of t_VFHL1,2,3, t_VFHHL1,2,3, t_VFLL1,2,3, t_VFLH1,2,3

7

IR22381QPBF/IR21381Q(PbF)

Figure 7: Switching Time Waveforms

Figure 8: Low Side Desat Soft Shutdown Timing Waveform

8

IR22381QPBF/IR21381Q(PbF)

Figure 9: High Side Desat Soft Shutdown Timing Waveform

Figure 10: Brake Desat Timing Waveform

9

IR22381QPBF/IR21381Q(PbF)

Figure 11: Desat Timing Diagram

10

IR22381QPBF/IR21381Q(PbF)

HIN

LIN

DTL_off

DTH_off

HO

(HOP=HOQ=HON)

90%

50%

10%

DT

90%

50%

10%

LO

(LOP=LOQ=LON)

Figure 12: Internal Dead-Time Timing

V_B1,2,3

V_DESAT+

V_DESAT-

DSH_1,2,3

V_S1,2,3

V_B1,2,3

DSL_1,2,3

V_DESAT+

V_DESAT-

V_S1,2,3

t_VFHL1,2,3

t_VFHH1,2,3

V_CC

90%

VFH_1,2,3

10%

V_SS

t_VFLH1,2,3

t_VFLL1,2,3

V_CC

90%

10%

VFL_1,2,3

V_SS

Figure 13: Voltage Feedback Timing

11

IR22381QPBF/IR21381Q(PbF)

Figure 14: Shutdown Timing

Figure 15: Fault Duration with Pending Faultclear Waveform

(See paragraph 1.4.5 on page 21)

Figure 16: Output source current

12

IR22381QPBF/IR21381Q(PbF)

Lead Assignments

Figure 17: Package pin out

Lead Definitions

Symbol

Description

V_CC

V_SS

Low side supply voltage

Logic Ground

HIN_1,2,3/N Logic inputs for high side gate driver outputs (HOP_1,2,3/HOQ_1,2,3/HON_1,2,3

LIN_1,2,3

Logic input for low side gate driver outputs (LOP_1,2,3/LOQ_1,2,3/LON_1,2,3

FAULT/N Fault output (latched and open drain)

)

SD

Shutdown input

DT

Programmable deadtime resistor pin

Brake IGBT desaturation protection input

DSB

BRIN/N Logic input for brake driver

13

IR22381QPBF/IR21381Q(PbF)

Lead Definitions continued

Symbol

Description

BR

Brake driver output

COM

VB_1,2,3

Brake and Low side drivers return

High side gate driver floating supply

HOP_1,2,3High side driver sourcing output

HOQ_1,2,3High side driver boost sourcing output

HON_1,2,3High side driver sinking output

IGBT desaturation protection input and high side voltage feedback input

(see par. 1.4.3 on page 19)

DSH_1,2,3

VS_1,2,3

High voltage floating supply return

LOP_1,2,3Low side driver sourcing output

LOQ_1,2,3Low side driver boost sourcing output

LON_1,2,3Low side driver sinking output

IGBT desaturation protection input and low side voltage feedback input

(see par. 1.4.3 on page 19)

DSL_1,2,3

VFH_1,2,3High side voltage feedback logic output

VFL_1,2,3Low side voltage feedback logic output

14

IR22381QPBF/IR21381Q(PbF)

Functional block diagram

VB1

HOQ1

LATCH

HOP1

HIN1

SHUTDOWN

VFB

SCHMITT

TRIGGER

INPUT &

SHOOT

THROUGH

PREVENTION

LOCAL DESAT

PROTECTION

SOFT

SHUTDOWN

VOLTAGE

di/dt control

HIN1

100nsec

minimum

Deadtime

DRIVER

LEVEL

SHIFTERS

HON1

LIN1

VS1

FEEDBACK

DSH1

UV DETECT

VFH1

VB2

HOQ2

HOP2

LATCH

HIN2

SCHMITT

TRIGGER

INPUT &

SHOOT

THROUGH

PREVENTION

LOCAL DESAT

PROTECTION

SOFT

SHUTDOWN

VOLTAGE

di/dt control

HIN2

LIN2

100nsec

minimum

Deadtime

DRIVER

SHUTDOWN

HON2

LEVEL

SHIFTERS

VS2

VFB

FEEDBACK

DSH2

UV DETECT

VFH2

VB3

HOQ3

HOP3

HON3

LATCH

HIN3

SHUTDOWN

VFB

di/dt control

SCHMITT

TRIGGER

INPUT &

SHOOT

THROUGH

PREVENTION

LOCAL DESAT

PROTECTION

SOFT

SHUTDOWN

VOLTAGE

HIN3

LIN3

100nsec

minimum

Deadtime

DRIVER

LEVEL

SHIFTERS

VS3

FEEDBACK

DSH3

UV DETECT

VFH3

SD

DT

SOFT

SHUTDOWN

LOCAL DESAT

PROTECTION

LOQ1

LOP1

LIN1

di/dt control

SOFT

SHUTDOWN

DRIVER

LON1

DSL1

VFL1

VFL2

VFL3

VOLTAGE

FEEDBACK

LOCAL DESAT

PROTECTION

LOP2

LIN2

di/dt control

SOFT

SHUTDOWN

FAULT

LOGIC

CLEAR

LOGIC

DRIVER

LON2

DSL2

VOLTAGE

FEEDBACK

FAULT

VCC

LOQ3

LOP3

LON3

LOCAL DESAT

PROTECTION

LIN3

di/dt control

SOFT

SHUTDOWN

DRIVER

UV

DETECT

VOLTAGE

FEEDBACK

To Low Side Logic

DSL3

BRIN

VSS

BRAKE

DRIVER

BR

SHUTDOWN

DESAT

DETECTION

DSB

COM

15

IR22381QPBF/IR21381Q(PbF)

State diagram

Stable States

Temporary States

System Variables

−

FAULT CLEAR indicates:

LIN1=LIN2=LIN3=0

HIN/N /LIN/BRIN/N

UV_VCC

UV_VBS

DSH/L, DSB

−

FAULT

−

SOFT SHUTDOWN

Normal operation

UNDERVOLTAGE V_CC

SHUTDOWN (SD)

UNDERVOLTAGE V_BS

−

SD

NOTE 1: a change of logic value of the signal labeled on lines (system variable) generates a state transition.

NOTE 2: Exiting from UNDERVOLTAGE V_BSstate, the HO goes high only if a falling edge event happens in

HIN/N.

16

IR22381QPBF/IR21381Q(PbF)

Logic Table

Output drivers status description

HO/LO/BR

HOP/LOP HOQ/LOQ HON/LON

BR

status

0

1

HiZ

1

HiZ

0

1

1 (after t_on1

)

HiZ

SSD pull-

down

SSD

HiZ

N/A

Output follows inputs

LO/HO/BR

Under

Voltage

Driver

OUTPUTS

INPUTS

OUTPUT

Operation

HIN/N

LIN

0

BRIN/N

SD

0

FAULT/N

VCC

VBS

HO

LO BR

0

1

No

1

0

1

0

BR

Normal

Operation

1

0

Anti Shoot

Through

0

1

X

BRIN/N

X

0

1

0

X

1

No

X

No

X

0

BR

0

Shut Down

X

LIN

X

No

Yes

No

Yes

X

0

LO

0

Under

Voltage

(NOTE1)

X

0

Soft SD

(after DSL/H)

X

BRIN/N

No

SSD

SSD BR

Hard SD

(after DSB)

X

0

No

0

X

FAULT

(NOTE2)

LIN1=

LIN2=

Fault Clear

X ÆHIN/N

BRIN/N

X

(after t_FLTCLR

)

No

0 Æ HO

0

BR

LIN3= 0

NOTE1: Unless in Anti Shoot Through condition.

NOTE2: FAULT duration is at least t_faultwhen LIN1=LIN2=LIN3=0. Device stays in FAULT condition in all other

cases.

17

IR22381QPBF/IR21381Q(PbF)

Timing and logic state diagrams description

The following picture (Figure 18) shows the input/output logic diagram.

Figure 18: I/O timing diagram

Referred to timing diagram of Figure 18:

A. When the input signals are on together

the outputs go off (anti-shoot through).

B. The HO signal is on and the high side

IGBT desaturates, the HO turn off softly.

FAULT goes low. While in SSD, if LIN

goes up, LO does not change (freeze).

C. When FAULT is latched low (see FAULT

section) it can be disabled by

LIN1=LIN2=LIN3=0 condition.

E. The LO signal is on and the low side

IGBT desaturates, the low side behaviour

is the same as described in point B.

F. As C.

G. As D.

H. As A.

I. The BR signal is on and the brake IGBT

desaturates. The driver goes in FAULT

condition tuning off all the IGBTs (Hard

shut down).

D. SD disable HO and LO outputs.

18

IR22381QPBF/IR21381Q(PbF)

forcing FAULT pin low (see FAULT section and

Figure 20). This event disables both low side and

floating drivers and the diagnostic signal holds until

the under voltage condition is over. Fault condition

is not latched and the FAULT pin is released once

1

FEATURES DESCRIPTION

1.1 Start-up sequence

Device starts in FAULT condition at power-up

unless FAULT clear condition is forced (i.e.

LIN1=LIN2=LIN3=0 for at least t_FLTCLR– in this

case FAULT is asserted for t_fltclr, then resets).

In FAULT condition driver outputs are insensitive

to inputs: any noise on input pins is then rejected

during system power-up.

As soon as the controller awakes, a FAULT clear

action can be taken to enter the normal operating

condition.

V_CCbecomes higher than UV_VCC+.

The undervoltage on the V_BSworks disabling only

the floating driver. Undervoltage on V_BSdoes not

prevent the low side driver to activate its output nor

generate diagnostic signals. V_BSundervoltage

condition (V_BS< UV_VBS-) latches the high side

output stage in the low state. V_BSmust be

reestablished higher than UV_VBS+to return in

normal operating mode. To turn on the floating

driver H_INmust be re-asserted high (rising edge

event on H_INis required).

1.2 Normal operation mode

After clearing FAULT condition and supplies are

stable the device becomes fully operative (see

grey blocks in the State Diagram).

HIN/N_1,2,3, LIN_1,2,3and BRIN/N produce driver

outputs to switch accordingly, while the input logic

checks the input signals preventing shoot-through

events and including Dead-time (DT).

1.4.2

4.2 Power devices desaturation

Different causes can generate a power inverter

failure: phase and/or rail supply short-circuit,

overload conditions induced by the load, etc… In

all these fault conditions a large current increase is

produced in the IGBT.

The IR22381/IR21381 fault detection circuit

monitors the IGBT emitter to collector voltage (V_CE)

by means of an external high voltage diode. High

current in the IGBT may cause the transistor to

desaturate, i.e. V_CEto increase.

Once in desaturation, the current in power

transistor can be as high as 10 times the nominal

current. Whenever the transistor is switched off,

this high current generates relevant voltage

transients in the power stage that need to be

smoothed out in order to avoid destruction (by

over-voltages). The IR22381/IR21381 gate driver

accomplish the transients control by smoothly

turning off the desaturated transistor by means of

the LON pin activating a so called Soft ShutDown

sequence (SSD).

1.3 Shut down

The system controller can asynchronously

command the Shutdown through the 3.3 V

compatible CMOS I/O SD pin. This event is not

latched.

1.4 Fault management

IR22381 is able to manage both the supply failure

(undervoltage lockout on both low and high side

circuits) and the desaturation of power transistors

connected to its drivers outputs.

1.4.1

Undervoltage (UV)

The Undervoltage protection function disables the

output stage of each driver preventing the power

device being driven with too low voltages.

1.4.3

Desaturation detection: DSH/L and

DSB pin function

Both the low side (V_CCsupplied) and the floating

side (V_BSsupplied) are controlled by a dedicate

undervoltage function.

Undervoltage event on the V_CC(when

V_CC< UV_VCC-) generates a diagnostic signal by

Figure 19 shows the structure of the desaturation

sensing and soft shutdown block. This

configuration is the same for both high and low

side output stages.

19

IR22381QPBF/IR21381Q(PbF)

Figure 19: high and low side output stage for channels 1, 2, 3

VB1

UV detect

Latch

HOQ1

HOP1

____

HIN1

di/dt control

DRIVER

Schmitt trigger

input

100ns

minimum

deadtime

Input

latch

Level

Shifters

Shutdown

Local DESAT

protection

&

HON1

shoot through

prevention

Soft ShutDown

LIN1

VS1

VFH1

Voltage feedback

DSH1

HOLD

latch

oneshot

Clear

logic

LIN2

LIN3

LIN1

_____

FAULT

R

Desat H2

Desat H3

LOQ1

LOP1

LON1

Fault

duration

LIN1

S

Q

Desat L2

Desat L3

di/dt control

DRIVER

Local DESAT

protection

(t_fault)

VSS

VCC

Desat L1

UV_VCC

Soft ShutDown

Soft Shutdown

VFL1

Voltage feedback

UV

detect

DSL1

BR

FAULT

logic

di/dt control

DRIVER

Hard Shutdown

DESAT protection

Shutdown

____

BRIN

COM

DSB

Figure 20: Fault management diagram

20

IR22381QPBF/IR21381Q(PbF)

The external sensing diode should have BV>600V

(or 1200V depending on application) and low stray

capacitance (in order to minimize noise coupling and

switching delays). The diode is biased by a

dedicated circuit for IGBT driver outputs (see the

active-bias section) and by a pull-up resistor for

Brake output. When V_CEincreases, the voltage at

DSH/L pin increases too. Being internally biased to

the local supply, DSH/L or DSB voltage is

automatically clamped. When DSH/L or DSB exceed

the V_DESAT+threshold the comparator triggers (see

Figure 19). Comparator output is filtered in order to

avoid false desaturation detection by externally

induced noise; pulses shorter than t_DSare filtered

out. To avoid detecting a false desaturation during

IGBT turn on, the desaturation circuit is disabled by a

Blanking signal (T_BL, see Blanking block in Figure

19). Blanking time is the estimated maximum IGBT

turn on time and must be not exceeded by proper

gate resistance sizing. When the IGBT is not

completely saturated after T_BL, desaturation is

detected and the driver will turn off.

It must be noted that while in Soft Shut Down, both

Under Voltage fault and external Shut Down (SD)

are masked until the end of SSD. Desaturation

protection is working independently by the other

control pins and it is disabled only when the output

status is off.

Brake IGBT

Brake desaturation causes a hard shutdown for all

the IGBTs.

Fault condition is asserted and hold until cleared by

controller.

1.4.5

Fault is cleared by forcing low simultaneously LIN1,

LIN2 and LIN3 for at least t_FLTCLR

Fault Clear

.

When LIN inputs are simultaneously low and a

desaturation event happens, FAULT is activated for

a minimum amount of time of t_fault

.

1.5 Active bias

For the purpose of sensing the power transistor

desaturation the collector voltage is read by an

external HV diode. The diode is normally biased by

an internal pull up resistor connected to the local

supply line (V_Bor V_CC). When the transistor is “on”

the diode is conducting and the amount of current

flowing in the circuit is determined by the internal pull

up resistor value.

In the high side circuit, the desaturation biasing

current may become relevant for dimensioning the

bootstrap capacitor (see Figure 23). In fact, too low

pull up resistor value may result in high current

discharging significantly the bootstrap capacitor. For

that reason typical pull up resistor are in the range of

100 kꢀ. This is the value of the internal pull up.

While the impedance of DSH/DSL pins is very low

when the transistor is on (low impedance path

through the external diode down to the power

transistor), the impedance is only controlled by the

pull up resistor when the transistor is off. In that case

relevant dV/dt applied by the power transistor during

1.4.4

SSD and Fault management

Output bridge

Desaturation event implies a large amount of current.

For that reason, IR22381 turn off strategy is based

on soft shutdown.

Eligible desaturation signals coming from DSH/L

inputs initiate the Soft Shutdown sequence (SSD).

While in SSD, the SSD pull-down is activated (R_ON,SS

for t_ss– see Figure 19) to turn off the IGBT through

HON/LON.

Figure 20 shows the fault management circuit. In this

diagram Desat_H1,2,3 and Desat_L1,2,3 are the

internal signals triggered by the desaturation event.

IR22381 accomplishes output bridge turn off in the

following way:

-

if the desaturated IGBT is a low side, all the

low side IGBTs are softly turned off (SSD),

while the high side IGBTs are kept in the

state they were just before the desaturation

event.

If the desaturated IGBT is a high side, it is

soflty turned off simultaneously with all the

low side IGBTs. While the remaining HS

IGBTs are kept in the state they were just

before the desaturation event.

the commutation at the output results in

a

considerable current injected through the stray

capacitance of the diode into the desaturation

detection pin (DSH/L). This coupled noise may be

easily reduced using an active bias for the sensing

diode.

-

An Active Bias structure is available DSH/L pin. The

DSH/L pins present an active pull-up respectively to

VB/VCC, and a pull-down respectively to VS/COM.

The dedicated biasing circuit reduces the impedance

on the DSH/L pin when the voltage exceeds the

V_DESATthreshold (see Figure 21). This low

impedance helps in rejecting the noise providing the

current inject by the parasitic capacitance. When the

In any case, after the soft shutdown period (t_SS), all

IGBTs are hardly shut down (brake IGBT included).

Desaturation event generates a FAULT signal (see

Figure 11) that is latched until fault clear condition is

verified.

21

IR22381QPBF/IR21381Q(PbF)

power transistor is fully on, the sensing diode gets

forward biased and the voltage at the DSH/L pin

decreases. At this point the biasing circuit

deactivates, in order to reduce the bias current of the

diode as shown in Figure 21.

and one turn off stage for SSD operation (both

connected to HON/LON).

When the driver turns on the IGBT (see Figure 16), a

first stage is constantly activated (HOP/LOP) while

an additional stage is maintained active only for a

limited time (t_ON1, HOQ/LOQ). This feature boost the

total driving capability in order to accommodate both

fast gate charge to the plateau voltage and dV/dt

control in switching.

At turn off, a single n-channel sinks up to 460mA (I_O-)

and offers a low impedance path to prevent the self-

turn on due to the parasitic Miller capacitance in the

power switch.

1.7 Voltage FeedBack

Voltage feedback pins provide information about the

state of the corresponding IGBT by means of

sensing its collector.

Figure 21: R_DSH/LActive Biasing

The V_DESATthreshold discriminates whether the

sensed IGBT can be considered on (DSH/L <

V_DESAT) or off (DSH/L > V_DESAT).

1.6 Output stage

IGBT state information is then sent to VFH/L_1,2,3

open collector outputs, which are tied to Vss

ground.

The structure is shown in Figure 19 and consists of

two turn on stages (connected to HOP/LOP and

HOQ/LOQ), one turn off stage for normal operation

See Figure 22 for functional details.

Figure 22: Voltage feedback functional diagram

22

IR22381QPBF/IR21381Q(PbF)

Now we must consider the influencing factors

contributing V_BSto decrease:

2 Sizing tips

− IGBT turn on required Gate charge (Q_G);

− IGBT gate-source leakage current (I_{LK_GE});

− Floating section quiescent current (I_QBS);

− Floating section leakage current (I_LK)

− Bootstrap diode leakage current (I_{LK_DIODE});

2.1 Bootstrap supply

The V_BS1,2,3voltage provides the supply to the high

side drivers circuitry of the IR22381/IR21381. V_BS

supply sit on top of the V_Svoltage and so it must be

floating.

The bootstrap method to generate V_BSsupply can

be used with IR22381/IR21381 high side drivers.

The bootstrap supply is formed by a diode and a

capacitor connected as in Figure 23.

− Desat diode bias when on (I_DS-

)

− Charge required by the internal level shifters

(Q_LS); typical 20nC

− Bootstrap capacitor leakage current (I_{LK_CAP});

− High side on time (T_HON).

I_{LK_CAP}is only relevant when using an electrolytic

capacitor and can be ignored if other types of

capacitors are used. It is strongly recommend using

at least one low ESR ceramic capacitor (paralleling

electrolytic and low ESR ceramic may result in an

efficient solution).

Then we have:

Q_TOT= Q_G+ Q_LS+ (I_{LK _ GE}+ I_QBS

+

+ I_LK+ I_{LK _ DIODE}+ I_{LK _CAP}+ I_DS−)⋅T_HON

The minimum size of bootstrap capacitor is:

Figure 23: bootstrap supply schematic

Q_TOT

This method has the advantage of being simple and

low cost but may force some limitations on duty-

cycle and on-time since they are limited by the

requirement to refresh the charge in the bootstrap

capacitor.

C_{BOOT min}

=

∆V_BS

An example follows:

using a 15A @ 100°C IGBT (GB15XP120K):

Proper capacitor choice can reduce drastically

these limitations.

• I_QBS= 250 µA

• I_LK= 50 µA

• Q_LS= 20 nC;

• Q_G= 58 nC

• I_{LK_GE}= 250 nA

• I_{LK_DIODE}= 100 µA (with reverse recovery time <100 ns);

• I_{LK_CAP}= 0

(See Static Electrical Charact.);

Bootstrap capacitor sizing

To size the bootstrap capacitor, the first step is to

establish the minimum voltage drop (∆V_BS) that we

have to guarantee when the high side IGBT is on.

If V_GEminis the minimum gate emitter voltage we

want to maintain, the voltage drop must be:

(Q_ge+Q_gcDatasheet GB15XP120K);

(Datasheet GB15XP120K);

(neglected for ceramic capacitor);

(see Static Electrical Charact.);

• I_DS-= 150 µA

• T_HON= 100 µs.

∆V_BS≤V_CC−V_F−V_{GE min}−V_CEon

under the condition:

And:

•

V_CC= 18 V

V_F= 1 V

•

V

_CEonmax= 2.5 V

_GEmin= 11.9 V

V_{GE min}> V_{BSUV −}

the maximum voltage drop ∆V_BSbecomes

where V_CCis the IC voltage supply, V_Fis bootstrap

diode forward voltage, V_CEonis emitter-collector

voltage of low side IGBT and V_BSUV-is the high-side

supply undervoltage negative going threshold.

∆V_BS≤V_CC−V_F−V_GEmin−V_CEon

=

23

IR22381QPBF/IR21381Q(PbF)

constant. The minimum on time for charging the

bootstrap capacitor or for refreshing its charge must

be verified against this time-constant.

= 18V −1V −11.9V − 2.5V = 2.6V

And the bootstrap capacitor must be:

133 nC

2.6V

c. Bootstrap Capacitor

C_BOOT

≥

= 51 nF

For high T_HONdesigns where is used an electrolytic

tank capacitor, its ESR must be considered. This

parasitic resistance forms a voltage divider with

R_bootgenerating a voltage step on V_BSat the first

charge of bootstrap capacitor. The voltage step and

the related speed (dV_BS/dt) should be limited. As a

general rule, ESR should meet the following

constraint:

NOTICE: Here above V_CChas been chosen to

be 18V as an example. IGBTs can be supplied

with higher/lower supply accordingly to design

requirements. Vcc variations due to low voltage

power supply must be accounted in the above

formulas.

ESR

⋅V_CC≤ 3V

Some important considerations

a. Voltage ripple

ESR + R_BOOT

There are three different cases making the

bootstrap circuit get conductive (see Figure 23)

Parallel combination of small ceramic and large

electrolytic capacitors is normally the best

compromise, the first acting as fast charge thank for

the gate charge only and limiting the dV_BS/dt by

reducing the equivalent resistance while the second

keeps the V_BSvoltage drop inside the desired ∆V_BS.

I_LOAD< 0; the load current flows in the low side

IGBT displaying relevant V_CEon

V_BS= V_CC−V_F−V_CEon

d. Bootstrap Diode

The diode must have a BV> 600V (or 1200V

depending on application) and a fast recovery time

(trr < 100 ns) to minimize the amount of charge fed

back from the bootstrap capacitor to V_CCsupply.

In this case we have the lowest value for V_BS.

This represents the worst case for the bootstrap

capacitor sizing. When the IGBT is turned off the

Vs node is pushed up by the load current until the

high side freewheeling diode get forwarded

biased

2.2 Gate resistances

I_LOAD= 0; the IGBT is not loaded while being

on and V_CEcan be neglected

The switching speed of the output transistor can be

controlled by properly size the resistors controlling

the turn-on and turn-off gate current. The following

section provides some basic rules for sizing the

resistors to obtain the desired switching time and

speed by introducing the equivalent output

resistance of the gate driver (R_DRpand R_DRn).

V_BS= V_CC−V_F

I_LOAD> 0; the load current flows through the

freewheeling diode

The examples always use IGBT power transistor.

Figure 24 shows the nomenclature used in the

following paragraphs. In addition, V_geindicates the

plateau voltage, Q_gcand Q_geindicate the gate to

collector and gate to emitter charge respectively.

V_BS= V_CC−V_F+V_FP

*

In this case we have the highest value for V_BS.

Turning on the high side IGBT, I_LOADflows into it

and V_Sis pulled up.

To minimize the risk of undervoltage, bootstrap

capacitor should be sized according to the I_LOAD<0

case.

b. Bootstrap Resistor

A resistor (R_boot) is placed in series with bootstrap

diode (see Figure 23) so to limit the current when

the bootstrap capacitor is initially charged. We

suggest not exceeding some Ohms (typically 5,

maximum 10 Ohm) to avoid increasing the V_BStime-

24

IR22381QPBF/IR21381Q(PbF)

I_C

C_RES

R

_Gon= gate on-resistor

R_DRp= driver equivalent on-resistance

V_GE

IR22381Q/IR21381Q HOP/LOP and HOQ/LOQ

pins can be used to configure gate charge circuit.

Fast turn on can be configured using HOP and LOP

pins (up to t_ON1switching time).

t₁,Q_GE

V_CE

t₂,Q_GC

For slower turn on times HOQ and LOQ can be

used.

Current partitioning can be changed acting on the

output resistors.

dV/dt

I_C

90%

C_RESon

C_RES

V_GE

V_ge*

In particular, shorting HOP to HOQ and LOP to

LOQ, R_DRpis defined by

C_RESoff

10%

t,Q

⎧

⎛

⎞

⎟

⎠

⎛

⎞

t_on1Vcc Vcc t_SW

⎜

⎟

+

−1

when t_SW> t_on1

when t_SW≤ t_on1

⎪

⎨

⎜

t_SWI_o1+I_o2+t_on1

⎝

⎠

⎝

t_SW

R_DRp

=

Vcc

I_o1+

t_Don

t_R

⎪

Figure 24: Nomenclature

⎩

(I_O1+,I_O2+and t_on1from “static Electrical

Characteristics”).

2.2.1

Sizing the turn-on gate resistor

Table 1 reports the gate resistance size for two

commonly used IGBTs (calculation made using

typical datasheet values and assuming Vcc=15V).

- Switching-time

For the matters of the calculation included

hereafter, the switching time t_swis defined as the

time spent to reach the end of the plateau voltage

(a total Q_gc+Q_gehas been provided to the IGBT

gate). To obtain the desired switching time the gate

resistance can be sized starting from Q_geand Q_gc,

- Output voltage slope

Turn-on gate resistor R_Goncan be sized to control

output slope (dV_OUT/dt).

While the output voltage has

*

Vcc, V_ge(see Figure 25):

a

non-linear

behaviour, the maximum output slope can be

approximated by:

Q_gc+ Q_ge

I_avg

and

R_TOT

=

t_sw

I_avg

dV_out

dt

=

C_RESoff

Vcc −V_g^*_e

inserting the expression yielding I_avgand

rearranging:

=

I_avg

*

Vcc −V_ge

R_TOT

=

I_avg

C_RES

dV_out

dt

Vcc/Vb

C_RESoff

⋅

R_DRp

As an example, Table 2 shows the sizing of gate

resistance to get dV_out/dt=5V/ns when using two

popular IGBTs, typical datasheet values and

assuming Vcc=15V.

R_Gon

COM/Vs

NOTICE: Turn on time must be lower than T_BLto

avoid improper desaturation detection and SSD

triggering.

Figure 25: R_Gonsizing

where R_TOT= R_DRp+ R_Gon

25

IR22381QPBF/IR21381Q(PbF)

As a result, when τ is faster than the collector rise

time (to be verified after calculation) the transfer

function can be approximated by:

Sizing the turn-off gate resistor

The worst case in sizing the turn-off resistor R_Goffis

when the collector of the IGBT in off state is forced

to commutate by external events (i.e. the turn-on of

the companion IGBT).

V_ge

= s ⋅(R_Goff+ R_DRn)⋅C_RESoff

In this case the dV/dt of the output node induces a

parasitic current through C_RESoffflowing in R_Goffand

V_de

R

_DRn(see Figure 26).

dV_de

So that V_ge= (R_Goff+ R_DRn)⋅C_RESoff

⋅

in the

If the voltage drop at the gate exceeds the threshold

voltage of the IGBT, the device may self turn on

causing large oscillation and relevant cross

conduction.

dt

time domain.

Then the condition:

dV_out

dt

(

)

V_th>V_ge= R_Goff+ R_DRn⋅C_RESoff

dV/dt

must be verified to avoid spurious turn on.

HS Turning ON

C_RESoff

Rearranging the equation yields:

R_Goff

V_th

OFF

(1) R_Goff

<

− R_DRn

ON

dV

dt

R_DRn

C_IES

C_RESoff

⋅

In any case, the worst condition for a spurious turn

on is with very fast steps on IGBT collector.

In that case collector to gate transfer function can

be approximated with the capacitor divider:

Figure 26: R_Goffsizing: current path when Low

Side is off and High Side turns on

C_RESoff

The transfer function between IGBT collector and

IGBT gate then becomes:

V_ge=V_de⋅

(C_RESoff+ C_IES)

which is driven only by IGBT characteristics.

V_ge

s ⋅(R_Goff+ R_DRn)⋅C_RESoff

=

As an example, table 3 reports R_Goff(calculated with

the above mentioned equation (1)) for two popular

IGBTs to withstand dV_out/dt = 5V/ns.

V_de1+ s ⋅(R_Goff+ R_DRn)⋅(C_RESoff+ C_IES)

Which yields to a high pass filter with a pole at:

NOTICE: the above-described equations are

intended being an approximated way for the gate

resistances sizing. More accurate sizing may

account more precise device modelling and

parasitic component dependent on the PCB and

power section layout and related connections.

1

1/τ =

(R_Goff+ R_DRn) ⋅(C_RESoff+ C_IES)

Table 1: R_Gonsizing driven by t_swconstraint

IGBT

Qge

Qgc

Vge* tsw

Iavg

Rtot

Tsw

RGon → std commercial value

GB15XP120K*

GB05XP120K

IRGB5B120KD

12nC

46nC

9V

500ns 116mA

400ns 44mA

500ns 33mA

77Ω

Rtot - RDRp = 15 ꢀ → 10 ꢀ

Rtot - RDRp = 65 ꢀ → 68 ꢀ

Rtot - RDRp = 102 ꢀ → 100 ꢀ

→465ns

→408ns

→502ns

3.7nC 14nC

3.7nC 13nC

9.5V

124Ω

164Ω

Table 2: Table 2: RGon sizing driven by dVOUT/dt constraint

IGBT

Qge

Qgc

Vge* CRESoff Rtot

dVout/dt

→5V/ns

→5.1V/ns

→5V/ns

RGon → std commercial value

GB15XP120K*

GB05XP120K

IRGB120KD

12nC 46nC 9V

3.7nC 14nC 9.5V 12pF

3.7nc 13nC 9.5V 11pF

38pF

47Ω

91Ω

Rtot - RDRp = 4.5 ꢀ → 4.7ꢀ

Rtot - RDRp = 48.8 ꢀ → 47ꢀ

100Ω Rtot - RDRp = 57 ꢀ → 56 ꢀ

26

IR22381QPBF/IR21381Q(PbF)

Table 3: RGoff sizing

IGBT

Vth(min)

CRESoff RGoff

GB15XP120K*

GB05XP120K

IRG4PH20K(D)

5

38pF

12pF

11pF

RGoff = 0 ꢀ

RGoff ≤ 55 ꢀ

RGoff ≤ 63 ꢀ

* sized with 18V supply

3 PCB LAYOUT TIPS

3.1 Distance from H to L voltage

The IR22381/IR21381Q pin out lacks some pins

(see Figure 17) maximizing the distance between

floating (from DC- to DC+) and low voltage pins . It’s

strongly recommended to place components tied to

floating voltage in the respective high voltage

portions of the device (VB_1,2,3, VS_1,2,3) side.

Figure 27: gate drive loop

3.2 Ground plane

Ground plane must not be placed under or nearby

the high voltage floating side to minimize noise

coupling.

3.4 Supply capacitors

IR22381 output stages are able to quickly turn on

IGBT with up to 460mA of output current. The

supply capacitors must be placed as close as

possible to the device pins (V_CCand V_SSfor the

ground tied supply, V_Band V_Sfor the floating

3.3 Gate drive loops

Current loops behave like an antenna able to

receive and transmit EM noise. In order to reduce

EM coupling and improve the power switch turn

on/off performances, gate drive loops must be

reduced as much as possible. Figure 23 shows the

high and low side gate loops.

Moreover, current can be injected inside the gate

drive loop via the IGBT collector-to-gate parasitic

capacitance. The parasitic auto-inductance of the

gate loop contributes to develop a voltage across

the gate-emitter increasing the possibility of self

turn-on effect. For this reason is strongly

recommended to place the three gate resistances

close together and to minimize the loop area (see

Figure 27).

supply)

in

order

to

minimize

parasitic

inductance/resistance.

3.5 Routing and placement

example

Figure 28 shows one of the possible layout

solutions using a 3 layer PCB (low voltage signals

not shown) on an ECONO PIM module. This

example takes into account all the previous

considerations. Placement and routing for supply

capacitors and gate resistances in the high and low

voltage side minimize respectively supply path and

gate drive loop. The bootstrap diode is placed under

the device to have the cathode as close as possible

to bootstrap capacitor and the anode far from high

voltage and close to V_CC.

27

IR22381QPBF/IR21381Q(PbF)

a) TOP(Gate Drive)

b) BOTTOM (GND)

28

IR22381QPBF/IR21381Q(PbF)

c) MID (VCC/COM/DCP)

Figure 28: layout example: top (a), internal layer (b) and bottom (c) layer

29

IR22381QPBF/IR21381Q(PbF)

Case Outline

Qualification Level: Industrial level, MSL3, Lead-free.

ESD Classification:

Human Body Model (HBM): Class 2, per JESD22-A114-B

Machine Model (MM): Class B, per EIA/JESD22-A115-A

WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105

This product has been qualified for the industrial market.

Data and specifications are subject to change without notice. 08/11/05.

30


型号：	IR22381Q
厂家：	Infineon
描述：	AC Motor Controller, PQFP64, LEAD FREE, MS-022, MQFP-64
文件：	总30页 (文件大小：1096K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR22381Q [INFINEON]

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