IR22771SPBF [INFINEON]
Phase Current Sensor IC for AC motor control; 相电流传感器IC用于交流电机控制
| 型号： | IR22771SPBF |
| 厂家： | 
Infineon |
| 描述： | Phase Current Sensor IC for AC motor control |
| 文件： | 总16页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60234 revB
IR22771S/IR21771S(PbF)
Phase Current Sensor IC for AC motor control
Features
Product Summary
VOFFSET (max)
IR22771 1200 V
IR21771 600V
±250mV
• Floating channel up to 600V for IR21771 and 1200V for
IR22771
Vin range
• Synchronous sampling measurement system
• High PWM noise (ripple) rejection capability
• Digital PWM output
• Fast Over Current detection
• Suitable for bootstrap power supplies
• Low sensing latency (<7.5 µsec @20kHz)
Bootstrap supply range
8-20 V
2.2 mA
Floating channel quiescent
current (max)
Sensing latency (max)
7.5 µsec
(@20kHz)
40ksample/sec
(@20kHz)
±470 mV
Throughput
Over Current threshold (max)
Description
IR21771/IR22771 is a high voltage, high speed, single phase
current sensor interface for AC motor drive applications. The
current is sensed by an external shunt resistor. The IC converts the
analog voltage into a time interval through a precise circuit that also
performs a very good ripple rejection showing small group delay.
The time interval is level shifted and given to the output. The max
throughput is 40 ksample/sec suitable for up to 20 kHz
asymmetrical PWM modulation and max delay is <7.5µsec
(@20kHz). Also a fast over current signal is provided for IGBT
protection.
Package
Typical Connection
(Please refer to
Lead Assignments
for correct pin
configuration. This
diagram shows
electrical
connections only)
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IR22771S/IR21771S(PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to VSS; all currents are defined positive into any lead. The Thermal Resistance and Power
Dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
IR22771
IR21771
- 0.3
1225
V
VB
High Side Floating Supply Voltage
- 0.3
625
V
V
VS
High Side Floating Ground Voltage
High-Side Inputs Voltages
- 25
+ 0.3
VB
VB
VB
VB
Vin+ / Vin-
G0 / G1
VCC
- 5
+ 0.3
+ 0.3
25
V
VB
High-Side Range Selectors
- 0.3
VB
- 0.3
V
Low-Side Fixed Supply Voltage
Low-Side Input Synchronization Signal
PWM Output
V
Sync
PO
- 0.3
- 0.3
- 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
50
V
V
OC
Over Current Output Voltage
Allowable Offset Voltage Slew Rate
Maximum Power Dissipation
Thermal Resistance, Junction to Ambient
Junction Temperature
V
dVS/dt
PD
V/ns
mW
ºC/W
ºC
ºC
ºC
250
RthJA
TJ
90
-40
-55
125
TS
Storage Temperature
150
TL
Lead Temperature (Soldering, 10 seconds)
300
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to
. The
VSS
offset rating is tested with all supplies biased at 15V differential.
VS
Symbol
VBS
Definition
High Side Floating Supply Voltage (VB V )
Min.
VS + 8.0
-5
Max.
VS + 20
1200
600
Units
V
V
V
V
-
S
IR22771
IR21771
VS
High Side Floating Ground Voltage
-5
Vin+ / Vin-
G0 / G1
VCC
High-Side Inputs Voltages
High-Side Range Selectors
Low Side Logic Fixed Supply Voltage
Low-Side Input Synchronization Signal
Sync Input Frequency
VS - 5.0
Note 1
8
VS + 5.0
Note1
20
V
V
Sync
fsync
VSS
VCC
4
20
kHz
V
PO
PWM Output
-0.3
-0.3
-40
Note 2
Note 2
125
OC
Over Current Output Voltage
Ambient Temperature
V
TA
ºC
Note 1: Shorted to VS or VB
Note 2: Pull-Up Resistor to VCC
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IR22771S/IR21771S(PbF)
Static Electrical Characteristics
VCC, VBS = 15V unless otherwise specified. Temp=27°C; Vin=Vin+ - Vin.
Pin: VCC, VSS, VB, VS
Test
Conditions
Symbol
Definition
Quiescent VBS supply current
Quiescent VCC supply current
Min
Typ
Max
2.2
6
Units
mA
f
sync = 10kHz,
20kHz
IQBS
1
f
sync = 10kHz,
20kHz
IQCC
mA
VB = VS =
1200V
IR22771
IR21771
50
50
µA
µA
Offset supply leakage
current
ILK
VB = VS = 600V
Pin: Vin+, Vin-, Sync, G0, G1, OC
Test
Conditions
Symbol
Definition
Min
Typ
Max
Units
Vinmax
Vinmin
VIH
Maximum input voltage before saturation
Minimum input voltage before saturation
Sync Input High threshold
250
mV
mV
V
-250
2.2
See Figure 1
See Figure 1
See Figure 1
V
VIL
Sync Input Low threshold
Sync Input Hysteresis
Vin+ input current
0.8
Vhy
Ivinp
0.2
-18
V
fsync = 4kHz to
-6
-8
µA
20kHz
G1, G0 = VB-
5V
Ipu
G0, G1 pull-up Current
-20
µA
|Vocth
|
Over Current Activation Threshold
SYNC to VSS internal pull-down
300
6
470
12
mV
RSync
kΩ
@ I = 2mA
RonOC
Over Current On Resistance
25
75
Ω
Figure
See
3
Schmitt trigger
SYNC
Rsync
VSS
VIL
VIH
Vhy
Figure 1: Sync input thresholds
Figure 2: Sync input circuit
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IR22771S/IR21771S(PbF)
Pin: PO
Symbol
Test
Definition
Min
Typ
Max
Units
Conditions
R
fsync
pull-up=500 Ω
= 4, 20kHz
Input offset voltage measured by PWM
output
VPOs
-50
20
mV
Vthreshold=2.75V
Ext supply=5V
(See Figure 6)
∆VPOs
∆Tj
/
Input offset voltage temperature drift
TBD
µV/°C
∆offset between samples on channel1
and channel2 measured at PO (See
Note1)
f
sync = 10kHz
∆VPos
-10
-38
10
mV
See Figure 6
Gp
PWM Output Gain
-40.5
TBD
-42.5
%/V
Vin=±250mV
∆Gp ∆Tj PWM Output Gain Temperature Drift
%/(V*ºC)
/
VS-VSS = 0,
600V
sync = 10kHz
CMRR
PO Output common mode (VS) rejection
PO
0.2
m%/V
f
VPolin
PO Linearity
0.07
TBD
0.2
1.6
%
fsync = 10kHz
fsync = 10kHz
∆ Vlin ∆Tj PO Linearity Temperature Drift
%/ºC
/
OC active (See
VthPO
PSRR PO PSRR for PO Output
RonPO PO On Resistance
PO threshold for OC reset
0.8
25
V
Figure 4
)
VCC=VBS=
8,20V
0.2
%/V
@ I = 2mA
See Figure 3
75
Ω
Note1: Refer to PO output description for channels definition
PO
or
OC
RON
Internal signal
VSS
Figure 3: PO and OC open collector circuit
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IR22771S/IR21771S(PbF)
AC Electrical Characteristics
VBIAS V , V ) = 15V unless otherwise specified. Temp=27°C.
(
CC
BS
Test
Conditions
Symbol
fsync
fout
Definition
Min
Typ
Max
Units
PWM frequency
Throughput
4
20
kHz
ksample/sec
kHz
2 ⋅ fsync
fsync
BW
Bandwidth (@ -3 dB)
1
GD
Group Delay (input filter)
µs
4⋅fsync
Dmin
Minimum Duty Cycle (Note 1)
Maximum Duty Cycle (Note 1)
De-bounce time of OC
10
30
%
%
Vin=+Vinmax
Vin=-Vinmin
See Figure 4
Figure
Dmax
tdOCon
TOCoff
2.7
3.5
4.7
0.5
µs
µs
Time to reset OC forcing PO
See
4
0.30
2⋅fsync
1.3
MD
SR
Measure Delay
µs
µs
0.51
Step response (max time to reach
steady state)
See Figure 5
fsync
fsync
Note 1: negative logic, see fig. 4 on page 7
Note 2: Cload < 5 nF avoids overshoot
Figure 4: OC timing diagram
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IR22771S/IR21771S(PbF)
Vmax
V
in
Vmin
SYNC
PO
SR
MD
(PO full response time)
Figure 5: PO timing diagram
Vmax
V
in
Vmin
SYNC
Supply=5V
Vth=2.75V
PO
GP *VPOs1
GP *VPOs0
GP *VPOs1
GP *VPOs0
20%
20%
20%
DVPOs= VPOs1-VPOs0
20%
Figure 6: ∆offset between two consecutive samples measured at PO
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IR22771S/IR21771S(PbF)
Lead Assignments
SOIC16WB
Lead Definitions
Pin
1
Symbol
VCC
NC
Description
Low side voltage supply
No connection
2
3
4
VSS
NC
Low side ground supply
No connection
5
NC
No connection
6
7
8
9
OC
PO
Sync
NC
Over current signal (open drain)
PWM output (open drain)
DSP synchronization signal
No connection
10
11
12
13
14
15
16
NC
G0
G1
VS
VIN-
VIN+
VB
No connection
Integrator gain lsb
Integrator gain msb
High side return
Negative sense input
Positive sense input
High side supply
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IR22771S/IR21771S(PbF)
Timing and logic state diagrams description
** See OC and PO detailed descriptions below in this document
Functional block diagram
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IR22771S/IR21771S(PbF)
A residual offset can be read in PO duty cycle
according to VPOs (see Static electrical
characteristics).
1
DEVICE DESCRIPTION
1.1 SYNC input
Sync input clocks the whole device. In order to
make the device work properly it must be
synchronous with the triangular PWM carrier as
shown in Figure 8.
According to Figure 8, it can be assumed that odd
cycles are represented by SYNC at high level
(channel 1) and even cycles represented by SYNC
at low level (channel 2).
The two channels are independent in order to
provide the correct duty cycle value of PO even for
non-50% duty cycle of SYNC signal. Small variation
of SYNC duty cycle are then allowed and
automatically corrected when calculating the duty
cycle using Eq. 1.
However, channel 1 and channel 2 can have a
difference in offset value which is specified in
∆VPOS (see Static electrical characteristics).
To implement a correct offset compensation of PO
duty cycle, each channel must be compensated
separately.
SYNC pin is internally pulled-down (10 kΩ) to VSS.
1.2 PWM Output (PO)
PWM output is an open collector output (active low).
It must be pulled-up to proper supply with an
external resistor (suggested value between 500Ω
and 10kΩ).
τ
Supply
Vlow
1.3 Over Current output (OC)
OC output is an open drain pin (active low).
A simplified block diagram of the over current circuit
is shown in the Figure 9.
Figure 7: PO rising and falling slopes
PO pull-up resistor determines the rising slope of
the PO output and the lower value of PO as shown
in Figure 7, where τ = RC , C is the total PO pin
capacitance and R is the pull-up resistance.
Over current is detected when |Vin|=|Vinp-Vinm|>VOCth
If an event of over current lasts longer than tdOCon
.
,
OC pin is forced to VSS and remains latched until
PO is externally forced low for at least tOCoff (see
timing on Figure 4). During an over current event
(OC is low), PO is off (pulled-up by external
resistor).
If OC is reset by PO and over current is still active,
OC pin will be forced low again by the next edge of
SYNC signal.
Ron
Vlow = Supply ⋅
Ron +R pull−up
where Ron is the internal open collector resistance
and Rpull-up is the external pull-up resistance.
PO duty cycle is defined for active low logic by the
following formula:
To reset OC state PO must be forced to VSS for at
least TOCoff
.
Toff _ cycle _ n+1
•
Auto reset function
Eq. 1 Dn =
The auto reset function consists in clearing
automatically the OC fault.
Tcycle _ n
To enable the auto reset function, simply short
circuit the OC pin with the PO pin.
PO duty cycle (Dn) swings between 10% and 30%.
Zero input voltage corresponds to 20% duty cycle.
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IR22771S/IR21771S(PbF)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Triangular
SYNC (0)
PO
Toff_cycle1
Tcycle1
Toff_cycle2
Toff _ cycle2
Dn =
1
Tcycle2
Toff_cycle3
Tcycle3
Tcycle1
Toff_cycle4
Toff _ cycle3
Dn2 =
Toff _ cycle4
Tcycle2
Dn3 =
Tcycle3
Figure 8: PO Duty Cycle
Ext
supply
High voltage
Low voltage
OC
VIN+
VIN-
Over current
detection
S
R
D
VSS
PO
Figure 9: Over current block diagram
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IR22771S/IR21771S(PbF)
1.5 Filter AC characteristic
1.4 DC transfer functions
The working principle of the device can be easily
explained by Figure 10, in which the main signals
are represented.
IR21771/22771 signal path can be considered as
composed by three stages in series (see Figure 13).
The first two stages perform the filtering action.
Stage 1 (input filter) implements the filtering action
originating the transfer function shown in Figure 14.
The input filter is a self-adaptive reset integrator
which performs an accurate ripple cancellation. This
stage extracts automatically the PWM frequency
from Sync signal and puts transmission zeros at
even harmonics, rejecting the unwanted PWM
noise.
Triangular
reference
SYNC
Vin
PO
The following timing diagram shows the principle by
which even harmonics are rejected (Figure 12).
Figure 10: Main current sensor signals and
outputs
PWM out (PO pin) gives a duty cycle which is
inversely proportional to the input signal.
Eq. 2 gives the resulting Dn of the PWM output (PO
pin):
%
Eq. 2 Dn = 20% − 40 ⋅Vin
V
where Vin = Vinp-Vinm
PO duty cycle
30%
25%
20%
15%
Vin
10%
Figure 12: Even harmonic cancellation principle
As can be seen from Figure 14, the odd harmonics
are rejected as a first order low pass filter with a
Figure 11: PO Duty Cycle (Dn)
single pole placed in fPWM
.
The input filter group delay in the pass-band is very
low (see GD on AC electrical characteristics) due to
the beneficial action of the zeroes.
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IR22771S/IR21771S(PbF)
Figure 13: Simplified block diagram
Figure 14: Input filter transfer function (10 kHz PWM)
The second stage samples the result of the first
Odd harmonic cancellation using SYNC2 (i.e. 90
degrees shifted SYNC signal) signal will introduce
Tsync/4 additional propagation delay.
stage at double Sync frequency. This action can be
used to fully remove the odd harmonics from the
input signal.
To perform this cancellation it is necessary a shift of
90 degrees of the SYNC signal with respect to the
triangular carrier edges (SYNC2).
The following timing diagrams show the principle of
odd harmonics cancellation (Figure 15), in which
SYNC2 allows the sampling of stage 1 output
during odd harmonic zero crossings.
Another way to obtain the same result (odd
harmonics cancellation) can be achieved by
controller computing the average of two consecutive
PO results using SYNC1 (SYNC is in this case
aligned to triangular edges, i.e. 0 degree shift).
This method is suitable for most symmetric (center
aligned) PWM schemes.
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IR22771S/IR21771S(PbF)
reduced by half allowing zeroes to be put at fPWM
multiples (i.e. even and odd harmonics cancellation,
no more computational effort needed by the
controller).
For this particular PWM scheme another suitable
solution is driving the IR2x771 with a half frequency
SYNC signal (fSYNC=fPWM/2).
In this case the cut frequency of the input filter is
Switching level
Triangular
Phase voltage
Phase current
Current Mean
Stage 1 input:
Input signal
components
(1st and 2nd
Fundamental
harmonic
Third
harmonic
harmonic only)
Fundamental
harmonic
Stage 1
output
Third
harmonic
Sampling
instant
SYNC 1
Error
Sampling
instant
SYNC 2
Figure 15: Even harmonic cancellation principle
G0 and G1 do not affect the overall current sensor
gain.
1.6 Input filter gain setting
G0 and G1 pins are used to change the time
constant of the integrators of the high side input
filter.
To avoid internal saturation of the input filter, G0
and G1 must be connected according to SYNC
frequency as shown in Table 1. A too small time
constant may saturate the internal integrator, while
a large time constant may reduce accuracy.
f PWM
G0
VB
VS
VB
VS
G1
VB
VB
VS
VS
> 16 kHz *
16 / 10 kHz
10 / 6 kHz
< 6 kHz
*Æ 40 kHz
Table 1: G0, G1 gain settings
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IR22771S/IR21771S(PbF)
2 Sizing tips
2.1 Bootstrap supply
The VBS1,2,3 voltage provides the supply to the high
side drivers circuitry of the IR22771S/IR21771S.
VBS supply sit on top of the VS voltage and so it
must be floating.
Then we have:
QTOT = QLS + (IQBS + +ILK + ILK _ DIODE + ILK _CAP ) ⋅THON
The minimum size of bootstrap capacitor is then:
QTOT
The bootstrap method to generate VBS supply can
be used with IR22771S/IR21771S current sensors.
The bootstrap supply is formed by a diode and a
capacitor connected as in Figure 16.
CBOOT min
=
∆VBS
Some important considerations
a) Voltage ripple
There are three different cases making the
bootstrap circuit get conductive (see Figure 16)
ILOAD < 0; the load current flows in the low side
IGBT displaying relevant VCEon
VBS = VCC −VF −VCEon
Figure 16: bootstrap supply schematic
In this case we have the lowest value for VBS.
This represents the worst case for the bootstrap
capacitor sizing. When the IGBT is turned off the
Vs node is pushed up by the load current until the
high side freewheeling diode get forwarded
biased
This method has the advantage of being simple and
low cost but may force some limitations on duty-
cycle and on-time since they are limited by the
requirement to refresh the charge in the bootstrap
capacitor.
ILOAD = 0; the IGBT is not loaded while being
Proper capacitor choice can reduce drastically
these limitations.
on and VCE can be neglected
VBS = VCC −VF
Bootstrap capacitor sizing
Given the maximum admitted voltage drop for VBS,
namely ∆VBS, the influencing factors contributing to
ILOAD > 0; the load current flows through the
freewheeling diode
VBS decrease are:
− Floating section quiescent current (IQBS);
− Floating section leakage current (ILK)
− Bootstrap diode leakage current (ILK_DIODE);
− Charge required by the internal level shifters
(QLS); typical 20nC
− Bootstrap capacitor leakage current (ILK_CAP);
− High side on time (THON).
VBS = VCC −VF +VFP
In this case we have the highest value for VBS.
Turning on the high side IGBT, ILOAD flows into it
and VS is pulled up.
b) Bootstrap Resistor
A resistor (Rboot) is placed in series with bootstrap
diode (see Figure 16) so to limit the current when
the bootstrap capacitor is initially charged. We
suggest not exceeding some Ohms (typically 5,
maximum 10 Ohm) to avoid increasing the VBS time-
constant. The minimum on time for charging the
bootstrap capacitor or for refreshing its charge must
be verified against this time-constant.
ILK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using
at least one low ESR ceramic capacitor (paralleling
electrolytic and low ESR ceramic may result in an
efficient solution).
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IR22771S/IR21771S(PbF)
c) Bootstrap Capacitor
For high THON designs where is used an electrolytic
tank capacitor, its ESR must be considered. This
parasitic resistance develops a voltage divider with
Rboot generating a voltage step on VBS at the first
charge of bootstrap capacitor. The voltage step and
the related speed (dVBS/dt) should be limited. As a
general rule, ESR should meet the following
constraint:
3.3 Antenna loops and inputs
connection
Current loops behave like antennas able to receive
EM noise. In order to reduce EM coupling, loops
must be reduced as much as possible. Figure 17
shows the high side shunt loops.
Moreover it is strongly suggested to use Kelvin
connections for Vin+ and Vin- to shunt paths and star-
connect VS to Vin- close to the shunt resistor as
explained in Fig. 18.
ESR
⋅VCC ≤ 3V
ESR + RBOOT
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best
compromise, the first acting as fast charge thank for
the gate charge only and limiting the dVBS/dt by
reducing the equivalent resistance while the second
keeps the VBS voltage drop inside the desired ∆VBS.
VB
VS
Vin-
Vin+
d) Bootstrap Diode
The diode must have a BV> 600V (or 1200V
depending on application) and a fast recovery time
(trr < 100 ns) to minimize the amount of charge fed
back from the bootstrap capacitor to VCC supply.
Figure 18: Recommended shunt connection
3.4 Supply capacitors
The supply capacitors must be placed as close as
possible to the device pins (VCC and VSS for the
ground tied supply, VB and VS for the floating
supply) in order to minimize parasitic traces
inductance/resistance.
3
PCB LAYOUT TIPS
3.1 Distance from H to L voltage
The IR22771S/IR21771S package (wide body)
maximizes the distance between floating (from DC-
to DC+) and low voltage pins (VSS). It’s strongly
recommended to place components tied to floating
voltage in the respective high voltage portions of the
device (VB, VS) side.
3.2 Ground plane
Ground plane must NOT be placed under or nearby
the high voltage floating side to minimize noise
coupling.
VB
VS
Antenna
Loop
Vin-
Vin+
Figure 17: antenna loops
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IR22771S/IR21771S(PbF)
Case Outline
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This part has been qualified for the Industrial Market
Data and specifications subject to change without notice. 8/17/2005
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