IR2277SPBF [INFINEON]
Phase Current Sensor IC for AC motor control; 相电流传感器IC用于交流电机控制
| 型号： | IR2277SPBF |
| 厂家： | 
Infineon |
| 描述： | Phase Current Sensor IC for AC motor control |
| 文件： | 总20页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60233 revB
IR2277S/IR2177S(PbF)
Phase Current Sensor IC for AC motor control
Features
Product Summary
VOFFSET (max)
IR2277
IR2177
1200 V
600 V
• Floating channel up to 600 V for IR2177 & 1200 V for
IR2277
Vin range
±250mV
8-20 V
2.2 mA
• Synchronous sampling measurement system
• High PWM noise (ripple) rejection capability
• Digital PWM output
Bootstrap supply range
Floating channel quiescent
current (max)
Sensing latency (max)
7.5 µsec
• Fast Over Current detection
(@20kHz)
40ksample/sec
(@20kHz)
±470 mV
• Suitable for bootstrap power supplies
• Low sensing latency (<7.5 µsec @20kHz)
• Ratiometric analog output suitable for DSP A/D interface
Throughput
Over Current threshold
(max)
Description
IR2177/IR2277 is a high voltage, high speed, single phase current
sensor interface for AC motor drive applications. The current is
sensed by an external shunt resistor. The IC converts the analog
voltage into a time interval through a precise circuit that also
performs a very good ripple rejection showing small group delay.
The time interval is level shifted and given to the output both as a
PWM signal (PO) and analog voltage (OUT). The analog voltage is
proportional to the measured current and is ratio metric with respect
to an externally provided voltage reference. The max throughput is
40 ksample/sec suitable for up to 20 kHz asymmetrical PWM
modulation and max delay is <7.5 µsec (@20kHz). Also a fast over
current signal is provided for IGBT protection.
Package
Typical Connection
(Please refer to
Lead Assignments
for correct pin
configuration. This
diagram shows
electrical
connections only)
1
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IR2277S/IR2177S(PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to VSS, all currents are defined positive into any lead. The Thermal Resistance and Power
Dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
- 0.3
- 0.3
Max.
1225
625
Units
IR2277
IR2177
VB
High Side Floating Supply Voltage
V
VS
High Side Floating Ground Voltage
High-Side Inputs Voltages
- 25
+ 0.3
V
V
VB
VB
VB
VB
Vin+ / Vin-
G0 / G1
VCC
- 5
+ 0.3
+ 0.3
25
VS
VS
High-Side Range Selectors
- 0.3
V
Low-Side Fixed Supply Voltage
Low-Side Input Synchronization Signal
DSP Reference High and Low Voltages
Analog Output Voltage
- 0.3
V
Sync
VRH/VRL
Out
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
50
V
V
V
PO
PWM Output
V
OC
Over Current Output Voltage
Allowable Offset Voltage Slew Rate
Maximum Power Dissipation
Thermal Resistance, Junction to Ambient
Junction Temperature
V
dVS/dt
PD
V/ns
mW
ºC/W
ºC
ºC
ºC
250
RthJA
TJ
90
-40
-55
125
TS
Storage Temperature
150
TL
Lead Temperature (Soldering, 10 seconds)
300
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to Vss. The
offset rating is tested with all supplies biased at 15V differential.
Vs
Symbol
VBS
Definition
High Side Floating Supply Voltage (VB V )
Min.
VS + 8.0
Max.
VS + 20
1200
600
Units
V
-
S
IR2277
IR2177
VS
High Side Floating Ground Voltage
-5
V
V
Vin+ / Vin-
G0 / G1
VCC
High-Side Inputs Voltages
VS - 5.0
Note 1
8
VS + 5.0
Note1
20
High-Side Range Selectors
Low Side Logic Fixed Supply Voltage
Low-Side Input Synchronization Signal
Sync Input Frequency
V
V
Sync
VSS
4
VCC
fsync
Using PO
Using OUT
20
kHz
8
20
PO
OC
VRH
VRL
TA
PWM Output
-0.3
-0.3
3
Note 2
Note 2
VCC-2.5
VRH-3
125
V
V
Over Current Output Voltage
OUT Reference High Voltage
OUT Reference Low Voltage
Ambient Temperature
V
VSS
-40
V
ºC
Note 1: Shorted to VS or VB
Note 2: Pull-Up Resistor to VCC
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IR2277S/IR2177S(PbF)
Static Electrical Characteristics
, VBS = 15V unless otherwise specified. Temp=27°C; Vin=Vin+ - Vin.
VCC
Pin: VCC, VSS, VB, VS
Test
Units
Symbol
Definition
Min.
Typ.
Max.
2.2
6
Conditions
fsync = 10kHz,
20kHz
IQBS
IQCC
Quiescent VBS supply current
Quiescent VCC supply current
1
mA
mA
fsync = 10kHz,
20kHz
VB = VS =
1200V
IR2277
IR2177
50
50
ILK
Offset supply leakage current
µA
VB = VS = 600V
Pin: Vin+, Vin-, Sync, G0, G1, OC
Test
Conditions
Symbol
Definition
Min.
Typ.
Max.
Units
Vinmax
Vinmin
VIH
Maximum input voltage before saturation
Minimum input voltage before saturation
Sync Input High threshold
250
mV
mV
V
-250
2.2
See Figure 1
See Figure 1
See Figure 1
V
VIL
Sync Input Low threshold
Sync Input Hysteresis
Vin+ input current
0.8
Vhy
Ivinp
0.2
-18
V
fsync = 4kHz to
-6
-8
µA
20kHz
G1, G0 = VB-
5V
Ipu
G0, G1 pull-up Current
-20
µA
|Vocth
|
Over Current Activation Threshold
SYNC to VSS internal pull-down
300
6
470
12
mV
RSync
kΩ
@ I = 2mA
RonOC
Over Current On Resistance
25
75
Ω
Figure
See
3
Schmitt trigger
SYNC
Rsync
VSS
VIL
VIH
Vhy
Figure 1: Sync input thresholds
Figure 2: Sync input circuit
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IR2277S/IR2177S(PbF)
Pin: PO
Symbol
Test
Units
Definition
Min.
Typ.
Max.
Conditions
R
fsync
pull-up=500 Ω
= 4, 20kHz
Input offset voltage measured by PWM
output
VPOs
-50
20
mV
V
threshold=2.75V
Ext supply=5V
(See Figure 6)
∆VPOs
∆Tj
/
Input offset voltage temperature drift
TBD
µV/°C
∆offset between samples on channel1
and channel2 measured at PO (See
Note1)
f
sync = 10kHz
∆VPOs
-10
-38
10
mV
See Figure 6
Gp
PWM Output Gain
-40.5
TBD
-42.5
%/V
Vin=±250mV
∆Gp ∆Tj PWM Output Gain Temperature Drift
%/(V*ºC)
/
Vs-Vss = 0,
600V
sync = 10kHz
CMRR
PO Output common mode (VS) rejection
PO
0.2
m%/V
f
VPOlin
PO Linearity
0.07
TBD
0.2
1.6
%
10kHz
∆ Vlin ∆Tj PO Linearity Temperature Drift
%/ºC
10kHz
/
OC active (See
VthPO
PSRR PO PSRR for PO Output
RonPO PO On Resistance
PO threshold for OC reset
0.8
25
V
%/V
Ω
Figure 4
)
VCC=VBS=
8,20V
0.2
@ I = 2mA
See Figure 3
75
Note1: Refer to PO output description for channels definition
PO
or
OC
RON
Internal signal
VSS
Figure 3: PO and OC open collector circuit
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IR2277S/IR2177S(PbF)
Pin: OUT, VRH, VRL
Symbol
Test
Conditions
Definition
Min.
36
Typ.
Max.
84
50
Units
RREF
Vaos
VRH to VRL input resistance
kΩ
mV
f
sync = 8kHz, 20
Input offset voltage measured by
analog output
-100
kHz
∆ Vaos
∆Tj
/
Measured by
analog output
Input offset voltage temperature drift
TBD
µV / ºC
∆offset between samples on channel1
and channel2 measured at OUT
(Note1)
f
sync = 8kHz, 20
∆Vaos
kHz
VR=VRH-VRL=3V
Ga
Analog Output Gain
-20%
2VR
TBD
+20%
V/V
ºC-1
Analog Output Gain Temperature Drift
∆Ga / ∆Tj
Vs-Vss=0V,
600V
fsync = 10kHz
CMRR
OUT
Analog Output common mode (VS
offset) rejection
100
dB
f
sync = 8kHz,
20kHz
VOUTlin
Out Linearity
0.3
0.7
%
%/ºC
dB
fsync = 8kHz,
20kHz
VCC= VBS =8V,
20V
∆ Vlin /
∆Tj
PSRR
OUT
Out Linearity Temperature Drift
PSRR for Analog Output
TBD
30
100
VOUTl
VOUTh
Vout Low Saturation
Vout High Saturation
0
50
mV
V
Vin= -500mV
Vin = +500mV
VRH+0.2
VRH+0.7
Note1: Refer to PO output description for channels definition
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IR2277S/IR2177S(PbF)
AC Electrical Characteristics
VBIAS V , V ) = 15V unless otherwise specified. Temp=27°C.
(
CC
BS
Test
Units
Symbol
Definition
Min.
Typ.
Max.
Conditions
PO
4
8
20
20
fsync
PWM frequency
kHz
OUT
2⋅fsync
fout
Throughput
ksample/sec
kHz
fsync
BW
Bandwidth (@ -3 dB)
1
GD
Group Delay (input filter)
µs
4⋅fsync
Dmin
Minimum Duty Cycle (Note 1)
Maximum Duty Cycle (Note 1)
De-bounce time of OC
10
30
%
%
Vin=+Vinmax
Vin=-Vinmin
See Figure 4
Figure
Dmax
tdOCon
TOCoff
Cload
2.7
0
3.5
4.7
0.5
50
µs
µs
nF
Time to reset OC forcing PO
Analog output load capacitor
See
4
NOTE 2
SLOUT
tsettl
Analog output (OUT) Slew Rate
Output settling time (1%)
0.2
5
1
30
V/µs
µs
Cout ≤ 5 nF
Cout ≤ 5 nF
0.30
2⋅fsync
MD
Measure Delay
µs
See
0.51
fsync
1.3
Step response (max time to reach
steady state) for PO output
SR
µs
fsync
Figure 5
See
1.3
0.51
Step response (max time to reach
steady state) for OUT output
+ tsettl
+tsettl
SROUT
µs
fsync
fsync
Figure 5
Note 1: negative logic, see Figure 4 on page 7
Note 2: Cload < 5 nF avoids overshoot
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IR2277S/IR2177S(PbF)
Figure 4: OC timing diagram
Vmax
V
in
Vmin
SYNC
PO
SR
(PO full response time)
VRH
MD
OUT
VRL
tsettl
SROUT
(OUT full response time)
Figure 5: timing diagram
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IR2277S/IR2177S(PbF)
Vmax
V
in
Vmin
SYNC
Supply=5V
PO
Vth=2.75V
GP *VPOs0
GP *VPOs1
GP *VPOs0
GP *VPOs1
20%
20%
20%
DVPOs= VPOs1-VPOs0
20%
Figure 6: ∆offset between two consecutive samples measured at PO
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IR2277S/IR2177S(PbF)
Lead Assignments
SOIC16WB
Lead Definitions
Pin
1
2
Symbol
VCC
OUT
VSS
Description
Low side voltage supply
Analog output
Low side ground supply
3
4
5
6
7
8
9
VRL
VRH
OC
PO
Sync
NC
Lower rail of A/D voltage range
Higher rail of A/D voltage range
Over current signal (open drain)
PWM output (open drain)
DSP synchronization signal
No connection
10
11
12
13
14
15
16
NC
G0
G1
VS
VIN-
VIN+
VB
No connection
Integrator gain lsb
Integrator gain msb
High side return
Negative sense input
Positive sense input
High side supply
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IR2277S/IR2177S(PbF)
Timing and logic state diagrams description
** See OC and PO detailed descriptions below in this document
Functional block diagram
10
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IR2277S/IR2177S(PbF)
A residual offset can be read in PO duty cycle
1
Device Description
according
to
VPOs
(see
Static
electrical
characteristics).
1.1 SYNC input
According to
Sync input clocks the whole device. In order to
make the device work properly it must be
synchronous with the triangular PWM carrier as
shown in Figure 8.
Figure 8, it can be assumed that odd cycles are
represented by SYNC at high level (let’s name
channel 1 the output related to this state of SYNC)
and even cycles represented by SYNC at low level
(channel 2).
SYNC pin is internally pulled-down (10 kΩ) to VSS.
The two channels are independent in order to
provide the correct duty cycle value of PO even for
non-50% duty cycle of SYNC signal. Small variation
of SYNC duty cycle are then allowed and
automatically corrected when calculating the duty
cycle using Eq. 1.
1.2 PWM Output (PO)
PWM output is an open collector output (active low).
It must be pulled-up to proper supply with an
external resistor (suggested value between 500Ω
and 10kΩ).
However, channel 1 and channel 2 can have a
difference in offset value which is specified in
∆VPOS (see Static electrical characteristics).
To implement a correct offset compensation of PO
duty cycle and analog OUT, each channel must be
compensated separately.
τ
Supply
Vlow
Figure 7: PO rising and falling slopes
1.3 Over Current output (OC)
OC output is an open drain pin (active low).
A simplified block diagram of the over current circuit
is shown in the
PO pull-up resistor determines the rising slope of
the PO output and the lower value of PO as shown
in Figure 7, where τ = RC , C is the total PO pin
capacitance and R is the pull-up resistance.
Figure 9.
Over current is detected when |Vin|=|Vinp-Vinm|>VOCth
If an event of over current lasts longer than tdOCon
.
,
Ron
Vlow = Supply ⋅
OC pin is forced to VSS and remains latched until
PO is externally forced low for at least tOCoff (see
timing on Figure 4). During an over current event
(OC is low), PO is off (pulled-up by external
resistor).
Ron +R pull−up
where Ron is the internal open collector resistance
and Rpull-up is the external pull-up resistance.
If OC is reset by PO and over current is still active,
OC pin will be forced low again by the next edge of
SYNC signal.
PO duty cycle is defined for active low logic by the
following formula:
To reset OC state PO must be forced to VSS for at
Toff _ cycle _ n+1
least TOCoff
.
Eq. 1 Dn =
•
Autoreset function
The autoreset function consists in clearing
automatically the OC fault.
Tcycle _ n
PO duty cycle (Dn) swings between 10% and 30%.
Zero input voltage corresponds to 20% duty cycle.
To enable the autoreset function, simply short
circuit the OC pin with the PO pin.
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IR2277S/IR2177S(PbF)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Triangular
SYNC (0)
PO
Toff_cycle1
Tcycle1
Toff_cycle2
Toff _ cycle2
Dn =
Tcycle2
Toff_cycle3
Tcycle3
1
Tcycle1
Toff_cycle4
Toff _ cycle3
Dn2 =
Tcycle2
Toff _ cycle4
Dn3 =
Tcycle3
Figure 8: PO Duty Cycle
Ext
supply
High voltage
Low voltage
OC
VSS
VIN+
VIN-
Over current
detection
S
R
D
PO
Figure 9: Over current block diagram
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IR2277S/IR2177S(PbF)
1.4 Analog Output (OUT)
The analog output is internally buffered and capable
of driving capacitive loads ranging up to 50nF.
OUT
VRH
VRH and VRL set the dynamic range and gain of OUT
pin.
Additional circuitry to protect A/D converter input
against excessive voltage is not required.
Hereafter follow some definitions (see Figure 10
and following).
VRH+VRL
2
VRL
VSS
•
•
Vin=Vinp-Vinm
Input referred analog offset (Vaos): It is
the input that gives an output that equals
Vin
(Vpos if PO is measured
Vaos
VRH + VRL
instead of OUT)
OUT =
(referred to VSS).
Figure 10: Input offset definition
2
∆OUT
∆Vin
•
•
Gain: It is defined by the ratio Ga=
.
OUT
VRH
Linearity: It is defined by the maximum
difference between the ideal OUT/Vin curve
and the measured curve depurated of the
offset voltage and the gain error.
OUT
The analog output is also defined by some dynamic
characteristics (see figure 8):
Ga
Vin
Gid
•
•
Slew Rate (SLOUT). The maximum slope of
OUT measured in V/µs
Settling time (tsettl). Time needed by the
analog output (OUT) to reach 90% of final
value.
VRL
VSS
Vin
Figure 11: Gain definition
•
•
Measure delay (MD). It is defined by the
time interval between the actual SYNC
edge and PO rising edge.
Step response (SR). Is the time needed by
Output to reach the final value after a step
of the input.
OUT
VRH
Is always within the following range:
Linearity
Error
1
1
+ MD + tsettl ≤ SROUT ≤
+ MD + tsettl
Ga
2⋅ fSYNC
fSYNC
Gid
VRL
VSS
Vin
Figure 12: Linearity error definition
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IR2277S/IR2177S(PbF)
1.5 DC transfer functions
VRH +VRL
Eq. 3 OUT = 2⋅
(
VRH −VRL ⋅Vin +
)
2
The working principle of the device can be easily
explained by Figure 13, in which the main signals
are represented.
The same equation can be referred to VRL, as
follows in Eq. 4:
Triangular
reference
Eq. 4
VRH −VRL
SYNC
OUT −VRL = 2⋅
(
VRH −VRL ⋅Vin +
)
2
Vin
PO
OUT
VRH
VRH
OUT
VRL
(VRH+VRL)/2
Figure 13: Main current sensor signals and
outputs
Vin
VRL
PWM out (PO pin) gives a duty cycle which is
inversely proportional to the input signal while the
OUT pin gives the analog converted output.
Eq. 2 gives the resulting Dn of the PWM output (PO
pin):
Figure 15: ideal OUT/Vin transfer function
%
Eq. 2 Dn = 20% − 40 ⋅Vin
V
where Vin = Vinp-Vinm
PO duty cycle
30%
25%
20%
15%
Vin
10%
Figure 14: PO Duty Cycle (Dn)
The Voltage-to-Time conversion (Vin to PO) must be
reconstructed (see Functional Block Diagram) to
give an analog voltage output at OUT pin.
OUT pin swings from VRL to VRH, so the analog
output (referred to VSS) follows Eq. 3:
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IR2277S/IR2177S(PbF)
As can be seen from Figure 18, the odd harmonics
are rejected as a first order low pass filter with a
Filter AC characteristic
single pole placed in fPWM
.
IR2177/2277 signal path can be considered as
composed by three stages in series (see Figure 17).
The first two stages perform the filtering action.
Stage 1 (input filter) implements the filtering action
originating the transfer function shown in Figure 18.
The input filter is a self-adaptive reset integrator
which performs an accurate ripple cancellation. This
stage extracts automatically the PWM frequency
from Sync signal and puts transmission zeros at
even harmonics, rejecting the unwanted PWM
noise.
The input filter group delay in the pass-band is very
low (see GD on AC electrical characteristics) due to
the beneficial action of the zeroes.
The second stage samples the result of the first
stage at double Sync frequency. This action can be
used to fully remove the odd harmonics from the
input signal.
To perform this cancellation it is necessary a shift of
90 degrees of the SYNC signal with respect to the
triangular carrier edges (SYNC2).
The following timing diagrams show the principle of
odd harmonics cancellation (Figure 19), in which
SYNC2 allows the sampling of stage 1 output
during odd harmonic zero crossings.
The following timing diagram shows the principle by
which even harmonics are rejected (Figure 16).
Odd harmonic cancellation using SYNC2 (i.e. 90
degree shifted SYNC signal) signal will introduce
Tsync/4 additional propagation delay.
Anther way to obtain the same result (odd
harmonics cancellation) can be achieved by
controller computing the average of two consecutive
PO results using SYNC1 (SYNC is in this case
aligned to triangular edges, i.e. 0 degree shift).
This method is suitable for most symmetric (center
aligned) PWM schemes.
For this particular PWM scheme another suitable
solution is driving the IR2x77 with a half frequency
SYNC signal (fsync=fPWM/2).
In this case the cut frequency of the input filter is
reduced by half allowing zeroes to be put at fPWM
multiples (i.e. even and odd harmonics cancellation,
no more computational effort needed by the
controller).
Figure 16: Even harmonic cancellation principle
Figure 17: Simplified block diagram
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IR2277S/IR2177S(PbF)
Figure 18: Input filter transfer function (10 kHz PWM)
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IR2277S/IR2177S(PbF)
Switching level
Triangular
Phase voltage
Phase current
Current Mean
Stage 1 input:
Input signal
components
(1st and 2nd
Fundamental
harmonic
Third
harmonic
harmonic only)
Fundamental
harmonic
Stage 1
output
Third
harmonic
Sampling
instant
SYNC 1
Error
Sampling
instant
SYNC 2
Figure 19: Even harmonic cancellation principle
1.6 Input filter gain setting
2
Sizing tips
G0 and G1 pins are used to change the time
constant of the integrators of the high side input
filter.
To avoid internal saturation of the input filter, G0
and G1 must be connect according to SYNC
frequency as shown in Table 1. A too small time
constant may saturate the internal integrator, while
a large time constant may reduce accuracy.
G0 and G1 do not affect the overall current sensor
gain.
2.1 Bootstrap supply
The VBS1,2,3 voltage provides the supply to the high
side drivers circuitry of the IR2277S/IR2177S. VBS
supply sit on top of the VS voltage and so it must be
floating.
The bootstrap method to generate VBS supply can
be used with IR2277S/IR2177S current sensors.
The bootstrap supply is formed by a diode and a
capacitor connected as in Figure 20.
f PWM
G0
VB
VS
VB
VS
G1
VB
VB
VS
VS
> 16 kHz *
16 / 10 kHz
10 / 6 kHz
< 6 kHz
*Æ 40 kHz
Table 1: G0, G1 gain settings
Figure 20: bootstrap supply schematic
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IR2277S/IR2177S(PbF)
This method has the advantage of being simple and
low cost but may force some limitations on duty-
cycle and on-time since they are limited by the
requirement to refresh the charge in the bootstrap
capacitor.
high side freewheeling diode get forwarded
biased
ILOAD = 0; the IGBT is not loaded while being
on and VCE can be neglected
Proper capacitor choice can reduce drastically
these limitations.
VBS = VCC −VF
ILOAD > 0; the load current flows through the
Bootstrap capacitor sizing
freewheeling diode
Given the maximum admitted voltage drop for VBS,
namely ∆VBS, the influencing factors contributing to
VBS = VCC −VF +VFP
VBS decrease are:
In this case we have the highest value for VBS.
Turning on the high side IGBT, ILOAD flows into it
and VS is pulled up.
− Floating section quiescent current (IQBS);
− Floating section leakage current (ILK)
− Bootstrap diode leakage current (ILK_DIODE);
− Charge required by the internal level shifters
(QLS); typical 20nC
b) Bootstrap Resistor
A resistor (Rboot) is placed in series with the
bootstrap diode (see Figure 20) to limit the current
when the bootstrap capacitor is initially charged. We
suggest not exceeding some Ohms (typically 5,
maximum 10 Ohms) to avoid increasing the VBS
time-constant. The minimum on time for charging
the bootstrap capacitor or for refreshing its charge
must be verified against this time-constant.
− Bootstrap capacitor leakage current (ILK_CAP);
− High side on time (THON).
ILK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using
at least one low ESR ceramic capacitor (paralleling
electrolytic and low ESR ceramic may result in an
efficient solution).
c) Bootstrap Capacitor
For high THON designs where an electrolytic tank
capacitor is used, its ESR must be considered. This
parasitic resistance develops a voltage divider with
Rboot generating a voltage step on VBS at the first
charge of bootstrap capacitor. The voltage step and
the related speed (dVBS/dt) should be limited. As a
general rule, ESR should meet the following
constraint:
Then we have:
QTOT = QLS + (IQBS + +ILK + ILK _ DIODE + ILK _CAP ) ⋅THON
The minimum size of bootstrap capacitor is then:
QTOT
CBOOT min
=
∆VBS
ESR
⋅VCC ≤ 3V
ESR + RBOOT
Some important considerations
a) Voltage ripple
There are three different cases making the
bootstrap circuit get conductive (see Figure 20)
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best
compromise, the first acting as fast charge tank for
the gate charge only and limiting the dVBS/dt by
reducing the equivalent resistance while the second
keeps the VBS voltage drop inside the desired ∆VBS.
ILOAD < 0; the load current flows in the low side
IGBT displaying relevant VCEon
d) Bootstrap Diode
VBS = VCC −VF −VCEon
The diode must have a BV> 600V (or 1200V
depending on application) and a fast recovery time
(trr < 100 ns) to minimize the amount of charge fed
back from the bootstrap capacitor to VCC supply.
In this case we have the lowest value for VBS.
This represents the worst case for the bootstrap
capacitor sizing. When the IGBT is turned off the
Vs node is pushed up by the load current until the
18
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IR2277S/IR2177S(PbF)
3.3 Antenna loops and inputs
connection
3
PCB LAYOUT TIPS
Current loops behave like antennas able to receive
EM noise. In order to reduce EM coupling loops
must be reduced as much as possible. Figure 21
shows the high side shunt loops.
Moreover it is strongly suggested to use Kelvin
connections for Vin+ and Vin- to shunt paths and star-
connect VS to Vin- close to the shunt resistor as
explained in Fig. 22.
3.1 Distance from H to L voltage
The IR2277S/IR2177S package (wide body)
maximizes the distance between floating (from DC-
to DC+) and low voltage pins (VSS). It is strongly
recommended to place components tied to floating
voltage in the respective high voltage portions of the
device (VB, VS) side.
3.2 Ground plane
Ground plane must NOT be placed under or nearby
the high voltage floating side to minimize noise
coupling.
V B
V S
VB
V in -
V in+
VS
Antenna
Loop
Vin-
Vin+
Figure 22: Recommended shunt connection
Figure 21: antenna loops
3.4 Supply capacitors
The supply capacitors must be placed as close as
possible to the device pins (VCC and VSS for the
ground tied supply, VB and VS for the floating
supply) in order to minimize parasitic traces
inductance/resistance
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IR2277S/IR2177S(PbF)
Case Outline
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This part has been qualified for the Industrial Market
Data and specifications subject to change without notice. 8/18/2005
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