IR3093MPBF_技术文档

IR3093

DATA SHEET

3 PHASE OPTERON, ATHLON, OR VR10.X CONTROL IC

DESCRIPTION

The IR3093 Control IC provides a full featured, cost effective, single chip solution to implement robust

power conversion solutions for three different microprocessor families; 1) AMD’s Opteron, 2) AMD’s

Athlon or 3) Intel’s VR-10.X family of processors. The user can select the appropriate VID range with a

single pin. Control and 3 phase Gate Drive functions are integrated into a single cost effective IC. . In

addition to CPU power, the IR3093 offers a compact, efficient solution for high current POL converters.

FEATURES

x

5 bit or 6 bit VID with 0.5% overall system accuracy

x

Selectable VID Code for AMD Opteron or Athlon or Intel VR10.X

Programmable Slew Rate response to “On-the-Fly” VID Code Changes

3A GATELX Pull Down Drive Capability

Programmable 100KHz to 540KHz oscillator

Programmable Voltage Positioning (can be disabled)

Programmable Softstart

Programmable Hiccup Over-Current Protection with Delay to prevent false triggering

Simplified Powergood provides indication of proper operation and avoids false triggering

Operates up to 21V input with 7.9V Under-Voltage Lockout

5V UVL with 4.36V Under-Voltage Lockout threshold

Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage

Enable Input

OVP Flag Output detects high side fet short at powerup

Pin compatible with IR3092, 2-phase PWM Control IC

Available 48L MLPQ package

ORDERING INFORMATION

Device

Order Quantity

IR3093MTR

*IR3093M

3000 per Reel

100 piece strips

* Samples Only

PACKAGE INFORMATION

VID3

GATEH1

PGND1

VID4

48L MLPQ

(7 x 7 mm Body)

_JA= 27^oC/W

ROSC

VOSNS-

OCSET

VDAC

VDRP

GATEL1

VCCL1_2

5VUVL

IR3093

48LDMLPQ

GATEL2

PGND2

–

FB

GATEH2

VCCH2

EAOUT

SS/DEL

SCOMP2

SCOMP3

VCCH3

GATEH3

PGND3

Page 1 of 39

07/15/04

IR3093

PIN DESCRIPTION

PIN# PIN SYMBOL

PIN DESCRIPTION

Inputs to VID D to A Converter

Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents

Remote Sense Input. Connect to ground at the Load.

1

2

3

4

VID3

VID4

ROSC

VOSNS-

Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current

source.

5

OCSET

Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced

to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate.

Buffered IIN signal. Connect an external RC network to FB to program converter output impedance

Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an

external resistor connected to the converter output voltage at the load and an internal current source. Bias

current is a function of ROSC. Also OVP sense

6

7

VDAC

VDRP

8

FB

9

EAOUT

SS/DEL

Output of the Error Amplifier

Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to

program the timing.

10

Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s

bandwidth. Phase 2 is forced to match phase 1’s current.

11

SCOMP2

Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s

bandwidth. Phase 3 is forced to match phase 1’s current.

12

SCOMP3

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

LGND

SETBIAS

VCC

Local Ground and IC substrate connection

External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.

Power for internal circuitry and source for BIASOUT regulator

Non-inverting input to the Phase 3 Current Sense Amplifier.

Inverting input to the Phase 3 Current Sense Amplifier.

200mA open-looped regulated voltage set by SETBIAS for GATE drive bias.

Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.

Non-inverting input to the Phase 2 Current Sense Amplifier.

Inverting input to the Phase 2 Current Sense Amplifier.

Ground Selects VR10.X VID, Float Selects OPTERON VID, VCC Selects ATHLON VID

Power for Phase 3 Low-Side Gate Driver.

Phase 3 Low-Side Gate Driver Output and input to GATEH3 non-overlap comparator.

Return for Phase 3 Gate Drivers

Phase 3 High-Side Gate Driver Output and input to GATEL3 non-overlap comparator.

Power for Phase 3 High-Side Gate Driver

Power for Phase 2 High-Side Gate Driver

Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.

Return for Phase 2 Gate Drivers

Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.

CSINP3

CSINM3

BIASOUT

PWRGD

CSINP2

CSINM2

VID_SEL

VCCL3

GATEL3

PGND3

GATEH3

VCCH3

VCCH2

GATEH2

PGND2

GATEL2

Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under

voltage condition initiates Soft Start.

32

5VUVL

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

VCCL1_2

GATEL1

PGND1

GATEH1

VCCH1

NC

CSINM1

CSINP1

OVP

ENABLE

OVPSNS

5VREF

VID5

Power for Phase 1 and 2 Low-Side Gate Drivers.

Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.

Return for Phase 1 Gate Drivers

Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.

Power for Phase 1 High-Side Gate Driver

Not connected

Inverting input to the Phase 1Current Sense Amplifier.

Non-inverting input to the Current Sense Amplifier.

Output that drives high during an Over-Voltage condition.

Enable Input. A logic low applied to this pin puts the IC into Fault mode.

Dedicated output voltage sense pin for Over Voltage Protection.

Compensation for internal voltage reference rail.

Inputs to VID D to A Converter

VID0

VID1

VID2

Page 2 of 39

07/15/04

IR3093

ABSOLUTE MAXIMUM RATINGS

Operating Junction Temperature……………..150^oC

Storage Temperature Range………………….-65^oC to 150^oC

1

2

3

4

5

6

7

8

NAME

VID3

VID4

VMAX

30V

0.5V

30V

10V

30V

n/a

30V

0.3V

30V

0.3V

30V

0.3V

30V

n/a

VMIN

-0.3V

-0.5V

-0.3V

n/a

-0.3V

ISOURCE

1mA

10mA

1mA

5mA

1mA

10mA

1mA

5mA

50mA

1mA

250mA

1mA

250mA

1mA

n/a

ISINK

1mA

10mA

1mA

5mA

1mA

20mA

1mA

5mA

1mA

250mA

1mA

20mA

1mA

ROSC

VOSNS-

OCSET

VDAC

VDRP

FB

EAOUT

SS/DEL

SCOMP2

SCOMP3

LGND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SETBIAS

VCC

CSINP3

CSINM3

BIASOUT

PWRGD

CSINP2

CSINM2

VID_SEL

VCCL3

GATEL3

PGND3

GATEH3

VCCH3

VCCH2

GATEH2

PGND2

GATEL2

5VUVL

VCCL1_2

GATEL1

PGND1

GATEH1

VCCH1

NC

CSINM1

CSINP1

OVP

ENABLE

OVPSNS

5VREF

VID5

VID0

VID1

VID2

3A for 100ns, 200mA DC

-0.3V DC, -2V for 100ns

3A for 100ns, 200mA DC

-0.3V

n/a

-0.3V DC, -2V for 100ns

3A for 100ns, 200mA DC

-0.3V

n/a

-0.3V DC, -2V for 100ns

3A for 100ns, 200mA DC

-0.3V

n/a

-0.3V DC, -2V for 100ns

3A for 100ns, 200mA DC

-0.3V

1mA

n/a

1mA

3A for 100ns, 200mA DC

-0.3V DC, -2V for 100ns

3A for 100ns, 200mA DC

-0.3V

n/a

-0.3V DC, -2V for 100ns

3A for 100ns, 200mA DC

-0.3V

n/a

1mA

20mA

1mA

30V

10V

30V

-0.3V

250mA

1mA

10mA

1mA

Page 3 of 39

07/15/04

IR3093

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over: 7.4V V_CC 21V, 4V V_CCLX 14V,

4V V_CCHX 28V, C_GATEHX=3.3nF, C_GATELX=6.8nF, 0^oC T_J 125 ^oC

PARAMETER

VDAC Reference

TEST CONDITION

MIN

TYP

MAX

UNIT

-0.3V VOSNS- 0.3V, Connect FB to

EAOUT, Measure V(EAOUT) –

V(VOSNS-) deviation from Table 1.

Applies to all VID codes.

System Set-Point Accuracy

0.5

%

Sink Current

Source Current

R_ROSC= 47kꢀꢁ9'$& 2&6(7

45

48

53

56

61

64

PA

VID Input Threshold, INTEL

VID_SEL=0, Referenced to VOSNS-

VID_SEL=Float, Referenced to VOSNS-

0.4

1.55

0.6

1.65

0.8

1.75

V

VID Input Threshold, AMD

VID_SEL OPTERON

Threshold

1.0

1.2

1.4

V

VID_SEL ATHLON Threshold

VID_SEL Float Voltage

VID_SEL Pull-up Resistance

3.0

2.1

30

3.3

2.6

50

3.8

3.2

100

V

k

Tracks ATHLON threshold

V(VID_SEL)<2.1V

VID_SEL Pull-down

Resistance

V(VID_SEL)>3.2V

60

150

350

k

VID Pull-up Current

VID Float Voltage

VID = 11111 Fault Blanking

Error Amplifier

VID0-5 = 1V

Referenced to LGND

Delay to PWRGD assertion

9

4.5

0.5

18

4.9

2.1

27

5.2

4.1

PA

V

Ps

Connect FB to EAOUT, Measure

V(EAOUT)-V(VDAC). Applies to all VID

codes and -0.3V<VOSNS-<0.3V. Note

2.

Input Offset Voltage

-5

-1

3

mV

FB Bias Current

DC Gain

Gain-Bandwidth Product

Slew Rate

Source Current

Sink Current

Max Voltage

R_ROSC= 47k

Note 1

23.5

90

4

26.4

100

7

1.25

430

1.1

4.9

50

29.4

105

PA

dB

MHz

V/Ps

PA

mA

V

mV

Note 1, 50mV FB signal

300

.75

4.5

600

1.5

5.3

200

Min Voltage

VDRP Buffer Amplifier

V(VDRP) – V(VDAC) with

CSINMX=CSINPX=0. Note 1.

Positioning Offset Voltage

Output Voltage Range

-125

0.2

0

125

mV

V

3.75

Page 4 of 39

07/15/04

IR3093

PARAMETER

VDRP Buffer Amplifier cont.

Source Current

TEST CONDITION

MIN

TYP

MAX

UNIT

4

8

20

mA

Sink Current

200

300

650

PA

Oscillator

Switching Frequency

Phase Shift

R_ROSC= 47k

Sequence: GATEH1-GATEH2-GATEH3

160

102

200

120

240

138

kHz

°

BIASOUT Regulator

SETBIAS Bias Current

Set Point Accuracy

BIASOUT Dropout Voltage

R_ROSC= 47k

V(SETBIAS)-V(BIASOUT) @ 100mA

I(BIASOUT)=100mA,Threshold when

V(SETBIAS)-V(BIASOUT)=0.45V

94

0.1

1.2

103

0.25

1.8

117.5

0.55

2.5

PA

V

BIASOUT Current Limit

Soft Start and Delay

SS/DEL to FB Input Offset

Voltage

150

0.8

250

1.1

450

1.8

mA

V

With FB = 0V, adjust V(SS/DEL) until

EAOUT drives high

Charge Current

Hiccup Discharge Current

OC Discharge Current

Charge/Discharge Current

Ratio

30

3.5

25

9

60

6

55

10

90

9

70

13

PA

PA/PA

Charge Voltage

Delay Comparator Threshold

Discharge Comparator

Threshold

3.8

190

170

4.0

250

265

4.2

300

350

V

mV

Relative to Charge Voltage

Over-Current Comparator

Input Offset Voltage

V(OCSET)-V(VDAC),

CSINM=CSINP1=CSINP2=CSINP3,

Note 1.

-125

0

125

mV

OCSET Bias Current

Max OCSET Set Point

Under-Voltage Lockout

VCC Start Threshold

VCC Stop Threshold

VCC Hysteresis

5VUVL Start Threshold

5VUVL Stop Threshold

5VUVL Hysteresis

R_ROSC= 47k

23.5

3.9

27

29.4

PA

V

7.4

6.9

400

4.05

3.92

100

7.9

7.4

540

4.36

4.17

200

8.4

7.9

700

4.55

4.33

250

V

mV

V

mV

Start – Stop

Page 5 of 39

07/15/04

IR3093

PARAMETER

PWRGD Output

Output Voltage

Leakage Current

Enable Input

TEST CONDITION

I(PWRGD) = 4mA

MIN

TYP

MAX UNIT

150

0

400

10

mV

V(PWRGD) = 5.5V

PA

Threshold, INTEL

Threshold, AMD

Input Resistance

Pull-up Voltage

Gate Drivers

VID_SEL=0, Referenced to VOSNS-

VID_SEL=Float, Referenced to VOSNS-

0.4

1.3

5

0.6

1.5

10

0.8

1.7

20

V

k

V

2.4

3.0

3.7

GATEH Rise Time

VCCHX = 8V, Measure 1V to 7V transition

time. Note 1.

VCCHX = 8V, Measure 7V to 1V transition

time. Note 1.

VCCLX= 8V, Measure 1V to 7V transition

time. Note 1.

VCCLX= 8V, Measure 7V to 1V transition

time. Note 1.

25

50

30

0

50

ns

V

GATEH Fall Time

GATEL Rise Time

GATEL Fall Time

High Voltage (AC)

Low Voltage (AC)

90

60

Measure VCCLX– GATELX or VCCHX –

GATEHX, Note 1

Measure GATELX or GATEHX, Note 1

0.5V

0

0.5V

V

GATEL low to GATEH high

delay

VCCHX = VCCLX= 8V, Measure the time

from GATELX falling to 1V to GATEHX

rising to 1V. Note 1.

VCCHX = VCCLX= 8V, Measure the time

from GATEHX falling to 1V to GATELX

rising to 1V. Note 1.

10

20

25

50

ns

GATEH low to GATEL high

delay

25

35

50

ns

Disable Pull-Down Current

GATHX or GATELX=2V with VCC = 0V.

Measure Gate pull-down current

50

PA

PWM Comparator

Propagation Delay

Note1

100

150

4

0.9

65

ns

V

Common Mode Input Range

Internal Ramp Start Voltage

Internal Ramp Amplitude

0.45

35

0.6

50

mV /

%DTC

Current Sense Amplifier

CSINPX Bias Current

CSINMX Bias Current

Input Current Offset Ratio

Average Input Offset Voltage

Offset Voltage Mismatch

Gain at T_J= 25 ^oC

-1

0.25

-5

0

1

0

23.5

20.4

0

1

2

5

25

21.5

1

75

2.8

PA

PA/PA

mV

V/V

mV

V

(VDRP-VDAC)/GAIN with CSINX=0. Note1

Monitor I(SCOMPX), Note1.

-5

22

18.5

-1

-25

0

Gain at T_J= 125 ^oC

Gain Mismatch

Differential Input Range

Common Mode Input Range

Note 1.

Page 6 of 39

07/15/04

IR3093

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Share Adjust Error Amplifier

Input Offset Voltage

MAX Duty Cycle Adjust Ratio

MIN Duty Cycle Adjust Ratio

Transconductance

Note 1

-5

1.5

0.6

100

16

0

5

mV

Compare Duty Cycle to GATEHX

Note 1

2.0

0.5

200

22

300

28

PA/V

PA

SCOMPX Source/Sink Current

Equal Duty Cycle Comparator

Threshold

0.45

0.60

0.95

V

Duty Cycle Match at Startup

Compare Duty Cycle to GATEHX

V(SS/DEL)=0

-5

300

-1

450

5

700

%

SCOMPX Precharge Current

0% Duty Cycle Comparator

Threshold Voltage

PA

Below Internal Ramp1 Start Voltage

80

50

130

200

180

400

mV

ns

Propagation Delay

VCCLX= 8V. Step EAOUT from .8V to

.3V and measure time to GATELX

transition to < 7V.

Body Breaking Disable

Comparator Threshold

OVP

Compare V(FB) to V(VDAC)

75

110

mV

VR10.X Comparator Threshold VID_SEL=0V. Compare to V(VDAC)

120

360

0.8

150

450

1.1

200

600

1.8

mV

V

AMD Comparator Threshold

Float VID_SEL. Compare to V(VDAC)

Power-up Headroom for OVP

Flag

VCC=OVPSNS where V(OVP)>0.5V.

Same for 5VUVL=OVPSNS.

OVPSNS Threshold at Power- VCC=2V, V(OVP) >0.5V. Same for

0.3

0.48

0.60

275

0.85

0.95

400

V

up

V(5VUVL)=2V.

SS/DEL Power-up Clear

Threshold

Propagation Delay

VCC=12V, V(OVPSNS)=1V,

0.35

VDAC=1.6V, where OVP<0.5V

VCCLX= 8V. V(EAOUT)=0V. Step

OVPSNS 540mV + V(VDAC). Measure

time to GATELX transition to >1V.

V(OVP)=0.5V, VCC=1.8V, 5VUVL=0V

OVP to LGND

I(OVP)=10uA, V(VCC) or V(5VUVL)-

V(OVP), VCC=1.8V

ns

OVP Source Current

OVP Pull Down Resistance

OVP High Voltage

10

30

0.4

75

60

0.70

PA

k

V

100

1.1

OVPSNS Bias Current

5VREF

-1

0.3

1.5

uA

Short Circuit Current

Supply Voltage

20

4.5

45

5

60

5.5

mA

V

I(5VREF)=0A

General

VCC Supply Current

VOSNS- Current

VCCHX and VCCL3 Current

VCCL1_2 Supply Current

5VUVL Supply Current

V(VCC)=21V

33

3.2

3

6

100

38

3.7

5

10

200

44

4.2

7

17

400

mA

uA

-0.3V VOSNS- 0.3V, All VID Codes

V(VCCHX)=28V, V(VCCL3)=14V

V(VCCL1_2)=14V

V(5VUVL)=5V, no OVP condition

Note 1: Guaranteed by design, but not tested in production

Note 2: Critical limits are identified with bold text

Note 3: VDAC Output is trimmed to compensate for Error Amp input offsets errors

Page 7 of 39

07/15/04

IR3093

TYPICAL OPERATING CHARACTERISTICS

I(FB) and I(OCSET) Current vs. ROSC

I(VDAC) Sink and Source Currents vs. ROSC

90

80

70

60

50

40

30

20

10

0

180

160

I(VDAC) Source

Current

I(FB)

140

120

100

80

I(OCSET)

I(VDAC) Sink Current

60

40

20

0

10

20

30

40

50

60

70

80

90

100 110 120

10 20 30 40 50 60 70 80 90 100 110 120 130

ROSC (kOhm)

ROSC in Kohms

I(SETBIAS) vs. ROSC

Oscillator freq vs. ROSC

320

300

280

260

240

220

200

180

160

140

120

100

80

500

450

400

350

300

250

200

150

100

50

60

40

20

0

10

20 30

40 50

60 70

80 90 100 110 120

10

20

30

40

50

60

70

80

90

100 110 120

ROSC (kOhm)

Frequency and Bias Current Accuracy vs. ROSC (includes

temperature)

Peak High side Gate drive current vs. Laod

capacitance

6

5

4

3

2

1

2.000

1.900

1.800

1.700

1.600

1.500

1.400

1.300

1.200

1.100

1.000

Frequency

VDAC Sink

VDAC Source

FB Bias

OCSET

I(RISE)

I(FALL)

SETBIAS

1

2

3

4

5

6

7

8

9

10

20

30

40

50

60

70

80

90

100

C(GATEHX) in nF

ROSC (kOhm)

Page 8 of 39

07/15/04

IR3093

Peak Low side Gate drive current vs. Laod

capacitance

3.250

3.000

2.750

2.500

2.250

2.000

1.750

1.500

1.250

1.000

I(RISE)

I(FALL)

1

2

3

4

5

6

7

8

9

10

C(GATELX) in nF

Error Amplifier Frequency Response

180

100

0

93dB DC gain

88° Phase Margin

3.1MHz Crossover

-100

-180

1.0Hz

100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz

10Hz

DB(V(comp))

P(V(comp))

Frequency

Page 9 of 39

07/15/04

IR3093

PWM Operation

The IR3093 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing

edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage

control loop. The PWM block diagram of the IR3093 is shown in Figure 2.

IROSC

U30

RSFF

CLK1

CLK2 CLK2

S

Q

PWM COMPARATOR

-

QB

CLK3

R

+

RESET DOMINANT

VIN

OSCBLOCK

OVPSNS

VDAC

GATEH1

GATEL1

+

-

IROSC/2

80mV

1

2

BB DISABLE

RCS1 CCS1

9p

0.6V

CDAC

RDAC

VDAC

ERROR AMPLIFIER

+

VOSNS-

FB

-

0% DUTY CYCLE

VIN

0.47V

RSFF

CLK2

GATEH2

GATEL2

S

VOUT SENSE+

VOUT+

Q

CCOMP

IROSC

PWM COMPARATOR

-

QB

1

2

R

RCOMP

+

RESET DOMINANT

EAOUT

VDRP

COUT

RCS2

CCS2

IROSC

VOUT-

VDRP BUFFER

+

RDRP

VOUT SENSE-

-

Share Adjust Error Amp

+

9p

0.6V

RFB

0 TO IROSC*3/4

-

SCOMP2

CSC2

RSC2

VIN

1

RSFF

CLK3

GATEH3

GATEL3

S

Q

PWM COMPARATOR

EAOUT

-

QB

R

2

+

RESET DOMINANT

RCS3

CCS3

IROSC

Share Adjust Error Amp

+

9p

0.6V

0 TO IROSC*3/4

-

SCOMP3

VDAC

CSC3

RSC3

CSINM3

CSINP3

X23.5

-

+

VDAC

CSINM2

CSINP2

-

+

CSINM1

CSINP1

-

+

Figure 2 – PWM Block Diagram

Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to increase,

the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 9pf capacitor is

charged by a current source that proportional to the switching frequency resulting in a ramp rate of 50mV per percent

duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the internal ramp amplitude

is typically 500mV from the starting point (or floor) to the crossing of the EAOUT control voltage. When the PWM

ramp voltage exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns off the high side driver, turns

on the low side driver, and discharges the PWM ramp to 0.6V until the next clock pulse.

Page 11 of 39

07/15/04

IR3093

50% INTERNAL OSCILLATOR RAMP

DUTY CYCLE

CLK1

CLK2

CLK3

RAMP3 MIN DUTY

CYCLE ADJUST

RAMP3 MAX DUTY

CYCLE ADJUST

RAMP3

FIXED RAMP1

RAMP2

EAOUT

0.6V

RAMP1 SLOPE

= 50mV / % DC

THE SHARE ADJUST ERROR AMPLIFIER CAN

CHANGE THE PULSE WIDTH OF RAMPS

0.5 RAMP1 TO 2.0 RAMP1 TO FORCE

CURRENT SHARING.

2

& 3 FROM

x

X

Figure 3 – 3 Phase Oscillator and PWM Waveforms

The RSFF is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseconds in

response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase

with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of

the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement

guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors

response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The

inductor current will increase much more rapidly than decrease in response to load transients.

This control method is designed to provide “single cycle transient response” where the inductor current changes in

response to load transients within a single switching cycle maximizing the effectiveness of the power train and

minimizing the output capacitor requirements.

Body Braking^TM

In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in

response to a load step decrease is;

T_SLEW= [L x (I_MAX- I_MIN)] / Vout

The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response

to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous

rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + V_{BODY DIODE}. The

minimum time required to reduce the current in the inductor in response to a load transient decrease is now;

T_SLEW= [L x (I_MAX- I_MIN)] / (Vout + V_{BODY DIODE}

)

Page 12 of 39

07/15/04

IR3093

Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be

increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through

the “0% Duty Cycle Comparator”. If the Error Amplifier’s output voltage drops below 0.47V, this comparator turns off

the low side gate driver.

Figure 4 depicts PWM operating waveforms under various conditions

CLK1

PULSE

EAOUT

PWM

Ramp1

0.6V

0.47V

GATEH1

GATEL1

STEADY-STATE

OPERATION

DUTY CYCLE INCREASE

DUE TO LOAD

DUTY CYCLE DECREASE DUE TO LOAD

DECREASE (BODY BRAKING) OR FAULT

STEADY-STATE

OPERATION

INCREASE

Figure 4 – PWM Operating Waveforms

Current Sense Amplifier

A high speed differential current sense amplifier is shown in Figure 5. Its gain decreases with increasing temperature

and is nominally 23.5 at 25ºC and 20.4 at 125ºC (-1400 ppm/ºC). This reduction of gain tends to compensate the 3850

ppm/ºC increase in inductor DCR. Since in most designs the IR3093 IC junction is hotter than the inductors these two

effects tend to cancel such that no additional temperature compensation of the load line is required.

The current sense amplifier can accept positive differential input up to 75mV and negative up to -25mV before clipping.

The output of the current sense amplifier is summed with the DAC voltage which is used for over current protection,

voltage positioning and current sharing.

vL

L

RL

iL

Vo

Rs

Cs

vc

Co

CSA

CO

Figure 5 – Inductor Current Sensing and Current Sense Amplifier

Page 13 of 39

07/15/04

IR3093

VCC Under Voltage Lockout (UVLO)

The VCC UVLO function monitors the IR3093’s VCC supply pin and ensures enough voltage is available to power the

internal circuitry. During power-up the fault latch is reset when VCC exceeds 7.9V and all other faults are cleared. The

fault latch is set when VCC drops below 7.4V and SS/DEL is below 3.75V.

5VUVL Under Voltage Lockout (5VUVL)

The 5VUVL function is provided for converters using a separate voltage supply other than VCC for gate driver bias.

The 5VUVL comparator prevents operation by discharging SS/DEL below 3.75V to force EAOUT low. The 5VUVL

comparator has an OK threshold of 4.36V ensuring adequate gate drive voltage is present and a fault threshold of

4.17V.

Power Good Output

The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft

start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.75V. The PWRGD pin

becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in operation and has

no fault, but does not ensure the output voltage is within the specification. Output voltage regulation within the design

limits can logically be assured however, assuming no component failure in the system.

Tri-State Gate Drivers

The GATELX drivers can pull down up to 3.5A peak current and source up to 1.5A. The GATEHX drivers can source

and sink up to 1.5A peak current. An adaptive non-overlap circuit monitors the voltage on the GATEHX and GATELX

pins to prevent MOSFET shoot-through current while minimizing body diode conduction.

The Error Amplifier output of the Control IC drives low in response to any fault condition such as VCC input under

voltage or output overload. The 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state

operation prevents negative inductor current and negative output voltage during power-down.

The Gate Drivers revert to a high impedance “off” state at VCCLX and VCCHX supply voltages below the normal

operating range. An 80kꢁUHVLVWRUꢁLVꢁFRQQHFWHGꢁDFURVVꢁWKHꢁ*$7(;ꢁDQGꢁ3*1';ꢁSLQVꢁWRꢁSUHYHQWꢁWKHꢁ*$7(;ꢁYROWDJHꢁ

from rising due to leakage or other cause under these conditions.

Over Voltage Protection (OVP)

The output Over-Voltage Protection comparator monitors the output voltage through the OVPSNS pin, the positive

remote sense point. If OVPSNS exceeds VDAC plus 150mV (for VR-10.0, 450mV for OPTERON and ATHLON,

selected with the VID_SEL pin), both GATEL pins drive high and the OVP pin sources 75uA current. The OVP circuit

over-rides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low

side MOSFET will remain ON until the over-voltage condition ceases. The lower MOSFETs alone can not clamp the

output voltage however an SCR or N-MOSFET could be triggered with the OVP pin to prevent processor damage.

In the event of a high side MOSFET short, the OVP flag is activated with as little supply voltage as possible. The

OVPSNS pin is compared against both VCC and 5VUVL for OVP conditions at power-up. VCC is monitored for

conversion off 12V, 5VUVL is monitored for conversion off 5V. The OVP pin flags a voltage greater than 0.5V with

supply voltages as low as 1.0V. This headroom voltage varies inversely with temperature. An external comparator

can be used to disable the silver box, activate a crowbar, or supply source.

The overall system must be considered when designing for OVP. In many cases the over-current protection of the AC-

DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without

damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not

possible, a fuse can be added in the input supply to the multiphase converter.

Page 14 of 39

07/15/04

IR3093

A Body Braking^TMDisable Comparator has been included to prevent false OVP firing during dynamic VID down

changes. The BB DISABLE Comparator disables Body Braking^TMwhen FB exceeds VDAC by 75mV. The low side

MOSFETs will then be controlled to keep V(FB) and V(VOUT) within 80mV of V(VDAC), below the 150mV INTEL OVP

trip point.

Page 15 of 39

07/15/04

IR3093

APPLICATIONS INFORMATION

VIN

CIN

VIN

GNDIN

ENABLE

OVP

VOUT SENSE+

VOUT+

RCS1 CCS1

2

C5VREF

CBST1

1

VID5

VID0

VID1

VID2

COUT

VID3

VID4

VOUT-

U13

VIN

VOUT SENSE-

RROSC

CDAC

VID3

VID4

ROSC

VOSNS-

OCSET

VDAC

VDRP

FB

EAOUT

SS/DEL

SCOMP2

SCOMP3

GATEH1

PGND1

GATEL1

VCCL1_2

5VUVL

GATEL2

PGND2

GATEH2

VCCH2

VCCH3

GATEH3

PGND3

CBST2

RFB

RDAC

RDRP

1

2

IR3093

48LD MLPQ

ROCSET

RCS2

CCS2

CCOMP

RCOMP

CSC2 CSC3

VIN

1

CSS

CBIAS

Csense-

RSC2 RSC3

IR3093

CBST3

VIN

CVCC

2

RSET

RCS3

CCS3

POWERGOOD

Figure 6 – System Diagram

VID Control

The IR3093 provides three different microprocessor solutions. The VID_SEL pin selects the appropriate Digital-to-

Analog Converters (DAC), VID threshold voltages, and Over Voltage Protection (OVP) threshold for either VR-10.0,

OPTERON, or ATHLON solutions. Reference voltages are shown in Table 1. The DAC output voltage is available

at the VDAC pin. A detailed block diagram of the VID control circuitry can be found in Figure 7. The VID pins are

internally pulled up to 4.9V by 18uA current sources. The VID input comparators have a 0.6V threshold for VR-10.0

or 1.65V threshold for OPTERON and ATHLON. The selected DAC voltage is provided at the Error Amplifier

positive input and to the VDAC pin by the trans-conductance DAC Buffer.

The VDAC voltage is trimmed to the Error Amplifier output voltage with EAOUT tied to FB via an accurate resistor.

This compensates DAC Buffer input offset, Error Amplifier input offset, and errors in the generation of the FB bias

current which is based on R_ROSC. This trim method provides a 0.5% system accuracy.

The IR3093 can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The

IR3093 detects a VID change and blanks the DAC output response for 400ns to verify the new code is valid and not

due to skew or noise. The sink/source capability of the VDAC buffer amp is programmed by the same external

resistor that sets the oscillator frequency, R_ROSC. The slew rate of the voltage at the VDAC pin can be adjusted by an

external capacitor between VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is

Page 16 of 39

07/15/04

IR3093

required to compensate the VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the

VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and

overshoot of the output voltage.

18uA

4.9V

TO FAULT

VID=11111X FAULT

BLANKING, 3.3us

VID5

VID0

VID1

VID2

VID3

VID4

"SLOW" VDAC

VID INPUT

COMPARATORS

(1 OF 6 SHOWN)

DIGITAL TO ANALOG

CONVERTER

VDAC

DAC BUFFER

-

SHOWN DEFAULT

"FAST" VDAC

+

TO VR10 WITH

IROSC

VID_SEL GROUNDED

+

DAC DEFAULTS

TO VR10 WITH

-

VID_SEL GROUNDED

0.6V

1.65V

5V

2.6V FLOAT VOLTAGE

3.3V

-

H=OPTERON

+

50K

150K

1.2V

+

VID_SEL

H=ATHLON

-

3.3V

VOSNS-

Figure 7– VID Control Block Diagram

VID = 11111X Fault

VID codes of 111111 and 111110 will set the fault latch and disable the Error Amplifier once SS/DEL is below 3.75V.

Page 17 of 39

07/15/04

IR3093

AMD Opteron VID Table

AMD ATHLON VID Table

VID_SEL Open. V(VDAC) is pre-

positioned 50mV higher than Vout

values listed below for load positioning.

VIDSEL to VCC. V(VDAC) is pre-

positioned 50mV higher than Vout values

listed below for load positioning.

Vout is measured at EAOUT with

ROSC=47K and a 1890 ohm resistor

connecting FB to EAOUT to cancel the

50mV pre-position offset.

Vout

VID4 VID3 VID2 VID1 VID0

(V)

Vout is measured at EAOUT with

ROSC=47K and a 1890 ohm resistor

connecting FB to EAOUT to cancel the

50mV pre-position offset.

Vout

VID4 VID3 VID2 VID1 VID0

(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

OFF⁴

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.850

1.825

1.800

1.775

1.750

1.725

1.700

1.675

1.650

1.625

1.600

1.575

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

OFF⁴

Note: 4 Output disabled (Fault mode)

Table 1 - Voltage Identification (VID)

Page 18 of 39

07/15/04

IR3093

INTEL VR-10.0 VID Table (VID_SEL Grounded, measured at EAOUT=FB. )

Processor Pins (0 = low, 1 = high)

Vout

(V)

Processor Pins (0 = low, 1 = high)

Vout

(V)

VID4 VID3 VID2 VID1 VID0 VID5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

OFF⁴

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

OFF⁴

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

Note: 4. Output disabled (Fault mode)

Table 1 Continued - Voltage Identification (VID)

Slew Rate Programming Capacitor CDAC and Resistor RDAC

VDAC sink current ISINK and source current ISOURCE are determined by R_ROSC,and their value can be found using

the curve in this data sheet. The slew rate of VDAC down-slope SRDOWN can be programmed by the external

capacitor CDAC as defined in Equation (1) and shown in Figure1. Resistor RDAC is used to compensate VDAC

circuit and is determined by Equation (2). The slew rate of VDAC up-slope SRUP is proportional to the down-slope

slew rate SRDOWN and is given by Equation (3).

I_SINK

C_DAC

(1)

SR_DOWN

Page 19 of 39

07/15/04

IR3093

15

3.2 ꢀ10

R_DAC 0.5 ꢁ

(2)

(3)

2

C_DAC

I_SOURCE

SR_UP

C_DAC

Oscillator Resistor R_ROSC

The oscillator frequency is programmable from 100kHz to 540kHz with an external resistor R_ROSCas shown in

Figure 6 oscillator generates an internal 50% duty cycle sawtooth signal (Figure 3.) that is used to generate 120°

out-of-phase timing pulses to set Phase 1,2 and 3 RS flip-flops. Once the switching frequency is chosen, R_ROSCcan

be determined from the curve in the Typical Operating Characteristics Section.

Soft Start, Over-Current Fault Delay, and Hiccup Mode

The IR3093 has a programmable soft-start function to limit the surge current during converter power-up. A capacitor

connected between the SS/DEL and LGND pins controls soft start timing as well as over-current protection delay

and hiccup mode timing.

Figure 8 depicts the various operating modes of the SS/DEL function. Under a no fault condition, the SS/DEL

capacitor will charge. The SS/DEL charge soft-start duration is controlled by a 60uA charge current which charges

CSS up to 4.0V. The Error Amplifier output is clamped low until SS/DEL reaches 1.1V. The Error Amplifier will then

regulate the converter’s output voltage to match the SS/DEL voltage less the 1.1V offset until it reaches the level

determined by the VID inputs. The PWRGD signal is asserted once the SS/DEL voltage exceeds 3.75V.

Five different faults will immediately cause SS/DEL to begin discharging and set the Fault Latch once SS/DEL is

below 3.75V;

1. VCC Under Voltage Lock Out

2. 5VUVL Under Voltage Lock Out

3. VID=11111x fault

4. Low Enable pin

5. Over Current Condition.

A delay is included if any fault condition occurs after a successful soft start sequence. This is required since

momentary faults can occur as part of normal operation due to load transients such as exciting an over-current

condition or a VID=11111x code while going through VID transitions. If any fault occurs during normal operation, the

SS/DEL capacitor will discharge through a 55uA current sink but will not set the fault latch immediately. If the fault

condition persists long enough for the SS/DEL capacitor to discharge below the 3.75V threshold of the delay

comparator, the Fault latch will be set pulling the Error Amplifier’s output low, inhibiting switching and de-asserting

the PWRGD signal. The SS/DEL capacitor is then discharged through a 6uA discharge current resulting in a long

hiccup duration.

The SS/DEL capacitor will continue to discharge until it reaches 0.265V where the fault latch is reset allowing a

normal soft start to occur. If a fault condition is again encountered during the soft start cycle, the fault latch will be

set without any delay and hiccup mode will begin. During hiccup mode the 10 to 1 charge to discharge ratio results

in a 9.1% hiccup mode duty cycle regardless of at what point a fault condition occurs.

The converter can be disabled if the SS/DEL pin is pulled below 0.9V.

Page 20 of 39

07/15/04

IR3093

7.4V

VCC

UVLO

(12V)

4.36V

5VUVL

3.75V

1.1V

SS/DEL

VOUT

PWRGD

OCP THRESHOLD

IOUT

START-UP

NORMAL OPERATION

OCP

DELAY

HICCUP OVER-CURRENT

PROTECTION

RE-START

AFTER OCP

CLEARS

POWER-DOWN

(5VUVL GATES

FAULT MODE)

(VOUT CHANGES DUE TO

LOAD AND VID CHANGES)

(VCC GATES

FAULT MODE)

Figure 8 – Operating Waveforms

Soft-start delay time tSSDEL is the time SS/DEL charged up to 1.1V. After that the error amplifier output is released

to allow the soft start. The soft start time tSS represents the time during which converter output voltage rises from

zero to VO. tSS can be programmed by CSS using equation (4).

6

I

_CHG*t_SS60*10 *t_SS

V_O

C_SS

(4)

V_O

Once CSS is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the delay

time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in equation (5), (6) and (7)

respectively.

C_SS*'V C_SS*1.1

t_SSDEL

t_OCDEL

t_VccPG

(5)

(6)

(7)

6

I_CHG

60*10

C_SS*'V C_SS*0.25

6

I_DISCHG

61*10

C_SS*'V C_SS*(3.75 ꢂV_Oꢂ1.1)

6

I_CHG

60*10

Over Current Protection (OCP)

The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the average

Current Sense Amplifier output plus VDAC voltage exceeds the OCSET voltage, the over-current protection is

triggered.

Page 21 of 39

07/15/04

IR3093

A delay is included if an over-current condition occurs after a successful soft-start sequence. This is required since

over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an over-

current fault occurs during normal operation, the Over Current Comparator will initiate the discharge of the

capacitor at SS/DEL but will not set the fault latch immediately. If the over-current condition persists long enough

for the SS/DEL capacitor to discharge below the 250mV offset of the delay comparator, the Fault latch will be set

pulling the Error Amplifier’s output low inhibiting switching in the phase ICs and de-asserting the PWRGD signal.

See Soft Start, Over-Current Fault Delay, and Hiccup Mode. The hiccup mode duty cycle of over current protection

is determined by the ratio of the charge to discharge current and is fixed at 9.1% for the ratio of 10 to 1.

The inductor DC resistance RL is utilized to sense the inductor current. The current limit threshold is set by a

resistor ROCSET connected between the OCSET and VDAC pins, as shown in Fig1. ILIMIT is the required over

current limit. IOCSET, the bias current of OCSET pin, is set by R_ROSCand is determined by the curve in this data

sheet. OCP need to satisfy the high temperature condition. RL_MAX and RL_ROOM are the inductor DCR at

maximum temperature TL_MAX and room temperature T_ROOM respectively, the maximum inductor DCR can be

calculated from Equation (8)

6

R_{L _ MAX} R_{L _ ROOM}ꢀ[1ꢁ 3850*10 ꢀ(T_{L_ MAX}ꢂT_ROOM)]

(8)

The current sense amplifier gain of IR3093 decreases with temperature at the rate of1400 PPM, which

compensates part of the inductor DCR increase. The minimum current sense amplifier gain at the maximum IC

temperature TIC_MAX is calculated from Equation (9).

6

G_{CS _ MIN} G_{CS _ ROOM}ꢀ[1ꢂ1400*10 ꢀ(T_{IC _ MAX}ꢂT_ROOM)]

(9)

ROCSET can be calculated by the following equation (10), where ¨I is the ripple current in each output inductor.

I_LIMIT'I

R_OCSET [(

ꢁ

)ꢀ R_{L _ MAX}]ꢀG_{CS _ MIN}/ I_OCSET

(10)

(11)

3

2

Voꢀ(Vin ꢂVo)

'I

LꢀVinꢀ fsw

Adaptive Voltage Positioning

Adaptive voltage positioning is needed to reduce output voltage deviations during load transients and power

dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in

Figure 8. Resistor RFB is connected between the Error Amplifier’s inverting input pin FB and the converter’s output

voltage. An internal current source whose value is programmed by the same external resistor that programs the

oscillator frequency, R_ROSC, pumps current out of the FB pin. The FB bias current develops a positioning voltage

drop across RFB which forces the converter’s output voltage lower to V(VDAC)-I(FB)* RFB to maintain a balance at

the Error Amplifier inputs. RFB is selected to program the desired amount of fixed offset voltage below the DAC

voltage.

The voltage at the VDRP pin is an average of three phase Current Sense Amplifiers and represents the sum of the

VDAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin

through the resistor. The Error Amplifier forces the voltage on the FB pin to equal VDAC through the power supply

loop therefore the current through RDRP is equal to (VDRP-VDAC) / RDRP. As the load current increases, the

VDRP voltage increases accordingly which results in an increase RFB current, further positioning the output

regulated voltage lower thus making the output voltage reduction proportional to an increase in load current. The

droop impedance or output impedance of the converter can thus be programmed by the resistor RDRP. The offset

and slope of the converter output impedance are independent of the VDAC voltage.

Page 22 of 39

07/15/04

IR3093

AMD specifies the acceptable power supply regulation window as ±50mV around their specified VID tables. VR-

10.0 specifies the VID table voltages as the absolute maximum power supply voltage. In order to have all three

DAC options, the OPTERON and ATHLON DAC output voltages are pre-positioned 50mV higher than listed in AMD

specs. During testing, a series resistor is placed between EAOUT and FB to cancel the additional 50mV out of the

DAC. The FB bias current, equal to IROSC, develops the 50mV cancellation voltage. Trimming the VDAC voltage

by monitoring V(EAOUT) with this 50mV cancellation resistor in circuit also trims out errors in the FB bias current.

The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can

be retrieved by subtracting the VDAC voltage from the VDRP voltage.

VDAC

CDAC

VDAC

ERROR AMPLIFIER

+

RDAC

VOSNS-

FB

-

IROSC

RCOMP

CCOMP

VDAC

EAOUT

CSINM3

CSINP3

X23.5

-

+

IROSC

VDRP BUFFER

+

IDRP RDRP

VDRP

CSINM2

CSINP2

-

- V(CSav g) +

+

CSINM1

CSINP1

-

+

VPOSITIONING

RFB

-

VOUT SENSE+

VOUT SENSE-

Figure 9 - Adaptive voltage positioning

A resistor RFB between FB pin and the converter output is used to create output voltage offset VO_NLOFST which is

the difference between VDAC voltage and output voltage at no load condition. An internal current source whose

value is programmed by the same external resistor that programs the oscillator frequency, R_ROSC, pumps current I_FB

out of the FB pin.

The VDRP pin is connected to the FB pin through the Adaptive Voltage Positioning Resistor RDRP. Adaptive voltage

positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. RFB

and RDRP are determined by (12) and (13) respectively, where RO is the required output impedance of the

converter.

V_{O _ NLOFST}

R_FB

(12)

I_FB

Page 23 of 39

07/15/04

IR3093

R_FBꢀ R_{L _ MAX}ꢀG_{CS _ MIN}

n ꢀ R_O

R_DRP

(13)

Lossless Average Inductor Current Sensing

Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor

and measuring the voltage across the capacitor. The equation of the sensing network is,

R_Lꢁ sL

1ꢁ sR_SC_S

1

v_C(s) v_L(s)

i_L(s)

1ꢁ sR_SC_S

Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time

constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the

voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense

resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of

inductor DC current, but affects the AC component of the inductor current.

The advantage of sensing the inductor current versus high side or low side sensing is that actual output current

being delivered to the load is obtained rather than peak or sampled information about the switch currents. The

output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in

series with the inductor, this is the only sense method that can support a single cycle transient response. Other

methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).

An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer

from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency

variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and

the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier

bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional

sources of peak-to-average errors.

Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCSX as

follows.

L R_L

C_CS

R_CSX

(14)

Inductor DCR Temperature Correction

If the Current Sense Amplifier temperature dependent gain is not adequate to compensate the inductor DCR TC, a

negative temperature coefficient (NTC) thermistor can be added. The thermistor should be placed close to the

inductor and connected in parallel with the feedback resistor, as shown in Figure 9. The resistor in series with the

thermistor is used to reduce the nonlinearity of the thermistor.

Page 24 of 39

07/15/04

IR3093

VDAC

ERROR AMPLIFIER

+

EAOUT

VOSNS-

FB

-

IROSC

VDRP BUFFER

+

Current

+ VDAC

RDRP

VDRP

-

VOUT SENSE+

RFB

RLINEAR

RNTC

Figure 10 - Temperature compensation of inductor DCR

Remote Voltage Sensing

To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects

directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to

a separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed

transients are fed directly into the Error Amplifier without delay.

Master-Slave Current Share Loop

Current sharing between phases of the converter is achieved by a Master-Slave current share loop topology. The

output of the Phase 1 Current Sense Amplifier sets the reference for the Share Adjust Error Amplifiers. Each

Share Adjust Error Amplifier adjusts the duty cycle of its respective PWM Ramp and to force its input error to zero

compared to the master Phase 1, resulting in accurate current sharing.

The maximum and minimum duty cycle adjust range of Ramps 2 & 3 compared to Ramp1 has been limited to a

minimum of 0.5x and a maximum of 2.0x typical (see Figure 3.). The crossover frequency of the current share loop

can be programmed with a capacitor at the SCOMPX pin so that the share loop does not interact with the output

voltage loop.

The SCOMPX capacitor is driven by a trans-conductance stage capable of sourcing and sinking 22uA. The duty

cycle of Ramps 2 & 3 inversely tracks the voltage on their SCOMPX pin; if V(SCOMP2) increases, Ramp2’s slope

will increase and the effective duty cycle will decrease resulting in a reduction in Phase 2’s output current. Due to

the limited 22uA source current, an SCOMPX pre-charge circuit has been included to pre-condition V(SCOMPX)

so that the duty cycle of Ramps 2 & 3 are equal to Ramp1 prior to any GATEHX high pulses. The pre-condition

circuit can source 450uA. The Equal Duty Cycle Comparator (see Block Diagram) activates a pre-charge circuit

when SS/DEL is less than 0.6V. The Error Amplifier becomes active enabling GATEH switching when SS/DEL is

above 1.1V.

Set BIASOUT voltage

BIASOUT pin provides 150mA open-looped regulated voltage for GATE drive bias, and the voltage is set by

SETBIAS through an external resistor Rset connecting between SETBIAS pin and ground. Bias current I_SETBIASis a

function of ROSC. Rset is chosen by equation (15). VFD in the equation is the forward voltage drop across the

Bootstrap diode.

Page 25 of 39

07/15/04

IR3093

V_BIASOUTꢁV_FD

RSET

(15)

I_SETBIAS

Compensation of the Current Share Loop

The crossover frequency of the current share loop should be at least one decade lower than that of the voltage

loop in order to eliminate the interaction between the two loops. A 22nF capacitor from SCOMP to LGND is good

for most of the applications. If necessary have a 1k resistor in series with the Csc to make the current loop a little

bit faster.

Compensation of Voltage Loop

The adaptive voltage positioning is used in the computer applications to meet the load line requirements. Like

current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the

double poles of the power stage, which make the voltage loop compensation much easier.

Resistors RFB and RDRP are chosen according to Equations (12) and (13), and the selection of compensation

types depends on the capacitors used. For the applications using Electrolytic, Polymer or AL-Polymer capacitors,

type II compensation shown in Figure 11 (a) is usually enough. While for the applications with only low ESR

ceramic capacitors, type III compensation shown in Figure 11 (b) is preferred.

CCP1

RFB

CFB

RCOMP

CCOMP

VO+

RCOMP

CCOMP

RFB1

FB

-

EAOUT

RFB

EAOUT

VO+

FB

VDAC

RDRP

-

+

VDRP

EAOUT

VDAC

RDRP

CDRP

+

VDRP

(a) Type II compensation

(b) Type III compensation

Figure 11 . Voltage loop compensation network

Type II Compensation

Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and

capacitor across the output inductors matches that of the inductor, the crossover frequency of the voltage loop can

be estimated by Equations (16), where CE and RCE are the equivalent capacitance and ESR of output capacitors

respectively and RLE is the equivalent resistance of inductor DCR.

R_DRP

(16)

f_C

2S *C_Eꢀ (G_CS* R_FBꢀ R_LEꢂ R_CE)

RCOMP and CCOMP have limited effect on the crossover frequency, and are used only to fine tune the crossover

frequency and transient load response. Choose the desired crossover frequency fc1 around fc estimated by

Equation (16) and determine RCOMP and CCOMP.

Page 26 of 39

07/15/04

IR3093

(2S ꢀ f_C1)²ꢀ L_EꢀC_Eꢀ R_FB

V_INꢀ F_M

R_COMP

(17)

(18)

10 ꢀ L_EꢀC_E

C_COMP

R_COMP

CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.

A ceramic capacitor between 10pF and 220pF is usually enough. In equation (17), VIN is the input voltage, FM is

the PWM comparator gain (refer to equation (25)).

Type III Compensation

Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and

capacitor across the output inductors matches that of the inductor, the crossover frequency of the voltage loop can

be estimated by Equations (19).

R_DRP

(19)

f_C

2S *C_EꢀG_CS* R_FBꢀ R_LE

Choose the desired crossover frequency fc1 around fc estimated by Equation (19). Select other components to

ensure the slope of close loop gain is -20dB/Dec around the crossover frequency. Choose resistor RFB1 according

to Equation (20), and determine CFB and CDRP from Equations (21) and (22).

1

2

R_FB1 R_FB

to

R_FB1 R_FB

(20)

(21)

2

3

1

C_FB

4S ꢀ f_C1ꢀ R_FB1

(R_FBꢁ R_FB1) ꢀC_FB

(22)

C_DRP

R_DRP

RCOMP and CCOMP have limited effect on the crossover frequency, and are used only to fine tune the crossover

frequency and transient load response. Determine RCOMP and CCOMP from Equations (23) and (24), where FM is

the PWM comparator gain defined by Equation (25).

(2S ꢀ f_C1)²ꢀ L_EꢀC_Eꢀ R_FB

R_COMP

(23)

(24)

V_Iꢀ F_M

10ꢀ L_EꢀC_E

C_COMP

R_COMP

V_O

(25)

F_M

V_I*V_RAMP

CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise.

A ceramic capacitor between 10pF and 220pF is usually enough.

Page 27 of 39

07/15/04

IR3093

DESIGN EXAMPLE

IR3093 Demo Board for VRD10.1 Application

Specifications:

Input Voltage: VI=12 V

DAC Voltage: VDAC=1.35 V

No Load Output Voltage Offset: VO_NLOFST=20 mV

Output Current: IO=101 A DC

Output Current Limit set point: ILIMIT=130 A

Output Impedance: RO=1m

VCC Ready to VCC Power Good Delay: tVccPG=0-10mS

Soft Start Time: tSS=2 mS

Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS

Power Stage Design

Control IC: IR3093

Phase Number: n=3

Switching Frequency: fSW=300 kHz

Output Inductors: L=0.25 uH, RL=0.65 mꢁ

Output Capacitors: C=0.007F, RCE=0.7 m

External Components of IR3093

Oscillator Resistor Rosc

Once the switching frequency is chosen, ROSC can be determined from the curve in the datasheet of

IR3093 data sheet. For switching frequency of 300 kHz per phase, Choose ROSC=30k

Soft Start Capacitor CSS

Calculate the soft start capacitor from the required soft start time 2mS.

6

3

I_CHG*t_SS

60*10 *2*10

6

C_SS

0.09*10 F

Choose CSS = 0.1 uF

3

V_O

1.35 ꢂ 20*10

With the selected Css value, we can calculate the following delay times:

The Over-Current fault latch delay time tOCDEL will be:

6

C_SS*'V

I_DISCHG

0.1*10 *0.25

t_OCDEL

0.4mS

6

61*10

The soft start delay time is

6

C_SS* 'V

0.1*10 *1.1

t_SSDEL

1.8mS

6

I_CHG

60*10

Page 28 of 39

07/15/04

IR3093

The power good delay time is

6

C_SS* 'V

0.1*10 *(3.75 ꢂ1.33 ꢂ1.1)

t_VccPG

2.2mS

6

I_CHG

60*10

VDAC Slew Rate Programming Capacitor CDAC and Resistor RDAC

From IR3093 data sheet, the sink current ISINK of VDAC pin corresponding to ROSC=30kꢁ LVꢁ ꢂꢃX$ꢄꢁ

Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew

rate.

6

I_SINK

85ꢀ10

C_VDAC

34nF

6

3

SR_DOWN2.5ꢀ10 /10

Choose CVDAC = 33nF

Calculate the programming resistor.

15

3.2ꢀ10

3.2*10

3.4

R_DAC 0.5ꢁ

0.5ꢁ

2

9

2

C_DAC

ꢃ33*10

ꢄ

In practice slightly adjust RDAC to get desired slew rate.

Over Current Setting Resistor ROCSET

According to the spec, the output current limit set point ILIMIT = 130A. The bias current IOCSET set by

R_ROSCis around 40uA. Assume the maximum temperature TL_MAX = 120 C, the room temperature

TROOM=25 C, so

3

6

R_{L _ MAX} 0.65*10 ꢀ[1ꢁ 3850*10 ꢀ(120 ꢂ 25)] 0.9m:

Assume maximum IC temperature TIC_MAX=110C, the minimum current sense amplifier gain can be

calculated from Equation (11).

6

G_{CS _ MIN} 23.5ꢀ[1ꢂ1400*10 ꢀ(110 ꢂ 25)] 21

Using Equation (12) and (13) to calculate ROCSET:

Voꢀ(Vin ꢂVo)

LꢀVinꢀ fsw

1.33ꢀ(12 ꢂ1.33)

A

'I

15.8

6

0.25ꢀ10 ꢀ12ꢀ300ꢀ10³

I_LIMIT

3

'I

2

130 15.8

)ꢀ R_{L _ MAX}]ꢀG_{CS _ MIN}/ I_OCSET [( )ꢀ0.9ꢀ10 ]ꢀ21/(40ꢀ10 ) 24.2k:

3

6

R_OCSET [(

ꢁ

3

2

Choose ROCSET = 25 kꢁ

No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP

The value of the internal current source current IFB in the curve is 42uA according to R_ROSC= 30kꢄ

Page 29 of 39

07/15/04

IR3093

3

6

V_{O _ NLOFST}

20*10

42*10

R_FB

476ꢄꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ&KRRVHꢁ5FB = 499ꢁꢁꢁꢁꢁꢁ

IFB

3

R_FBꢀ R_{L _ MAX}ꢀG_{CS _ MIN}

nꢀ R_O

499ꢀ0.9ꢀ10 ꢀ21

R_DRP

3.1k:

3

3ꢀ1ꢀ10

Choose RDRP = 3.09kꢁꢁꢁꢁꢁꢁꢁꢁ

Inductor Current Sensing Capacitor CCS and Resistors RCS1 and RCS2

Choose capacitor CCS = 0.22uF calculate RCS1

6

3

L R_L0.25*10 /0.65*10

C_CS

R_CS1

1.8k:

Choose RCS1=2k

6

0.22*10

Set BIASOUT voltage Resistor Rset

Bias current I_SETBIASis around 160uA in this case. Set VBIASOUT around 8V to be gate drive voltage of

MOSFETs.

V_BIASOUTꢁ 0.3

8 ꢁ 0.3

160ꢀ10

RSET

51.9k:

6

I_SETBIAS

Choose RSET=51.1k

Compensation of Voltage Loop

AL-Polymer output capacitors are used in the design, and the crossover frequency of the voltage loop

can be estimated as,

3.09*10³

R_DRP

f_C

28kHz

3

2S ꢀC_Eꢀ(G_CSꢀ R_FBꢀ R_LEꢂ R_CE)

2S ꢀ0.007ꢀ[23.5ꢀ499ꢀ(0.65*10 /3) ꢂ 0.7*10 ]

RCOMP and CCOMP are used to fine tune the crossover frequency and transient load response. Choose

the desired crossover frequency fc1 (=30kHz) and determine RCOMP and CCOMP.

V_O

V_IꢀV_RAMP12 ꢀ0.63

1.33

F_M

0.18

(2S ꢀ f_C1)²ꢀ L_EꢀC_Eꢀ R_FB

V_Iꢀ F_M

9

(2S ꢀ30ꢀ10³)²ꢀ(250ꢀ10 / 3)ꢀ0.007ꢀ 499

R_COMP

5k:

12ꢀ0.18

9

10 ꢀ L_EꢀC_E

10 ꢀ (250 ꢀ10 / 3) ꢀ0.007

5ꢀ10³

C_COMP

48nF

R_COMP

In practice, adjust RCOMP and CCOMP if need to get desired dynamic load response performance.

Page 30 of 39

07/15/04

IR3093

MathCAD file to estimate the power dissipation of the IC

this Mathcad file step by step shows how to estimate the power dissipation of IR3093 .

Initial Conditions:

No.of Phases:

n ꢅ 3

IC Supply Voltage:

, IC Supply Current(quiescent):

Vcc ꢅ 12 (V)

Icq ꢅ 38 (mA)

Total High side Driver VCCH supply current(quiescent):

Total Low side Driver VCCL supply Current(quiescent):

Iqh ꢅ 5 n (mA)

Iql ꢅ 5 n (mA)

Biasout Voltage:

Vbias ꢅ 7.5 (V)

Switching Frequency per phase:

Thermal Impedance of IC:

fsw ꢅ 300 (kHz)

o

( C/W)

T

ꢅ 27

JA

The data from the selected MOSFETs:

ControI FET IR6623, Number of Control FET per phase:

Control FET total gate charge:

Synchronous FET IR6620, Number of sync. FET per phase:

Sync FET total gate charge:

nc ꢅ 1

ns ꢅ 1

Qgc ꢅ 16 (nC)

Qgs ꢅ 45 (nC)

Power Dissipation:

The IC will have less power dissipation if using external gate driver supply. For the worst case estimation,

assuming using the bias regulator for all the gate drive supply voltage.

1. Quiescent Power dissipation

Total Quiescent Power Dissipation:

3

Pq ꢅ (Icq ꢁ Iqh ꢁ Iql) Vcc 10

2. The Power Loss to drive the gate of the MOSFETs

Pq 0.816 (W)

With the assumption of the low MOSFET gate resistances, most gate drive losses are dissipated in

the driver circuit.

3

9

ª

º

Pdrv ꢅ Vbias fsw 10 n (nc Qgc ꢁ ns Qgs) 10

¬

¼

Pdrv 0.412 (W)

3

9

Where the

term in the equation gives the total

Ig ꢅ fsw 10 n (nc Qgc ꢁ ns Qgs) 10

average bias current required to drive all the MOSFETs.

3. The bias regulator Power Loss to supply driving the MOSFETs

Preg ꢅ (Vcc ꢂ Vbias) Ig

Preg 0.247 (W)

4. Total Power Dissipation of the IC:

Pdiss ꢅ Pq ꢁ Pdrv ꢁ Preg

Pdiss 1.475 (W)

o

( C)

And the total Junction temperature rising is:

Pdiss T 39.82

JA

Page 31 of 39

07/15/04

IR3093

APPLICATION CIRCUIT - 3 PHASE OPTERON CONVERTER

1 H C C V

C N

3 L E T A G

3 L C C V

1 M N I S C

1 P N I S C

P V O

E L B A N E

S N S P V O

F E R V 5

5 D I V

L E S _ D I V

2 M N I S C

2 P N I S C

D G R W P

T U O S A I B

3 M N I S C

3 P N I S C

C C V

0 D I V

1 D I V

2 D I V

S A I B T E S

D N G L

2 9 0 3 U R I

Figure 12. 12V Control, 12V Power Opteron Converter

Page 32 of 39

07/15/04

IR3093

APPLICATION CIRCUIT - 3 PHASE VR10.X CONVERTER

1 H C C V

C N

3 L E T A G

3 L C C V

1 M N I S C

1 P N I S C

P V O

E L B A N E

S N S P V O

F E R V 5

5 D I V

L E S _ D I V

2 M N I S C

2 P N I S C

D G R W P

T U O S A I B

3 M N I S C

3 P N I S C

C C V

0 D I V

1 D I V

2 D I V

S A I B T E S

D N G L

2 9 0 3 U R I

Figure 13. 12V Control, 5V Power, VR10 Converter

Page 33 of 39

07/15/04

IR3093

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC. Refer to the schematic in Figure 6 – System Diagram.

x Dedicate at least one inner layer of the PCB as power ground plane (PGND).

x The center pad of IC must be connected to ground plane (PGND) using the recommended via pattern shown in

“Package Dimensions”.

x The IC’s PGND1, 2, 3 and LGND should connect to the center pad under IC.

x The following components must be grounded directly to the LGND pin on the IC using a ground plane on the

component side of PCB: CSS, RSC2, RSC3, RSET, CVCC and C5VREF. The LGND should only be connected to

ground plan on the center pad under IC

x Place the decoupling capacitors CVCC and CBIAS as close as possible to the VCC and VCCL1_2, VCCL3

pins. The ground side of CBIAS should not be connected to LGND and it should directly grounded through vias.

x The following components should be placed as close as possible to the respective pins on the IC: RROSC,

ROCSET, CDAC, RDAC, CSS, CSC2, RSC2, CSC3, RSC3, RSET.

x Place current sense capacitors CCS1, 2, 3 and resistors RCS1, 2, 3 as close as possible to CSINP1, 2, 3 pins

of IC and route the two current sense signals in pairs connecting to the IC. The current sense signals should be

located away from gate drive signals and switch nodes.

x Use Kelvin connections to route the current sense traces to each individual phase inductor, in order to achieve

good current share between phases.

x Place the input decoupling capacitors closer to the drain of top MOSFET and the source of the bottom

MOSFET. If possible, Use multiple smaller value ceramic caps instead of one big cap, or use low inductance type

of ceramic cap, to reduce the parasitic inductance.

x Route the high current paths using wide and short traces or polygons. Use multiple vias for connections

between layers.

x The symmetry of the following connections from phase to phase is important for proper operation:

- The Kelvin connections of the current sense signals to inductors.

- The gate drive signals from the IC to the MOSFETS.

- The polygon shape of switching nodes.

Page 34 of 39

07/15/04

IR3093

PCB AND STENCIL DESIGN METHODOLOGY

x

7x7

48 Lead

0.5mm pitch MLPQ

See Figures 14-16.

PCB Metal Design (0.5mm Pitch Leads)

1. Lead land width should be equal to nominal part lead width. The minimum lead to lead

spacing should be ꢁꢅꢄꢆPPꢁWRꢁPLQLPL]HꢁVKRUWLQJꢄ

2. Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension +

0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet,

and the inboard extension will accommodate any part misalignment and ensure a fillet.

3. Center pad land length and width should be = maximum part pad length and width. However,

the minimum metal to metal spacing should be ꢁꢅꢄꢇꢈPPꢁꢉꢆꢁR]ꢄꢁ&RSSHUꢀꢁꢁꢅꢄꢆꢊPPꢁIRUꢁꢊꢁR]ꢄꢁ

Copper and ꢁꢅꢄꢇPPꢁIRUꢁꢇꢁR]ꢄꢁ&RSSHUꢋ

4. Sixteen 0.30mm diameter vias shall be placed in the pad land spaced at 1.2mm, and

connected to ground to minimize the noise effect on the IC, and to transfer heat to the PCB.

PCB Solder Resist Design (0.5mm Pitch Leads)

1. Lead lands. The solder resist should be pulled away from the metal lead lands by a minimum

of 0.060mm. The solder resist mis-alignment is a maximum of 0.050mm and it is

recommended that the lead lands are all NSMD. Therefore pulling the S/R 0.060mm will

always ensure NSMD pads.

2. The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist

is completely removed from between the lead lands forming a single opening for each “group”

of lead lands.

3. At the inside corner of the solder resist where the lead land groups meet, it is recommended to

provide a fillet so a solder resist width of ꢁꢅꢄꢇꢈPPꢁUHPDLQVꢄ

4. Land Pad. The land pad should be SMD, with a minimum overlap of the solder resist onto the

copper of 0.060mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is

allowable to have the solder resist opening for the land pad to be smaller than the part pad.

5. Ensure that the solder resist in-between the lead lands and the pad land is ꢁꢅꢄꢇꢃPPꢁGXHꢁWRꢁ

the high aspect ratio of the solder resist strip separating the lead lands from the pad land.

6. The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm

larger than the diameter of the via.

Stencil Design (0.5mm Pitch Leads)

1. The stencil apertures for the lead lands should be approximately 80% of the area of the lead

lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts.

Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should

not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable

solder release.

2. The stencil lead land apertures should therefore be shortened in length by 80% and centered

on the lead land.

3. The center land pad aperture should be striped with 0.25mm wide openings and spaces to

deposit approximately 50% area of solder on the center pad. If too much solder is deposited

on the center land pad the part will float and the lead lands will be open.

4. The maximum length and width of the center land pad stencil aperture should be equal to the

solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting

the center land to the lead lands when the part is pushed into the solder paste.

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IR3093

Figure 14. PCB metal and solder resist.

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Figure 15. PCB metal and component placement.

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IR3093

Figure 16. Stencil design.

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IR3093

PACKAGE DIMENSIONS

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information

www.irf.com

Page 39 of 39

07/15/04


型号：	IR3093MPBF
厂家：	Infineon
描述：	暂无描述稳压器开关式稳压器或控制器电源电路开关式控制器
文件：	总39页 (文件大小：695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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