IR3094MPBF [INFINEON]
3 PHASE PWM CONTROLLER FOR POINT OF LOAD; 3相PWM控制器,用于负载点![IR3094MPBF](http://pdffile.icpdf.com/pdf1/p00094/img/icpdf/IR3094_495491_icpdf.jpg)
型号: | IR3094MPBF |
厂家: | ![]() |
描述: | 3 PHASE PWM CONTROLLER FOR POINT OF LOAD |
文件: | 总29页 (文件大小:608K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Data Sheet No. PD 94716
IR3094PBF
3 PHASE PWM CONTROLLER FOR POINT OF LOAD
DESCRIPTION
The IR3094 Control IC provides a full featured, cost effective, single chip solution to offers a compact,
efficient solution for high current POL converters. Control and 3 Phase Gate Drive functions are integrated
into a single space-saving IC.
FEATURES
x
0.85V Reference Voltage
3A GATELX Pull Down Drive Capability
Programmable 100KHz to 540KHz oscillator
Programmable Voltage Positioning (can be disabled)
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates up to 16V converter input with 7.5V Under-Voltage Lockout
4.36V Under-Voltage Lockout threshold for gate driver voltage
Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage
Enable Input
OVP Flag Output detects high side fet short at powerup
Separate OVP sense line to sense the output voltage and latched OVP with protection
Inductor DCR sensing for current sensing will support up to 5.1V output applications
Available 48L MLPQ package
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ORDERING INFORMATION
Device
Order Quantity
IR3094MTRPBF
IR3094MPBF
3000 per Reel
100 piece strips
PACKAGE INFORMATION
NC
NC
GATEH1
PGND1
GATEL1
VCCL1_2
5VUVL
GATEL2
PGND2
GATEH2
VCCH2
VCCH3
GATEH3
PGND3
48L MLPQ
ROSC
VOSNS-
OCSET
VREF
VDRP
FB
EAOUT
SS/DEL
SCOMP2
SCOMP3
(7 x 7 mm Body)
IR3094
48LDMLPQ
JA = 27oC/W
Page 1 of 29
09/26/05
IR3094PBF
PIN DESCRIPTION
PIN# PIN SYMBOL
PIN DESCRIPTION
Not connected
Not connected
1
2
3
4
NC
NC
ROSC
VOSNS-
Connect a resistor to VOSNS- to program oscillator frequency, OCSET and STBIAS bias currents.
Remote Sense Input. Connect to ground at the load.
Programs the hiccup over-current threshold through an external resistor tied to VREF and an internal current
source. The bias current is a function of ROSC.
5
6
OCSET
VREF
0.85V Reference voltage. Current Sensing and Over Current Protection are referenced to this pin. An
external RC network tied to VOSNS- is needed for the compensation.
Buffered average current information. Connect an external resistor to FB to program converter output.
Inverting input to the Error Amplifier.
Output of the Error Amplifier.
7
8
9
VDRP
FB
EAOUT
Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to
LGND to program the timing.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 2 is forced to match phase 1’s current.
Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 3 is forced to match phase 1’s current.
10
11
12
SS/DEL
SCOMP2
SCOMP3
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LGND
SETBIAS
VCC
Local Ground and IC substrate connection.
External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.
Power for internal circuitry and source for BIASOUT regulator.
Non-inverting input to the Phase 3 Current Sense Amplifier.
Inverting input to the Phase 3 Current Sense Amplifier.
150mA open-looped regulated voltage set by SETBIAS for GATE drive bias.
Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.
Non-inverting input to the Phase 2 Current Sense Amplifier.
Inverting input to the Phase 2 Current Sense Amplifier.
Not connected
Power for Phase 3 Low-Side Gate Driver.
Phase 3 Low-Side Gate Driver Output and input to GATEH3 non-overlap comparator.
Return for Phase 3 Gate Drivers.
Phase 3 High-Side Gate Driver Output and input to GATEL3 non-overlap comparator.
Power for Phase 3 High-Side Gate Driver.
CSINP3
CSINM3
BIASOUT
PWRGD
CSINP2
CSINM2
NC
VCCL3
GATEL3
PGND3
GATEH3
VCCH3
VCCH2
GATEH2
PGND2
GATEL2
Power for Phase 2 High-Side Gate Driver.
Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.
Return for Phase 2 Gate Drivers.
Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.
Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under
voltage condition initiates Soft Start.
32
5VUVL
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VCCL1_2
GATEL1
PGND1
GATEH1
VCCH1
NC
CSINM1
CSINP1
OVP
ENABLE
OVPSNS
5VREF
NC
Power for Phase 1 and 2 Low-Side Gate Drivers.
Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.
Return for Phase 1 Gate Drivers.
Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.
Power for Phase 1 High-Side Gate Driver.
Not connected
Inverting input to the Phase 1 Current Sense Amplifier.
Non-inverting input to the Current Sense Amplifier.
Output that drives high during an Over-Voltage condition.
Enable Input. A logic low applied to this pin puts the IC into Fault mode.
Dedicated output voltage sense pin for Over Voltage Protection.
Decoupling for internal voltage reference rail.
Not connected
NC
NC
Not connected
Not connected
NC
Not connected
Page 2 of 29
09/26/05
IR3094PBF
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature……………..0oC to 150oC
Storage Temperature Range………………….-65oC to 150oC
PIN
3
4
5
6
7
8
9
NAME
ROSC
VOSNS-
OCSET
VDAC
VMAX
20V
0.5V
20V
20V
20V
20V
10V
20V
20V
20V
n/a
20V
20V
20V
20V
20V
20V
20V
20V
n/a
20V
20V
0.3V
30V
30V
30V
30V
0.3V
20V
20V
20V
20V
0.3V
30V
30V
n/a
VMIN
-0.3V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
ISOURCE
1mA
10mA
1mA
1mA
25mA
1mA
5mA
1mA
1mA
1mA
50mA
1mA
1mA
1mA
1mA
450mA
1mA
1mA
1mA
n/a
n/a
ISINK
1mA
1mA
1mA
1mA
5mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
500mA
1mA
1mA
1mA
20mA
1mA
1mA
n/a
VDRP
FB
EAOUT
SS/DEL
SCOMP2
SCOMP3
LGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SETBIAS
VCC
CSINP3
CSINM3
BIASOUT
PWRGD
CSINP2
CSINM2
NC
VCCL3
GATEL3
PGND3
GATEH3
VCCH3
VCCH2
GATEH2
PGND2
GATEL2
5VUVL
VCCL1_2
GATEL1
PGND1
GATEH1
VCCH1
NC
-0.3V
-0.3V
-0.3V
-0.3V
n/a
-0.3V
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
-0.3V DC, -2V for 100ns
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
-0.3V
n/a
-0.3V DC, -2V for 100ns
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
-0.3V
-0.3V
n/a
n/a
-0.3V DC, -2V for 100ns
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
-0.3V
n/a
-0.3V DC, -2V for 100ns
3A for 100ns, 200mA DC
-0.3V
-0.3V
1mA
n/a
1mA
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
-0.3V DC, -2V for 100ns
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
-0.3V
n/a
-0.3V DC, -2V for 100ns
3A for 100ns, 200mA DC
3A for 100ns, 200mA DC
-0.3V
n/a
n/a
n/a
n/a
1mA
1mA
1mA
1mA
1mA
20mA
CSINM1
CSINP1
OVP
ENABLE
OVPSNS
5VREF
20V
20V
20V
20V
20V
10V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
1mA
1mA
1mA
1mA
1mA
10mA
Page 3 of 29
09/26/05
IR3094PBF
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 8.0 VCC 16V, 4V VCCLX 14V,
4V VCCHX 28V, CGATEHX =3.3nF, CGATELX =6.8nF, 0oC TJ 125 oC
PARAMETER
VREF Reference
TEST CONDITION
MIN
TYP
MAX
UNIT
Sink Current
RROSC = 47kꢀꢁ95()=OCSET
RROSC = 47kꢀꢁ95()=OCSET
45
48
53
56
61
64
PA
PA
Source Current
Connect FB to EAOUT, Measure
V(EAOUT)-V(VOSNS-). Applies to
-0.3V<VOSNS-<0.3V.
System Reference Voltage
Error Amplifier
0.8415
0.85
0.8585
V
Connect FB to EAOUT, Measure
V(EAOUT)-V(VREF). Applies to
-0.3V<VOSNS-<0.3V. Note 1
Input Offset Voltage
-5
-1
3
mV
UVL FB Bias Current
UVL Head Room
DC Gain
40
1.2
90
4
90
2
150
2.5
uA
V
Note 1
100
7
105
dB
Gain-Bandwidth Product
Slew Rate
Note 1
MHz
V/Ps
PA
mA
V
Note 1, 50mV FB signal
1.25
430
1.1
4.9
50
Source Current
Sink Current
300
.75
4.5
600
1.5
5.3
200
Max Voltage
Min Voltage
mV
VDRP Buffer Amplifier
V(VDRP) – V(REF) with
CSINMX=CSINPX=0. Note 1.
Positioning Offset Voltage
-125
0
125
mV
Output Voltage Range
Source Current
Sink Current
0.2
4
3.75
20
V
8
mA
PA
200
300
650
Oscillator
Switching Frequency
RROSC = 47k
160
102
200
120
240
138
kHz
°
Sequence: GATEH1-GATEH2-
GATEH3
Phase Shift
Page 4 of 29
09/26/05
IR3094PBF
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
BIASOUT Regulator
SETBIAS Bias Current
Set Point Accuracy
RROSC = 47k
94
0
103
117.5
0.55
PA
V
V(SETBIAS)-V(BIASOUT) @ 100mA
0.25
I(BIASOUT)=100mA,Threshold when
V(SETBIAS)-V(BIASOUT)=0.45V
BIASOUT Dropout Voltage
1.2
1.8
2.5
V
BIASOUT Current Limit
150
250
500
mA
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
0.8
1.1
1.8
V
Charge Current
30
3.5
25
60
6
90
9
PA
PA
PA
Hiccup Discharge Current
OC Discharge Current
55
70
Charge/Discharge Current
Ratio
9
10
13
PA/PA
Charge Voltage
3.8
4.0
4.2
V
Delay Comparator Threshold
Relative to Charge Voltage
180
245
310
mV
Discharge Comparator
Threshold
170
265
350
mV
Over-Current Comparator
V(OCSET)-V(VREF),
CSINM=CSINP1=CSINP2=CSINP3,
Note 1.
Input Offset Voltage
-125
0
125
mV
OCSET Bias Current
Max OCSET Set Point
RROSC = 47k
23.5
3.9
27
29.4
PA
V
Under-Voltage Lockout
VCC Start Threshold
VCC Stop Threshold
VCC Hysteresis
7.0
6.5
7.5
7.0
8.0
7.5
V
V
Start – Stop
400
4.05
3.92
100
500
4.36
4.17
200
700
4.60
4.40
250
mV
V
5VUVL Start Threshold
5VUVL Stop Threshold
5VUVL Hysteresis
V
Start – Stop
mV
PWRGD Output
Output Voltage
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
150
0
400
10
mV
Leakage Current
PA
Page 5 of 29
09/26/05
IR3094PBF
PARAMETER
Enable Input
TEST CONDITION
MIN
TYP
MAX UNIT
Threshold
Referenced to VOSNS-
1.3
5
2.4
1.5
10
3.0
1.7
20
3.7
V
k
V
Input Resistance
Pull-up Voltage
Gate Drivers
GATEH Rise Time
VCCHX = 8V, Measure 1V to 7V transition
time. Note 1.
VCCHX = 8V, Measure 7V to 1V transition
time. Note 1.
VCCLX= 8V, Measure 1V to 7V transition
time. Note 1.
VCCLX= 8V, Measure 7V to 1V transition
time. Note 1.
Measure VCCLX– GATELX or VCCHX –
GATEHX, Note 1
Measure GATELX or GATEHX, Note 1
VCCHX = VCCLX= 8V, Measure the time
from GATELX falling to 1V to GATEHX
rising to 1V. Note 1.
VCCHX = VCCLX= 8V, Measure the time
from GATEHX falling to 1V to GATELX
rising to 1V. Note 1.
25
25
50
30
0
50
50
ns
ns
ns
ns
V
GATEH Fall Time
GATEL Rise Time
GATEL Fall Time
High Voltage (AC)
Low Voltage (AC)
90
60
0.5V
0
25
0.5V
50
V
ns
GATEL low to GATEH high
delay
10
10
20
GATEH low to GATEL high
delay
25
35
50
50
ns
Disable Pull-Down Current
GATHX or GATELX=2V with VCC = 0V.
Measure Gate pull-down current
PA
PWM Comparator
Propagation Delay
Note1
100
150
4
0.9
65
ns
V
V
Common Mode Input Range
Internal Ramp Start Voltage
Internal Ramp Amplitude
0.44
35
0.6
50
mV /
%DTC
Current Sense Amplifier
CSINPX Bias Current
CSINM2,3 Bias Current
CSINM1 Bias Current
Phase 2 and 3 Input Current
Offset Ratio
-1
-1
-2
0
0
-0.5
1
1
1
1
PA
PA
PA
PA/PA
Phase 1 Input Current Offset
Ratio
0.5
1.7
4
PA/PA
Average Input Offset Voltage
(VDRP-VREF)/GAIN with CSINX=0. Note1
Monitor I(SCOMPX), Note1.
-5
-5
22.5
19
-1
-25
-0.2
0
0
24
20.9
0
5
5
25.5
22
1
mV
mV
V/V
V/V
V/V
mV
V
Offset Voltage Mismatch
Gain at TJ = 25 oC
Gain at TJ = 125 oC
Gain Mismatch
Differential Input Range
Common Mode Input Range
Note 1.
75
5.5
Page 6 of 29
09/26/05
IR3094PBF
PARAMETER
TEST CONDITION
MIN
-5
TYP
MAX
UNIT
mV
Share Adjust Error Amplifier
Input Offset Voltage
Note 1
0
5
MAX Duty Cycle Adjust Ratio
MIN Duty Cycle Adjust Ratio
Transconductance
Compare Duty Cycle to GATEH1
Compare Duty Cycle to GATEH1
Note 1
1.5
0.6
100
16
2.0
0.5
200
22
300
28
PA/V
PA
SCOMPX Source/Sink Current
SCOMPX Precondition and
GATELX Release Threshold
V(FB)
0.6
0.67
0.74
V
SCOMP precondition current
Duty Cycle Match at Startup
0% Duty Cycle Comparator
Threshold Voltage
160
-7
360
-1
560
7
PA
%
Compare Duty Cycle to GATEHX
Below Internal Ramp1 Start Voltage
-25
25
75
mV
ns
Propagation Delay
VCCLX= 8V. Step EAOUT from .8V to
.3V and measure time to GATELX
transition to < 7V.
200
400
OVP
Comparator Threshold
Compare to V(VREF)
120
0.8
150
1.1
200
1.8
mV
V
Power-up Headroom for OVP
Flag
VCC=OVPSNS where V(OVP)>0.5V.
Same for 5VUVL=OVPSNS.
OVPSNS Threshold at Power- VCC=2V, V(OVP) >0.5V. Same for
0.3
0.48
0.60
0.85
0.95
V
V
up
V(5VUVL)=2V.
SS/DEL Power-up Clear
Threshold
VCC=12V, V(OVPSNS)=1V,
VREF=1.6V, where OVP<0.5V
0.35
VCCLX= 8V. V(EAOUT)=0V. Step
OVPSNS 540mV + V(VREF). Measure
time to GATELX transition to >1V.
Note 1.
Propagation Delay
150
350
650
ns
OVP Source Current
V(OVP)=0.5V, VCC=1.8V, 5VUVL=0V
OVP to LGND
10
30
75
60
PA
k
OVP Pull Down Resistance
100
1.1
1.5
I(OVP)=10uA, V(VCC) or V(5VUVL)-
V(OVP), VCC=1.8V
OVP High Voltage
0.4
0.70
-3.0
V
OVPSNS Bias Current
5VREF
-6.0
uA
Short Circuit Current
Supply Voltage
20
45
5
60
mA
V
I(5VREF)=0A
4.5
5.5
General
VCC Supply Current
VOSNS- Current
V(VCC)=16V
28.5
0.6
3
35
0.8
5
40.5
1.2
7
mA
mA
mA
mA
uA
-0.3V VOSNS- 0.3V
V(VCCHX)=28V, V(VCCL3)=14V
V(VCCL1_2)=14V
VCCHX and VCCL3 Current
VCCL1_2 Supply Current
5VUVL Supply Current
6
10
200
17
V(5VUVL)=5V, no OVP condition
100
400
%VRE
F
Non_Sync to Sync Threshold
70.6
77.7
87
Note 1: Guaranteed by design, but not tested in production
Note 2: VREF Output is trimmed to compensate for Error Amp input offsets errors
Page 7 of 29
09/26/05
IR3094PBF
TYPICAL OPERATING CHARACTERISTICS
I(VD) Sink and Source Currents vs. ROSC
REF
I(OCSET) Current vs. ROSC
90
80
70
60
50
40
30
20
10
0
180
160
140
120
100
80
I(VD) Source
REF
Current
I(OCSET)
I(VD) Sink Current
REF
60
40
20
0
10
20
30
40
50
60
70
80
90
100 110 120
10 20 30 40 50 60 70 80 90 100 110 120 130
ROSC (kOhm)
ROSC in Kohms
I(SETBIAS) vs. ROSC
Oscillator freq vs. ROSC
320
300
280
260
240
220
200
180
160
140
120
100
80
500
450
400
350
300
250
200
150
100
50
60
40
20
0
10
20 30
40 50
60 70
80 90 100 110 120
10
20
30
40
50
60
70
80
90
100 110 120
ROSC (kOhm)
ROSC (kOhm)
Peak High side Gate drive current vs. L
oad
Frequency and Bias Current Accuracy vs. ROSC (includes
temperature)
capacitance
2.000
1.900
1.800
1.700
1.600
1.500
1.400
1.300
1.200
1.100
1.000
6
5
4
3
2
1
Frequency
VREF Sink
VREF Source
OCSET
I(RISE)
I(FALL)
SETBIAS
1
2
3
4
5
6
7
8
9
10
10
20
30
40
50
60
70
80
90
100
C(GATEHX) in nF
ROSC (kOhm)
Page 8 of 29
09/26/05
IR3094PBF
Peak Low side Gate drive current vs. Laod
oad
capacitance
3.250
3.000
2.750
2.500
2.250
2.000
1.750
1.500
1.250
1.000
I(RISE)
I(FALL)
1
2
3
4
5
6
7
8
9
10
C(GATELX) in nF
Error Amplifier Frequency Response
180
100
0
93dB DC gain
88° Phase Margin
3.1MHz Crossover
-100
-180
1.0Hz
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz
10Hz
DB(V(comp))
P(V(comp))
Frequency
Page 9 of 29
09/26/05
STARTUP OVP Comparator
+
FB
EAOUT
OVPSNS
ROSC
OVP
VCC
75U
75U
VCCH1
-
60k
ON
VCC
5VUVL
DRIVE
GATEHI
OL_OUT
LGND
UVL
0.48V
IN
GATEH1
RESET DOMINANT
-
CLK1
OL_IN
PGND
GateHI
4 X IROSC
S
+
OVP Comparator
Q
+
PWM COMPARATOR
-
SETBIAS
BIASOUT
5VUVL
PGND1
1.243
QB
7.5V START
7.0V STOP
-
R
OVP LATCH
+
RSFF
150mV
VDAC
S
VCCL1_2
IROSC
Q
DRIVE
IROSC/2
QB
R
OL_OUT
GATELO
OL_IN
CLK1 CLK1
CLK2 CLK2
CLK3 CLK3
UVL
SET DOMINANT
IN
GATEL1
9p
-
PGND
GateLO
0.6V
+
4.36V START
4.17V STOP
Error_Amp
DISABLE
-
Oscillator
+
+
+
VCCH2
-
PWRGD
0% DUTY CYCLE
0.575V
DRIVE
GATEHI
OL_OUT
IN
GATEH2
RESET DOMINANT
CLK2
OL_IN
S
Q
PWM COMPARATOR
PGND
GateHI
OVER CURRENT
PGND2
OCSET
-
-
QB
-
R
IAVE
+
+
RSFF
+
IROSC
SYNC LATCH
DRIVE
DELAY
S
0.6V
IROSC/2
OL_OUT
GATELO
+
OL_IN
Q
+
-
QB
R
CO1
PRESET
IN
245mV
+
GATEL2
-
9p
PGND
GateLO
CO2
0.6V
SET DOMINANT
-
0 TO IROSC*3/4
Share Adjust Error Amp
4V
SoftStart_Clamp
1.1V
OFF
60U
0.75*VDAC
SCOMP2
+
-
H
FORCES IROSC/2
SS
VCCH3
6U
FAULT LATCH
RESET DOMINANT
ON
DRIVE
U37
S
Q
GATEHI
OL_OUT
55U
CLK3
PWM COMPARATOR
S
R
IN
GATEH3
Q
IAVE
OL_IN
-
QB
R
Discharge Comparator
OR4
3V
PGND
GateHI
SET DOMINANT
+
-
PGND3
VCCL3
RSFF
10k
+
CO3
CO2
CO1
0.265V
IROSC
summer
summer
summer
REF BUFFER
DRIVE
ENABLE
OL_OUT
GATELO
OL_IN
-
CO1
CO3
PRESET
9p
+
-
-
IN
+
GATEL3
0.6V
PGND
GateLO
+
IROSC
0 TO IROSC*3/4
X23.5
X23.5
X23.5
Share Adjust Error Amp
0.85V
1.5V
SCOMP3
INTERNAL
REFERENCE
+
-
VDRP
5VREF
VOSNS-
VREF
CSINM3
CSINP3
CSINM2
CSINP2
CSINM1
CSINP1
IR3094PBF
PWM Operation
The IR3094 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing
edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage
control loop. The PWM block diagram of the IR3094 is shown in Figure 2.
IROSC
U30
RSFF
CLK1
S
Q
CLK2 CLK2
CLK3 CLK3
PWM COMPARATOR
-
QB
R
+
RESET DOMINANT
VIN
OSCBLOCK
OVP LATCH
GATEH1
GATEL1
OVP SET
IROSC/2
S
Q
1
2
QB
R
OVP RESET
VREF
RCS1 CCS1
9p
0.6V
CDAC
RDAC
VDAC
ERROR AMPLIFIER
+
+
VOSNS-
FB
-
-
0% DUTY CYCLE
VIN
RSFF
0.575V
CLK2
GATEH2
GATEL2
S
VOUT SENSE+
VOUT+
Q
CCOMP
IROSC
PWM COMPARATOR
-
QB
1
2
R
RCOMP
+
RESET DOMINANT
EAOUT
VDRP
COUT
RCS2
CCS2
IROSC
VOUT-
VDRP BUFFER
+
RDRP
VOUT SENSE-
-
Share Adjust Error Amp
+
9p
0.6V
RFB
0 TO IROSC*3/4
-
SCOMP2
CSC2
RSC2
VIN
1
RSFF
CLK3
GATEH3
GATEL3
S
Q
PWM COMPARATOR
EAOUT
-
QB
R
2
+
RESET DOMINANT
RCS3
CCS3
IROSC
Share Adjust Error Amp
+
9p
0.6V
0 TO IROSC*3/4
-
SCOMP3
VDAC
CSC3
RSC3
CSINM3
CSINP3
X23.5
X23.5
X23.5
-
+
VDAC
VDAC
CSINM2
CSINP2
-
+
CSINM1
CSINP1
-
+
Figure 2 – PWM Block Diagram
Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to
increase, the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 9pf
capacitor is charged by a current source that proportional to the switching frequency resulting in a ramp rate of
50mV per percent duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the
internal ramp amplitude is typically 500mV from the starting point (or floor) to the crossing of the EAOUT control
voltage. When the PWM ramp voltage exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns
off the high side driver, turns on the low side driver, and discharges the PWM ramp to 0.6V until the next clock
pulse.
Page 11 of 29
09/26/05
IR3094PBF
50% INTERNAL OSCILLATOR RAMP
DUTY CYCLE
CLK1
CLK2
CLK3
RAMP3 MIN DUTY
CYCLE ADJUST
RAMP3 MAX DUTY
CYCLE ADJUST
RAMP3
FIXED RAMP1
RAMP2
EAOUT
0.6V
RAMP1 SLOPE
= 50mV / % DC
THE SHARE ADJUST ERROR AMPLIFIER CAN
CHANGE THE PULSE WIDTH OF RAMPS
0.5 RAMP1 TO 2.0 RAMP1 TO FORCE
CURRENT SHARING.
2
& 3 FROM
x
X
Figure 3 – 3 Phase Oscillator and PWM Waveforms
The RSFF is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements.
Body BrakingTM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW = [L x (IMAX - IMIN)] / Vout
(1)
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODY
DIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is
now;
TSLEW = [L x (IMAX - IMIN)] / (Vout + VBODY DIODE
)
(2)
Page 12 of 29
09/26/05
IR3094PBF
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished
through the “0% Duty Cycle Comparator”. If the Error Amplifier’s output voltage drops below 0.575V, this
comparator turns off the low side gate driver.
Figure 4 depicts PWM operating waveforms under various conditions
CLK1
PULSE
EAOUT
PWM
Ramp1
0.6V
0.575V
GATEH1
GATEL1
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
STEADY-STATE
OPERATION
INCREASE
Figure 4 – PWM Operating Waveforms
Current Sense Amplifier
A high speed differential current sense amplifier is shown in Figure 5. Its gain decreases with increasing
temperature and is nominally 24 at 25ºC and 20.9 at 125ºC (-1400 ppm/ºC). This reduction of gain tends to
compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the IR3094 IC junction is hotter than
the inductors these two effects tend to cancel such that no additional temperature compensation of the load line is
required.
The current sense amplifier can accept positive differential input up to 75mV and negative up to -25mV before
clipping. The output of the current sense amplifier is summed with the VREF voltage which is used for over current
protection, voltage positioning and current sharing.
vL
L
RL
iL
Vo
Rs
Cs
vc
Co
CSA
CO
Figure 5 – Inductor Current Sensing and Current Sense Amplifier
Page 13 of 29
09/26/05
IR3094PBF
Power-up in Non-Synchronous Mode
The SYNC LATCH is set by either a UVLO or a Low Enable fault at the beginning of the power-up cycle, keeping all
three low side gate drivers low. The SYNC LATCH is then reset once the FB pin exceeds 78% of VREF to release
the low side gate drive control to the Error-Amp. SCOMP preconditioning is also released at this time. Non-
Synchronous startup helps preventing negative inductor current until current sharing is stabilized.
VCC Under Voltage Lockout (UVLO)
The VCC UVLO function monitors the IR3094’s VCC supply pin and ensures enough voltage is available to power
the internal circuitry. During power-up the fault latch is reset when VCC exceeds 7.5V and all other faults are
cleared. The fault latch is set when VCC drops below 7.0V and SS/DEL is below 3.75V.
5VUVL Under Voltage Lockout (5VUVL)
The 5VUVL function is provided for converters using a separate voltage supply other than VCC for gate driver bias.
The 5VUVL comparator prevents operation by discharging SS/DEL below 3.75V to force EAOUT low. The 5VUVL
comparator has an OK threshold of 4.36V ensuring adequate gate drive voltage is present and a fault threshold of
4.17V.
Power Good Output
The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During
soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.75V. The
PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in
operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage
regulation within the design limits can logically be assured however, assuming no component failure in the system.
Tri-State Gate Drivers
The GATELX drivers can pull down up to 3.5A peak current and source up to 1.5A. The GATEHX drivers can
source and sink up to 1.5A peak current. An adaptive non-overlap circuit monitors the voltage on the GATEHX and
GATELX pins to prevent MOSFET shoot-through current while minimizing body diode conduction.
The Error Amplifier output of the Control IC drives low in response to any fault condition such as VCC input under
voltage or output overload. The 0% duty cycle comparator detects this and drives both gate outputs low. This tri-
state operation prevents negative inductor current and negative output voltage during power-down.
The Gate Drivers revert to a high impedance “off” state at VCCLX and VCCHX supply voltages below the normal
operating range. An 80kꢁUHVLVWRUꢁLVꢁFRQQHFWHGꢁDFURVVꢁWKHꢁ*$7(;ꢁDQGꢁ3*1';ꢁSLQVꢁWRꢁSUHYHQWꢁWKHꢁ*$7(;ꢁYROWDJHꢁ
from rising due to leakage or other cause under these conditions.
Over Voltage Protection (OVP)
The output Over-Voltage Protection comparator monitors the output voltage through the OVPSNS pin, the positive
remote sense point. If OVPSNS exceeds VREF plus 150mV, the OVP LATCH will be set. This will set the fault
latch immediately pulling the Error Amplifier’s output low, reset the PWM latch to fully turn-off the high side
MOSFETs and turn-on the low side MOSFETs within approximately 350ns. The low side MOSFETs will remain ON
until the OVP LATCH is reset by recycling VCC. OVPSNS exceeding VREF by 150mV also activates 75uA sources
on the OVP pin. The lower MOSFETs alone can not clamp the output voltage however an SCR or MOSFET could
be triggered with the OVP pin to prevent processor damage.
If powering up with a high side MOSFET short, the OVP flag is activated and the OVP LATCH is set with as little
VCC supply voltage as possible. The OVPSNS pin is compared against both VCC and 5VUVL for OVP conditions
at power-up. VCC is monitored for conversion off 12V, 5VUVL is monitored for conversion off 5V. The OVP pin
flags a voltage greater than 0.48V with supply voltages as low as 1.0V. This headroom voltage varies inversely with
temperature. An external comparator can be used to disable the silver box, activate a crowbar, or supply source.
Page 14 of 29
09/26/05
IR3094PBF
APPLICATIONS INFORMATION
OVP
ENABLE
VOUT+
VIN
CCS1
2
RCS1
1
C5VREF
CBST1
L1
RROSC
RFB
NC
NC
GATEH1
PGND1
GATEL1
VCCL1_2
5VUVL
GATEL2
PGND2
GATEH2
VCCH2
VCCH3
GATEH3
PGND3
VIN
RREF
CREF
ROSC
VOSNS-
OCSET
VREF
VDRP
FB
EAOUT
SS/DEL
SCOMP2
SCOMP3
ROCSET
RDRP
IR3094
48LDMLPQ
VOUT SENSE+
VOUT+
L2
CBST2
1
2
RCOMP CCOMP
COUT
RCS2
CCS2
CSC3
GND
VIN
CSC2
RSC2
Cosns-
CSS
RSC3
VOUT SENSE-
CBIAS
L3
CBST3
VIN
CVCC
VIN
1
2
RSET
CVIN
RCS3
CCS3
GND
PGOOD
Figure 6 – System Diagram
Oscillator Resistor RROSC
The oscillator frequency is programmable from 100kHz to 540kHz with an external resistor RROSC as shown in
Figure 6. The Oscillator generates an internal 50% duty cycle sawtooth signal (Figure 3.) that is used to generate
120° out-of-phase timing pulses to set Phase 1,2 and 3 RS flip-flops. Once the switching frequency is chosen,
RROSC can be determined from the curve in the Typical Operating Characteristics Section.
Soft Start, Over-Current Fault Delay, and Hiccup Mode
The IR3094 has a programmable soft-start function to limit the surge current during converter power-up. A capacitor
connected between the SS/DEL and LGND pins controls soft start timing as well as over-current protection delay
and hiccup mode timing.
Figure 8 depicts the various operating modes of the SS/DEL function. Under a no fault condition, the SS/DEL
capacitor will charge. The SS/DEL charge soft-start duration is controlled by a 60uA charge current which charges
CSS up to 4.0V. The Error Amplifier output is clamped low until SS/DEL reaches 1.1V. The Error Amplifier will then
regulate the converter’s output voltage to match the SS/DEL voltage less the 1.1V offset until it reaches the level
determined by the VREF voltage. The PWRGD signal is asserted once the SS/DEL voltage exceeds 3.75V.
Four different faults will immediately cause SS/DEL to begin discharging and set the Fault Latch once SS/DEL is
below 3.75V;
Page 15 of 29
09/26/05
IR3094PBF
1. VCC Under Voltage Lock Out
2. 5VUVL Under Voltage Lock Out
3. Low Enable pin
4. Over Current condition.
A delay is included if any of the four fault conditions occurs after a successful soft start sequence. This is required
since momentary faults can occur as part of normal operation due to load transients such as exciting an over-
current condition. If any fault occurs during normal operation, the SS/DEL capacitor will discharge through a 55uA
current sink but will not set the fault latch immediately. If the fault condition persists long enough for the SS/DEL
capacitor to discharge below the 3.75V threshold of the delay comparator, the Fault latch will be set pulling the Error
Amplifier’s output low, inhibiting switching and de-asserting the PWRGD signal. The SS/DEL capacitor is then
discharged through a 6uA discharge current resulting in a long hiccup duration.
The SS/DEL capacitor will continue to discharge until it reaches 0.265V where the fault latch is reset allowing a
normal soft start to occur. If a fault condition is again encountered during the soft start cycle, the fault latch will be
set without any delay and hiccup mode will begin. During hiccup mode the 10 to 1 charge to discharge ratio results
in a 9.1% hiccup mode duty cycle regardless of at what point a fault condition occurs.
OVP fault immediately sets the fault latch causing SS/DEL to begin to discharge and this fault can only be cleared
by cycling power to the IR3094 on and off.
If SS/DEL pin is pulled below 0.8V, the converter can be disabled.
7.0V
VCC
UVLO
(12V)
4.36V
5VUVL
3.75V
1.1V
SS/DEL
VOUT
PWRGD
OCP THRESHOLD
IOUT
START-UP
NORMAL OPERATION
OCP
DELAY
HICCUP OVER-CURRENT
PROTECTION
RE-START
AFTER OCP
CLEARS
POWER-DOWN
(5VUVL GATES
FAULT MODE)
(VOUT CHANGES DUE TO
LOAD AND VID CHANGES)
(VCC GATES
FAULT MODE)
Figure 7 – Operating Waveforms
Soft-start delay time tSSDEL is the time SS/DEL charged up to 1.1V. After that the error amplifier output is released
to allow the soft start. The soft start time tSS represents the time during which converter output voltage rises from
zero to VO. tSS can be programmed by CSS using equation (3).
6
I
CHG *tSS 60*10 *tSS
VO
CSS
(3)
VO
Page 16 of 29
09/26/05
IR3094PBF
Once CSS is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the delay
time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in equation (4), (5) and (6)
respectively.
CSS *'V CSS *1.1
tSSDEL
tOCDEL
tVccPG
(4)
(5)
(6)
6
ICHG
60*10
CSS *'V CSS *0.25
6
IDISCHG
61*10
CSS *'V CSS *(3.75 ꢀVO ꢀ1.1)
6
ICHG
60*10
VREF Compensation Network RREF and CREF
A RC network tied between VREF pin and VOSENS- is needed to compensate VREF circuit. VREF should come up
earlier than SS/DEL pin charged up to 3.75V. For save estimation, use half of the soft start time that is 0.5*tSS as
the VREF voltage establishing time. Use equation (7) and (8) to determine RREF and CREF where VREF source
current ISOURCE is determained by RROSC and can be found using the curve in the TYPICAL OPERATING
CHARACTERISTICS section.
I
SOURCE *0.5*tSS
CREF
(7)
(8)
VREF
15
3.2ꢁ10
RREF 0.5ꢂ
2
CREF
Over Current Protection (OCP)
The current limit threshold is set by a resistor connected between the OCSET and VREF pins. If the average
Current Sense Amplifier output plus VREF voltage exceeds the OCSET voltage, the over-current protection is
triggered.
A delay is included if an over-current condition occurs after a successful soft-start sequence. This is required since
over-current conditions can occur as part of normal operation due to load transients. If an over-current fault occurs
during normal operation, the Over Current Comparator will initiate the discharge of the capacitor at SS/DEL but will
not set the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to
discharge below the 245mV offset of the delay comparator, the Fault latch will be set pulling the Error Amplifier’s
output low inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The hiccup mode duty cycle of
over current protection is determined by the fixed 10:1 ratio of the charge to discharge current.
The inductor DC resistance RL is utilized to sense the inductor current. The current limit threshold is set by a
resistor ROCSET connected between the OCSET and VREF pins, as shown in Fig6. ILIMIT is the required over
current limit. IOCSET, the bias current of OCSET pin, is set by RROSC and is determined by the curve in the Typical
Operating Characteristics Section. OCP need to satisfy the high temperature condition. RL_MAX and RL_ROOM are
the inductor DCR at maximum temperature TL_MAX and room temperature T_ROOM respectively, the maximum
inductor DCR can be calculated from Equation (9)
Page 17 of 29
09/26/05
IR3094PBF
6
RL _ MAX RL _ ROOM ꢁ[1ꢂ 3850*10 ꢁ(TL_ MAX ꢀTROOM )]
(9)
The current sense amplifier gain of IR3094 decreases with temperature at the rate of 1400 PPM, which
compensates part of the inductor DCR increase. The minimum current sense amplifier gain at the maximum IC
temperature TIC_MAX is calculated from Equation (10).
6
GCS _ MIN GCS _ ROOM ꢁ[1ꢀ1400*10 ꢁ(TIC _ MAX ꢀTROOM )]
(10)
ROCSET can be calculated by the following equation (11).
ILIMIT
3
ROCSET (
ꢁ RL _ MAX ) ꢁGCS _ MIN / IOCSET
(11)
Output Voltage Droop
In some of the applications, output voltage droop is needed to minimize output voltage deviations during load
transients and reduce power dissipation of the load when it is drawing maximum current.
The voltage at the VDRP pin is an average of three phase Current Sense Amplifiers and represents the sum of the
VREF voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through
the RDRP resistor, see figure 6. The Error Amplifier forces the voltage on the FB pin to equal VREF through the
power supply loop therefore the current through RDRP is equal to (VDRP-VREF) / RDRP. As the load current
increases, the VDRP voltage increases accordingly which results in an increase in RFB current, positioning the
output regulated voltage lower thus making the output voltage reduction proportional to an increase in load current.
The droop impedance or output impedance of the converter can thus be programmed by the resistor RDRP. The
offset and slope of the converter output impedance are independent of the VREF voltage.
The VDRP pin voltage represents the average current of the converter plus the 0.84V reference voltage. The load
current can be retrieved by subtracting the VREF voltage from the VDRP voltage.
The converter voltage will be lowered by RO*IO, where RO is the required output impedance of the converter. RDRP
is determined by Equation (12)
RFB ꢁ RL _ MAX ꢁGCS _ MIN
RDRP
(12)
n ꢁ RO
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor. The equation of the sensing network is,
RL ꢂ sL
1ꢂ sRS CS
1
vC (s) vL (s)
iL (s)
(13)
1ꢂ sRS CS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
Page 18 of 29
09/26/05
IR3094PBF
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as
follows.
L RL
CCS
RCS
(14)
Inductor DCR Temperature Correction
If the Current Sense Amplifier temperature dependent gain is not adequate to compensate the inductor DCR TC, a
negative temperature coefficient (NTC) thermistor can be added. The thermistor should be placed close to the
inductor and connected in parallel with the feedback resistor, as shown in Figure 8. The resistor in series with the
thermistor is used to reduce the nonlinearity of the thermistor.
Figure 8 - Temperature compensation of inductor DCR
Remote Voltage Sensing
To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects
directly to the load. The VREF voltage is referenced to VOSNS- to avoid additional error terms or delay related to a
separate differential amplifier. The capacitor connecting the VREF and VOSNS- pins ensure that high speed
transients are fed directly into the Error Amplifier without delay.
Page 19 of 29
09/26/05
IR3094PBF
Master-Slave Current Share Loop
Current sharing between phases of the converter is achieved by a Master-Slave current share loop topology. The
output of the Phase 1 Current Sense Amplifier sets the reference for the Share Adjust Error Amplifiers. Each Share
Adjust Error Amplifier adjusts the duty cycle of its respective PWM Ramp and to force its input error to zero
compared to the master Phase 1, resulting in accurate current sharing.
The maximum and minimum duty cycle adjust range of Ramps 2 & 3 compared to Ramp1 has been limited to a
minimum of 0.5x and a maximum of 2.0x typical (see Figure 3.). The crossover frequency of the current share loop
can be programmed with a capacitor at the SCOMPX pin so that the share loop does not interact with the output
voltage loop.
The SCOMPX capacitor is driven by a trans-conductance stage capable of sourcing and sinking 22uA. The duty
cycle of Ramps 2 & 3 inversely tracks the voltage on their SCOMPX pin; if V(SCOMP2) increases, Ramp2’s slope
will increase and the effective duty cycle will decrease resulting in a reduction in Phase 2’s output current. Due to
the limited 22uA source current, an SCOMPX pre-conditon circuit has been included to pre-condition V(SCOMPX)
so that the duty cycle of Ramps 2 & 3 are equal to Ramp1 prior to any GATEHX high pulses. The pre-condition
circuit can source/sink 360uA. The SYNC LATCH (see Figure 1) releases the pre-condition circuit once FB reaches
78% of VREF.
Set BIASOUT voltage
BIASOUT pin provides a 150mA open-loop regulated voltage for GATE drive bias. The voltage is set by SETBIAS
through an external resistor Rset connecting between SETBIAS pin and ground. Bias current ISETBIAS is a function of
ROSC. Rset is chosen by equation (15). VFD in the equation is the forward voltage drop across the Bootstrap diode.
VBIASOUT ꢂVFD
RSET
(15)
ISETBIAS
Compensation of the Current Share Loop
The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop
in order to eliminate the interaction between the two loops. A 22nF capacitor from SCOMP to LGND is good for
most of the applications. If necessary have a resistor in series with the Csc to make the current loop a little bit
faster.
Compensation of Voltage Loop
The selection of compensation types depends on the output capacitors used in the converter. For the applications
using Electrolytic, Polymer or AL-Polymer capacitors and running at lower frequency, type II compensation shown in
Figure 9(a) is usually enough. While for the applications using only ceramic capacitors and running at higher
frequency, type III compensation shown in Figure 9(b) is preferred.
For applications without voltage droop, the compensation is the same as for the regular voltage mode control. For
converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency, type
III compensation is required as shown in Figure 9(b) with RDRP and CDRP removed.
Page 20 of 29
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IR3094PBF
CCP1
CCP1
RFB
CFB
RCP
CCP
VO+
RCP
CCP
RFB1
FB
-
EAOUT
RFB
EAOUT
VO+
FB
VREF
VDAC
-
RDRP
+
VDRP
EAOUT
EAOUT
VREF
RDRP
CDRP
+
VDRP
(a) Type II compensation
(b) Type III compensation
Figure 9. Voltage loop compensation networks
Type II Compensation for Voltage Droop Applications
Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10
and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the
output inductors matches that of the inductor, and determine RCP and CCP from (16) and (17), where LE and CE are
the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively.
(2S ꢁ fC )2 ꢁ LE ꢁCE ꢁ RFB ꢁ5
VI * 1ꢂ (2S * fC *C *RC )2
RCP
(16)
(17)
10 ꢁ LE ꢁ CE
CCP
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A
ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for Voltage Droop Applications
Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and
capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the
voltage loop can be estimated by (18) and (19), where RLE is the equivalent resistance of inductor DCR.
RDRP
(18)
(19)
fC1
2S *CE ꢁGCS *RFB ꢁ RLE
180
TC1 90 ꢀ A tan(0.5)ꢁ
S
Choose the desired crossover frequency fc around fc1 estimated by (18) or choose fc between 1/10 and 1/5 of the
switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB /Dec
around the crossover frequency. Choose resistor RFB1 according to (20), and determine CFB and CDRP from (21)
and (22).
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IR3094PBF
1
2
2
3
RFB1
RFB to
RFB1
RFB
(20)
(21)
1
CFB
4S ꢁ fC ꢁ RFB1
(RFB ꢂ RFB1 ) ꢁCFB
(22)
CDRP
RDRP
RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency
and transient load response. Determine RCP and CCP from (23) and (24).
(2S ꢁ fC )2 ꢁ LE ꢁCE ꢁ RFB ꢁ5
RCP
(23)
(24)
VI
10 ꢁ LE ꢁ CE
CCP
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A
ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for No Droop Applications
Resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of the
switching frequency per phase and select the desired phasHꢁPDUJLQꢁ Fꢂꢁ&DOFXODWHꢁ.ꢁIDFWRUꢁIURPꢁꢃ25), and determine
the component values based on (26) to (30),
TC
S
4
K tan[ ꢁ(
ꢂ1.5)]
(25)
(26)
(27)
(28)
(29)
(30)
180
(2S ꢁ LE ꢁCE ꢁ fC )2 ꢁ5
VI ꢁK
RCP RFB
ꢁ
K
CCP
2S ꢁ fC ꢁ RCP
1
CCP1
2S ꢁ fC ꢁ K ꢁ RCP
K
CFB
2S ꢁ fC ꢁ RFB
1
RFB1
2S ꢁ fC ꢁ K ꢁ CFB
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IR3094PBF
MathCAD file to estimate the power dissipation of the IC
The full featured Control IC IR3094 contain both Control and 3 phase Gate Drive functions. It also has the
adjustable voltage bias regulator inside to provide MOSFET Drive Voltage. For the thermal consideration,
this Mathcad file step by step shows how to estimate the power dissipation of IR3094 .
Initial Conditions:
No.of Phases:
n ꢃ 3
IC Supply Voltage:
, IC Supply Current(quiescent):
Vcc ꢃ 12 (V)
Icq ꢃ 35 (mA)
Total High side Driver VCCH supply current(quiescent):
Total Low side Driver VCCL supply Current(quiescent):
Iqh ꢃ 5 n (mA)
Iql ꢃ 5 n (mA)
Biasout Voltage:
Vbias ꢃ 7.5 (V)
Switching Frequency per phase:
Thermal Impedance of IC:
fsw ꢃ 450 (kHz)
(oC/W)
T
ꢃ 27
JA
The data from the selected MOSFETs:
ControI FET IR6637, Number of Control FET per phase:
Control FET total gate charge:
nc ꢃ 1
Qgc ꢃ 15 (nC)
Synchronous FET IR6612, Number of sync. FET per phase:
Sync FET total gate charge:
ns ꢃ 1
Qgs ꢃ 45 (nC)
Power Dissipation:
The IC will have less power dissipation if using external gate driver supply. For the worst case
estimation, assuming using the bias regulator for all the gate drive supply voltage.
1. Quiescent Power dissipation
Total Quiescent Power Dissipation:
ꢀ 3
Pq ꢃ (Icq ꢂ Iqh ꢂ Iql) Vcc 10
Pq
(W)
2. The Power Loss to drive the gate of the MOSFETs
With the assumption of the low MOSFET gate resistances, most gate drive losses are dissipated
in the driver circuit.
3
ꢀ 9
Pdrv ꢃ Vbias fsw 10 n (nc Qgc ꢂ ns Qgs) 10
Pdrv
(W)
¬
¼
3
ꢀ 9
Where the
term in the equation gives the total
Ig ꢃ fsw 10 n (nc Qgc ꢂ ns Qgs) 10
average bias current required to drive all the MOSFETs.
3. The bias regulator Power Loss to supply driving the MOSFETs
Preg ꢃ (Vcc ꢀ Vbias) Ig Preg
(W)
4. Total Power Dissipation of the IC:
Pdiss ꢃ Pq ꢂ Pdrv ꢂ Preg
Pdiss
(W)
(oC)
And the total Junction temperature rising is:
Pdiss T
JA
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IR3094PBF
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC. Refer to the schematic in Figure 6 – System Diagram.
x
x
Dedicate at least one inner layer of the PCB as power ground plane (PGND).
The center pad of IC must be connected to ground plane (PGND) using the recommended via pattern shown in
“Package Dimensions”.
x
x
The IC’s PGND1, 2, 3 and LGND should connect to the center pad under IC.
The following components must be grounded directly to the LGND pin on the IC using a ground plane on the
component side of PCB: CSS, RSC2, RSC3, RSET, CVCC and C5VREF. The LGND should only be connected to
ground plan on the center pad under IC
x
Place the decoupling capacitors CVCC and CBIAS as close as possible to the VCC and VCCL1_2, VCCL3
pins. The ground side of CBIAS should not be connected to LGND and it should directly ground through vias.
x
The following components should be placed as close as possible to the respective pins on the IC: RROSC,
ROCSET, CREF, RREF, CSS, CSC2, RSC2, CSC3, RSC3, RSET.
x
Place current sense capacitors CCS1, 2, 3 and resistors RCS1, 2, 3 as close as possible to CSINP1, 2, 3 pins
of IC and route the two current sense signals in pairs connecting to the IC. The current sense signals should be
located away from gate drive signals and switch nodes.
x
Use Kelvin connections to route the current sense traces to each individual phase inductor, in order to achieve
good current share between phases.
x
Place the input decoupling capacitors closer to the drain of top MOSFET and the source of the bottom
MOSFET. If possible, Use multiple smaller value ceramic caps instead of one big cap, or use low inductance type of
ceramic cap, to reduce the parasitic inductance.
x
Route the high current paths using wide and short traces or polygons. Use multiple vias for connections
between layers.
x
-
-
-
The symmetry of the following connections from phase to phase is important for proper operation:
The Kelvin connections of the current sense signals to inductors.
The gate drive signals from the IC to the MOSFETS.
The polygon shape of switching nodes.
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IR3094PBF
PCB AND STENCIL DESIGN METHODOLOGY
x
x
x
7x7
48 Lead
0.5mm pitch MLPQ
See Figures 10-12.
PCB Metal Design (0.5mm Pitch Leads)
1.
spacing should be ꢁꢄꢂꢅPPꢁWRꢁPLQLPL]HꢁVKRUWLQJꢂ
2. Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension +
Lead land width should be equal to nominal part lead width. The minimum lead to lead
0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the
inboard extension will accommodate any part misalignment and ensure a fillet.
3.
Center pad land length and width should be = maximum part pad length and width. However,
the minimum metal to metal spacing should be ꢁꢄꢂꢆꢇPPꢁꢃꢅꢁR]ꢂꢁ&RSSHUꢀꢁꢁꢄꢂꢅꢈPPꢁIRUꢁꢈꢁR]ꢂꢁ&RSSHUꢁ
and ꢁꢄꢂꢆPPꢁIRUꢁꢆꢁR]ꢂꢁ&RSSHUꢉ
4.
Sixteen 0.30mm diameter vias shall be placed in the pad land spaced at 1.2mm, and
connected to ground to minimize the noise effect on the IC, and to transfer heat to the PCB.
PCB Solder Resist Design (0.5mm Pitch Leads)
1.
Lead lands. The solder resist should be pulled away from the metal lead lands by a minimum
of 0.060mm. The solder resist mis-alignment is a maximum of 0.050mm and it is recommended that
the lead lands are all NSMD. Therefore pulling the S/R 0.060mm will always ensure NSMD pads.
2.
The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist
is completely removed from between the lead lands forming a single opening for each “group” of lead
lands.
3.
provide a fillet so a solder resist width of ꢁꢄꢂꢆꢇPPꢁUHPDLQVꢂ
4. Land Pad. The land pad should be SMD, with a minimum overlap of the solder resist onto the
At the inside corner of the solder resist where the lead land groups meet, it is recommended to
copper of 0.060mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable
to have the solder resist opening for the land pad to be smaller than the part pad.
5.
the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
6. The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm
Ensure that the solder resist in-between the lead lands and the pad land is ꢁꢄꢂꢆꢊPPꢁGXHꢁWRꢁ
larger than the diameter of the via.
Stencil Design (0.5mm Pitch Leads)
1.
The stencil apertures for the lead lands should be approximately 80% of the area of the lead
lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for
0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made
narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
2.
The stencil lead land apertures should therefore be shortened in length by 80% and centered
on the lead land.
3.
The center land pad aperture should be striped with 0.25mm wide openings and spaces to
deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the
center land pad the part will float and the lead lands will be open.
4.
The maximum length and width of the center land pad stencil aperture should be equal to the
solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the
center land to the lead lands when the part is pushed into the solder paste.
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IR3094PBF
Figure 10. PCB metal and solder resist.
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IR3094PBF
Figure 11. PCB metal and component placement.
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IR3094PBF
Figure 12. Stencil design.
Page 28 of 29
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IR3094PBF
PACKAGE DIMENSIONS
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
www.irf.com
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