IRF1404PBF [INFINEON]
HEXFET㈢ Power MOSFET; HEXFET㈢功率MOSFET
| 型号： | IRF1404PBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET㈢ Power MOSFET |
| 文件： | 总10页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-94968
IRF1404PbF
HEXFET® Power MOSFET
l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Automotive Qualified (Q101)
l Lead-Free
D
VDSS = 40V
RDS(on) = 0.004Ω
G
ID = 202A
S
Description
Seventh Generation HEXFET® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable
device for use in a wide variety of applications including
automotive.
The TO-220 package is universally preferred for all
automotive-commercial-industrialapplicationsatpower
dissipation levels to approximately 50 watts. The low
thermal resistance and low package cost of the TO-220
contributetoitswideacceptancethroughouttheindustry.
Absolute Maximum Ratings
TO-220AB
Parameter
Max.
202
143
808
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
A
PD @TC = 25°C
Power Dissipation
333
W
W/°C
V
Linear Derating Factor
2.2
VGS
EAS
IAR
Gate-to-Source Voltage
± 20
620
Single Pulse Avalanche Energy
Avalanche Current
mJ
See Fig.12a, 12b, 15, 16
A
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
mJ
1.5
V/ns
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
-55 to + 175
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
Units
RθJC
RθCS
RθJA
0.45
–––
62
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
°C/W
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1
02/02/04
IRF1404PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
40 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.039 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– 0.0035 0.004
Ω
V
S
VGS = 10V, ID = 121A
VDS = 10V, ID = 250µA
VDS = 25V, ID = 121A
2.0
76
––– 4.0
––– –––
Forward Transconductance
––– ––– 20
––– ––– 250
––– ––– 200
––– ––– -200
––– 131 196
VDS = 40V, VGS = 0V
IDSS
Drain-to-Source Leakage Current
µA
nA
VDS = 32V, VGS = 0V, TJ = 150°C
VGS = 20V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
IGSS
VGS = -20V
Qg
ID = 121A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
36 –––
37 56
17 –––
nC VDS = 32V
VGS = 10V
VDD = 20V
––– 190 –––
ID = 121A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
46 –––
33 –––
RG = 2.5Ω
RD = 0.2Ω
D
S
Between lead,
4.5
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
–––
–––
–––
6mm (0.25in.)
nH
G
from package
7.5
and center of die contact
Ciss
Input Capacitance
––– 5669 –––
––– 1659 –––
––– 223 –––
––– 6205 –––
––– 1467 –––
––– 2249 –––
VGS = 0V
Coss
Output Capacitance
pF
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
Coss
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 32V
Coss
Output Capacitance
Coss eff.
Effective Output Capacitance ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
IS
MOSFET symbol
––– –––
202
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 808
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.5
––– 78 117
––– 163 245
V
TJ = 25°C, IS = 121A, VGS = 0V
ns
TJ = 25°C, IF = 121A
Qrr
ton
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 400µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11)
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25°C, L = 85µH
as Coss while VDS is rising from 0 to 80% VDSS
RG = 25Ω, IAS = 121A. (See Figure 12)
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
ISD ≤ 121A, di/dt ≤ 130A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
2
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IRF1404PbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM4.5V
BOTTOM4.5V
4.5V
4.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
°
°
T = 175 C
J
T = 25 C
J
1
0.1
1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.5
202A
=
I
D
°
T = 25 C
J
2.0
1.5
1.0
0.5
0.0
°
T = 175 C
J
100
V
= 25V
DS
20µs PULSE WIDTH
V
=10V
GS
10
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
4
5
6
7
8
9
10 11
12
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF1404PbF
20
16
12
8
10000
I = 121A
D
V
= 0V, f = 1 MHZ
GS
V
V
= 32V
= 20V
DS
DS
C
= C + C , C SHORTED
iss
gs
gd ds
C
= C
8000
6000
4000
2000
0
rss
gd
C
= C + C
oss
ds gd
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 13
1
10
100
0
0
50
100
150
200
V
, Drain-to-Source Voltage (V)
Q , Total Gate Charge (nC)
DS
G
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
°
T = 175 C
J
10us
100us
°
T = 25 C
J
1ms
10ms
1
°
T = 25 C
C
°
T = 175 C
Single Pulse
J
V
= 0 V
GS
3.0
0.1
0.0
1
0.5
1.0
1.5
2.0
2.5
3.5
1
10
100
V
,Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF1404PbF
RD
220
200
180
160
140
120
100
80
VDS
LIMITED BY PACKAGE
VGS
10V
DꢀUꢀTꢀ
RG
+VDD
-
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
60
V
DS
40
90%
20
0
25
50
75
100
125
150
175
°
T , Case Temperature ( C)
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.01
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
DM
t
1
t
2
Notes:
1. Duty factor D = t / t
1
2
2. Peak T =P
x Z
+ T
thJC C
J
DM
0.001
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1404PbF
1500
1200
900
600
300
0
15V
I
D
TOP
49A
101A
BOTTOM 121A
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
-
I
A
AS
20V
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T , Junction Temperature( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
4.0
GS
GD
V
G
3.0
2.0
1.0
I
= -250µA
Charge
D
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
-75 -50 -25
0
25
50
75 100 125 150
V
GS
T , Temperature ( °C )
3mA
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRF1404PbF
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
∆
avalanche losses
0.05
0.10
1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax
is not exceeded.
3. Equation below based on circuit and waveforms shown
in Figures 12a, 12b.
400
TOP
BOTTOM 10% Duty Cycle
= 121A
Single Pulse
350
300
250
200
150
100
50
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
0
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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IRF1404PbF
Peak Diode Recovery dv/dt Test Circuit
+
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
DꢀUꢀT
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as DꢀUꢀTꢀ
• ISD controlled by Duty Factor "D"
• DꢀUꢀTꢀ - Device Under Test
VDD
Driver Gate Drive
P.W.
Period
Period
D =
P.W.
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. For N-channel HEXFET® Power MOSFETs
8
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IRF1404PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
3.78 (.149)
- B -
10.29 (.405)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
3.54 (.139)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
HEXFET
IGBTs, CoPACK
2- DRAIN
3- SOURCE
1
2
3
1- GATE
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4- DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1
2
DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
CONTROLLING DIMENSION : INCH
3
4
OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
PART NUMBER
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
INT ERNAT IONAL
RECT IFIER
LOGO
Note: "P" in assembly line
position indicates "Lead-Free"
DAT E CODE
YEAR 7 = 1997
WEEK 19
AS S EMBLY
LOT CODE
LINE C
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.02/04
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9
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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