IRF1405L [INFINEON]
Power MOSFET(Vdss=55V, Rds(on)=5.3mohm, Id=131A); 功率MOSFET （ VDSS = 55V ， RDS（ON） = 5.3mohm ，ID = 131A ）
| 型号： | IRF1405L |
| 厂家： | 
Infineon |
| 描述： | Power MOSFET(Vdss=55V, Rds(on)=5.3mohm, Id=131A) |
| 文件： | 总11页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD -93992
IRF1405S
IRF1405L
AUTOMOTIVE MOSFET
Typical Applications
HEXFET® Power MOSFET
●
●
●
●
●
Electric Power Steering (EPS)
Anti-lock Braking System (ABS)
Wiper Control
Climate Control
Power Door
D
VDSS = 55V
RDS(on) = 5.3mΩ
Benefits
G
●
●
●
●
●
●
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
ID = 131A
S
Description
Stripe Planar design of HEXFET® Power MOSFETs
utilizes the lastest processing techniques to achieve
extremelylow on-resistancepersiliconarea. Additional
features of this HEXFET power MOSFET are a 175°C
junction operating temperature, fast switching speed
and improved repetitive avalanche rating. These
benefits combine to make this design an extremely
efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
Absolute Maximum Ratings
D2Pak
IRF1405S
TO-262
IRF1405L
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
131
93
680
A
PD @TC = 25°C
Power Dissipation
200
W
W/°C
V
Linear Derating Factor
1.3
VGS
EAS
IAR
Gate-to-Source Voltage
± 20
590
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
See Fig.12a, 12b, 15, 16
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
mJ
V/ns
5.0
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
0.75
40
Units
°C/W
RθJC
RθJA
Junction-to-Ambient (PCB mount)
–––
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1
1/11/01
IRF1405S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
55 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
69
4.6 5.3
––– 4.0
––– –––
mΩ VGS = 10V, ID = 101A
V
S
VDS = 10V, ID = 250µA
VDS = 25V, ID = 110A
VDS = 55V, VGS = 0V
VDS = 44V, VGS = 0V, TJ = 150°C
VGS = 20V
Forward Transconductance
––– ––– 20
––– ––– 250
––– ––– 200
––– ––– -200
––– 170 260
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
IGSS
VGS = -20V
Qg
ID = 101A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
44
62
66
93
nC VDS = 44V
VGS = 10V
VDD = 38V
13 –––
––– 190 –––
––– 130 –––
––– 110 –––
ID = 110A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 1.1Ω
VGS = 10V
D
Between lead,
4.5
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
–––
–––
–––
6mm (0.25in.)
nH
G
from package
7.5
and center of die contact
S
Ciss
Input Capacitance
––– 5480 –––
––– 1210 –––
––– 280 –––
––– 5210 –––
––– 900 –––
––– 1500 –––
VGS = 0V
Coss
Output Capacitance
pF
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
Coss
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 44V
Coss
Output Capacitance
Coss eff.
Effective Output Capacitance ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
IS
MOSFET symbol
––– –––
131
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 680
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 88 130
––– 250 380
V
TJ = 25°C, IS = 101A, VGS = 0V
ns
TJ = 25°C, IF = 101A
Qrr
ton
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
www.irf.com
IRF1405S/L
1000
100
10
1000
100
10
VGS
15V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T = 175 C
J
°
°
T = 25 C
J
1
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
169A
=
I
D
°
T = 25 C
J
°
T = 175 C
2.5
2.0
1.5
1.0
0.5
0.0
J
100
10
1
V
= 25V
DS
V
= 10V
GS
20µs PULSE WIDTH
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
4
6
8
10 12
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF1405S/L
20
16
12
8
100000
I
D
= 101A
V
= 0V,
f = 1 MHZ
GS
V
V
= 44V
= 27V
DS
DS
C
= C + C
,
C
ds
SHORTED
iss
gs
gd
C
= C
rss
gd
C
= C + C
oss
ds gd
10000
1000
100
Ciss
Coss
Crss
10
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
60
Q
120
180
240
300
1
100
, Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
10000
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
°
T = 175 C
J
100
10us
100us
°
T = 25 C
J
1ms
10
10ms
°
= 25 C
T
C
°
T
= 175 C
J
V
= 0 V
Single Pulse
GS
2.5
1
0.0
1
0.5
V
1.0
1.5
2.0
3.0
1
10
100
,Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
www.irf.com
IRF1405S/L
160
120
80
40
0
RD
VDS
LIMITED BY PACKAGE
VGS
10V
D.U.T.
RG
+VDD
-
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
, Case Temperature ( C)
T
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.10
0.05
0.1
0.01
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
DM
t
1
t
2
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T = P
x Z
+ T
C
J
DM
thJC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1405S/L
1400
1200
1000
800
600
400
200
0
1 5V
I
D
TOP
41A
71A
BOTTOM 101A
DRIVER
L
V
G
DS
D.U.T
R
+
V
D D
-
I
A
AS
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T , Junction Temperature ( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
4.0
3.5
3.0
2.5
2.0
1.5
V
G
Charge
I
= 250µA
D
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
3mA
T
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
www.irf.com
IRF1405S/L
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
∆
avalanche losses
0.05
0.10
1
0.1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
600
500
400
300
200
100
0
TOP
BOTTOM 10% Duty Cycle
= 101A
Single Pulse
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = ∆T/ ZthJC
Fig 16. Maximum Avalanche Energy
Iav = 2∆T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRF1405S/L
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T*
-
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
+
-
VDD
VGS
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
Period
D =
P.W.
V
[
=10V
] ***
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
[
[
]
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
]
SD
Ripple ≤ 5%
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 17. For N-channel HEXFET® power MOSFETs
8
www.irf.com
IRF1405S/L
D2Pak Package Outline
10.54 (.415)
10.29 (.405)
10.16 (.400)
REF.
- B -
1.32 (.052)
4.69 (.185)
4.20 (.165)
1.40 (.055)
- A -
M AX.
1.22 (.048)
2
6.47 (.255)
6.18 (.243)
1.78 (.070)
1.27 (.050)
15.49 (.610)
14.73 (.580)
2.79 (.110)
2.29 (.090)
1
3
2.61 (.103)
2.32 (.091)
5.28 (.208)
4.78 (.188)
8.89 (.350)
REF.
1.40 (.055)
1.14 (.045)
1.39 (.055)
1.14 (.045)
3X
0.55 (.022)
0.46 (.018)
0.93 (.037)
0.69 (.027)
3X
5.08 (.200)
0.25 (.010)
M
B A M
MINIMUM RECOM MENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
LEAD ASSIGNMENTS
1 - GATE
NO TES:
1
2
3
4
DIM ENSIONS AFTER SO LDER DIP.
17.78 (.700)
2 - DRAIN
3 - SOURCE
DIM ENSIONING & TOLERANCING PER ANSI Y14.5M , 1982.
CONTROLLING DIM ENSION : INCH.
HEATSINK & LEAD DIM ENSIONS DO NOT INCLUDE BURRS.
3.81 (.150)
2.54 (.100)
2.08 (.082)
2X
2X
D2Pak Part Marking Information
A
INTERNATIONAL
RECTIFIER
PART NUM BER
F530S
LOGO
9246
1M
DATE CODE
(YYW W )
9B
ASSEM BLY
YY
=
YEAR
= W EEK
LOT CODE
W W
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9
IRF1405S/L
TO-262 Package Outline
TO-262 Part Marking Information
10
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IRF1405S/L
D2Pak Tape & Reel Information
TR R
1 .60 (.0 63)
1 .50 (.0 59)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEE D D IREC TIO N
TR L
11.60 (.457)
11.40 (.449)
1 .85 (.0 73)
1 .65 (.0 65)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED D IRE CTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
M AX.
60.00 (2.362)
M IN.
30.40 (1.197)
M AX.
NO TES
1. CO M FORM S TO EIA-418.
2. CO NTROLLING DIM ENSIO N: M ILLIM ETER.
3. DIM ENSION M EASURED
:
26.40 (1.039)
24.40 (.961)
4
@ HUB.
3
4. INCLUDES FLANGE DISTORTION
@
O UTER EDGE.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.11mH
RG = 25Ω, IAS = 101A. (See Figure 12).
ISD ≤ 101A, di/dt ≤ 210A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
ꢀCoss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
,
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.1/01
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11
相关型号：
IRF1405STRLPBF
Power Field-Effect Transistor, 75A I(D), 55V, 0.0053ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, PLASTIC, D2PAK-3
INFINEON
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