IRF6604TR1_技术文档

IRF^P6^D6^{- 94}0³⁶4^5E

HEXFET^®Power MOSFET

V_DSS

30V

R_DS(on)max

11.5mΩ@V_GS= 7.0V

13mΩ@V_GS= 4.5V

Qg

17nC

l Application Specific MOSFETs

l Ideal for CPU Core DC-DC Converters

l Low Conduction Losses

l Low Switching Losses

l Low Profile (<0.7 mm)

l Dual Sided Cooling Compatible

l Compatible with existing Surface Mount

Techniques

DirectFETISOMETRIC

MQ

Applicable DirectFET Outline and Substrate Outline (see p.9,10 for details)

SQ SX ST MQ MX MT

Description

The IRF6604 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET^TMpackaging

to achieve the lowest on-state resistance charge product in a package that has the footprint of an SO-8 and only 0.7 mm

profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly

equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed

regarding the manufacturing methods and process. The DirectFET package allows dual sided cooling to maximize

thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%.

The IRF6604 balances both low resistance and low charge along with ultra low package inductance to reduce both conduc-

tion and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power

the latest generation of processors operating at higher frequencies. The IRF6604 has been optimized for parameters that

are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket.

Absolute Maximum Ratings

Max.

Parameter

Units

V_DS

30

Drain-to-Source Voltage

V

±12

V

Gate-to-Source Voltage

GS

Continuous Drain Current, V_GS@ 7.0V

Pulsed Drain Current

49

I

@ T_C= 25°C

D

12

@ T_A= 25°C

@ T_A= 70°C

A

9.2

92

2.3

DM

P

@T_A= 25°C

@T_A= 70°C

@T_C= 25°C

Power Dissipation

D

1.5

Power Dissipation

W

42

Power Dissipation

0.018

-40 to + 150

Linear Derating Factor

W/°C

°C

T

Operating Junction and

J

Storage Temperature Range

STG

Thermal Resistance

Parameter

Junction-to-Ambient

Typ.

–––

12.5

20

Max.

55

Units

R_θ

JA

–––

3.0

JA

Junction-to-Ambient

Junction-to-Case

°C/W

JA

–––

1.0

JC

Junction-to-PCB Mounted

–––

J-PCB

Notes through are on page 11

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1

11/16/05

IRF6604

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Drain-to-Source Breakdown Voltage

Min. Typ. Max. Units

Conditions

V_GS= 0V, I_D= 250µA

BV_DSS

30

–––

V

∆ΒV_DSS/∆T_J

R_DS(on)

Breakdown Voltage Temp. Coefficient –––

Static Drain-to-Source On-Resistance –––

–––

27

––– mV/°C Reference to 25°C, I_D= 1mA

mΩ

9.0

11.5

13

V_GS= 7.0V, I_D= 12A

V_GS= 4.5V, I_D= 9.6A

V_DS= V_GS, I_D= 250µA

10

V_GS(th)

Gate Threshold Voltage

1.3

–––

38

–––

-4.5

–––

2.1

V

∆V_GS(th)/∆T_J

I_DSS

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

––– mV/°C

30

50

µA V_DS= 24V, V_GS= 0V

µA V_DS= 30V, V_GS= 0V

100

V

_DS= 24V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

nA V_GS= 12V

V_GS= -12V

––– -100

gfs

Q_g

–––

17

–––

26

S

V

_DS= 15V, I_D= 9.6A

–––

Q_gs1

Q_gs2

Q_gd

Q_godr

Q_sw

Q_oss

R_G

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

4.1

1.0

6.3

5.6

7.3

9.5

1.1

11

–––

2.0

V_DS= 15V

nC V_GS= 4.5V

I_D= 9.6A

Gate Charge Overdrive

See Fig. 16

Switch Charge (Q_gs2+ Q_gd)

Output Charge

nC

V_DS= 16V, V_GS= 0V

Gate Resistance

Turn-On Delay Time

Rise Time

Ω

t_d(on)

t_r

t_d(off)

t_f

–––

V_DD= 15V, V_GS= 4.5V

I_D= 9.6A

4.3

18

Turn-Off Delay Time

Fall Time

ns Clamped Inductive Load

25

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 2270 –––

V_GS= 0V

pF V_DS= 15V

ƒ = 1.0MHz

–––

420

190

–––

Avalanche Characteristics

Parameter

Typ.

–––

Max.

32

Units

mJ

A

Single Pulse Avalanche Energy

E_AS

I_AR

Avalanche Current

9.6

Repetitive Avalanche Energy

E_AR

0.23

mJ

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

D

I_S

Continuous Source Current

–––

42

(Body Diode)

Pulsed Source Current

A

showing the

integral reverse

G

I_SM

–––

92

S

(Body Diode)

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

–––

0.94

31

1.2

47

39

V

T = 25°C, I = 9.6A, V = 0V

J S GS

Reverse Recovery Time

Reverse Recovery Charge

ns T = 25°C, I = 9.6A

J F

Q_rr

di/dt = 100A/µs

26

nC

2

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IRF6604

1000

100

10

1000

100

10

VGS

10V

VGS

10V

TOP

7.0V

4.5V

4.0V

3.5V

3.3V

3.0V

7.0V

4.5V

4.0V

3.5V

3.3V

3.0V

BOTTOM 2.7V

2.7V

20µs PULSE WIDTH

Tj = 150°C

20µs PULSE WIDTH

Tj = 25°C

1

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

2.0

100.00

12A

=

I

D

T

= 150°C

J

1.5

1.0

0.5

0.0

T

= 25°C

J

10.00

V

= 15V

DS

20µs PULSE WIDTH

V

= 7.0V

1.00

GS

2.5

3.0

3.5

4.0

-60 -40 -20

0

20

40

60

80 100 120 140 160

°

T , Junction Temperature

(

C)

V

, Gate-to-Source Voltage (V)

J

GS

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

Vs. Temperature

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3

IRF6604

10000

6.0

5.0

4.0

3.0

2.0

1.0

0.0

V

C

= 0V,

f = 1 MHZ

GS

I = 9.6A

D

= C + C

,

C

SHORTED

iss

gs

gd

ds

C

= C

V

= 24V

= 15V

rss

gd

DS

C

= C + C

oss

ds

gd

Ciss

1000

Coss

Crss

100

1

10

100

0

5

10

15

20

25

V

, Drain-to-Source Voltage (V)

DS

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Fig 5. Typical Capacitance Vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

100

10

1

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R (on)

DS

°

T = 150

C

J

°

T = 25

C

J

100µsec

1msec

1

10msec

Tc = 25°C

Tj = 150°C

V

= 0 V

Single Pulse

GS

0.1

0.0

0.5

1.0

1.5

2.0

0

1

10

100

1000

V

,Source-to-Drain Voltage (V)

SD

V

, Drain-toSource Voltage (V)

DS

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4

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IRF6604

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

12

9

I

= 250µA

D

6

3

0

25

50

75

100

125

150

-75 -50 -25

0

25

50

75 100 125 150

T_A, Ambient Temperature (°C)

T

, Temperature ( °C )

J

Fig 9. Maximum Drain Current Vs.

Fig 10. Threshold Voltage Vs. Temperature

Ambient Temperature

100

10

1

D = 0.50

0.20

0.10

0.05

P

DM

0.02

0.01

t

1

t

2

SINGLE PULSE

(THERMAL RESPONSE)

Notes:

1. Duty factor D =

t

/ t

1

2

2. Peak T

= P

x

Z

+ T

J

DM

thJA

A

0.1

0.00001

0.0001

0.001

0.01

0.1

1

10

100

t , Rectangular Pulse Duration (sec)

1

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

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5

IRF6604

80

60

40

20

0

I

15V

D

TOP

4.3A

7.7A

9.6A

BOTTOM

DRIVER

+

L

V

DS

D.U.T

AS

R

G

V

DD

-

I

A

V

20V

GS

0.01

Ω

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

25

50

75

100

125

150

°

( C)

Starting Tj, Junction Temperature

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

L_D

I

AS

V_DS

Fig 12b. Unclamped Inductive Waveforms

+

-

V_DD

D.U.T

Current Regulator

V_GS

Same Type as D.U.T.

Pulse Width < 1µs

Duty Factor < 0.1%

50KΩ

.2µF

12V

Fig 14a. Switching Time Test Circuit

V_DS

.3µF

+

V

DS

D.U.T.

-

90%

V

GS

3mA

10%

V_GS

I

D

G

Current Sampling Resistors

t_d(on)

t_d(off)

t_r

t_f

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

6

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IRF6604

Driver Gate Drive

P.W.

D =

Period

D.U.T

Period

+

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

-

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

I

SD

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 16. Gate Charge Waveform

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7

IRF6604

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

loss

conduction

drive

output

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

g

⎛

⎜

Q_oss

⎞

⎠

P_loss= P_conduction+ P_switching+ P_drive+ P_output

+

×V × f + Q × V × f

(

)

in

rr

in

⎝ 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

P

= I ²× R_ds(on)

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

⎛

Q_gd

i_g

⎞

Q_gs2

i_g

⎞

⎟

⎜

⎟

⎜

+ I ×

× V × f + I ×

× V × f

in

⎝

⎠

⎝

⎠

+ Q × V × f

(

)

g

⎛ Q_oss

⎞

⎠

+

×V × f

in

⎝

2

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFET data sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

8

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IRF6604

DirectFET Outline Dimension, MQ Outline

(Medium Size Can, Q-Designation).

Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.

This includes all recommendations for stencil and substrate designs.

DIMENSIONS

IMPERIAL

MIN

METRIC

MAX

CODE

MIN

6.25

4.80

3.85

0.35

0.68

0.69

0.57

0.23

1.57

2.95

0.59

0.03

0.08

MAX

0.250

0.199

0.156

0.018

0.028

0.029

0.024

0.011

0.067

0.123

0.028

0.003

0.007

6.35

5.05

3.95

0.45

0.72

0.73

0.61

0.27

1.70

3.12

0.70

0.08

0.17

0.246

0.189

0.152

0.014

0.027

0.022

0.009

0.062

0.116

0.023

0.001

0.003

A

B

C

D

E

F

G

H

J

K

L

M

N

P

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9

IRF6604

DirectFET Substrate and PCB Layout, MQ Outline

(MediumSize Can, Q-Designation).

Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.

This includes all recommendations for stencil and substrate designs.

G = GATE

D = DRAIN

S = SOURCE

D

S

G

10

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IRF6604

DirectFET Tape & Reel Dimension

(Showing component orientation).

NOTE: Controlling dimensions in mm

Std reel quantity is 4800 parts. (ordered as IRF6604). For 1000 parts on 7" reel,

order IRF6604TR1

REEL DIMENSIONS

STANDARD OPTION (QTY 4800) TR1 OPTION (QTY 1000)

METRIC

IMPERIAL

METRIC

MIN MAX

IMPERIAL

CODE

MIN

MAX

N.C

MIN

MAX

N.C

0.50

N.C

0.53

N.C

MIN

330.0

20.2

12.8

1.5

MAX

N.C

13.2

N.C

18.4

14.4

15.4

A

B

C

D

E

F

12.992

0.795

0.504

0.059

3.937

N.C

6.9

177.77 N.C

0.75

0.53

0.059

2.31

N.C

19.06

13.5

1.5

N.C

0.520

N.C

12.8

N.C

100.0

N.C

58.72

N.C

0.724

0.567

0.606

13.50

12.01

G

H

0.488

0.469

0.47

12.4

11.9

LOADED TAPE FEED DIRECTION

DIMENSIONS

METRIC

IMPERIAL

CODE

MIN

MAX

0.319

0.161

0.484

0.219

0.209

0.264

N.C

MIN

7.90

3.90

11.90

5.45

5.10

6.50

1.50

MAX

8.10

4.10

12.30

5.55

5.30

6.70

N.C

A

B

C

D

E

F

0.311

0.154

0.469

0.215

0.201

0.256

0.059

G

H

1.60

0.063

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11

IRF6604

DirectFET Part Marking

Notes:

Surface mounted on 1 in. square Cu board.

ꢀ Used double sided cooling , mounting pad.

Mounted on minimum footprint full size board with metalized

back and with small clip heatsink.

Repetitive rating; pulse width limited by

max. junction temperature.

Starting T_J= 25°C, L = 0.70mH

R_G= 25Ω, I_AS= 9.6A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

T_Cmeasured with thermal couple mounted to top (Drain) of

part.

R is measured at T_Jof approximately 90°C.

θ

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 11/05

12

www.irf.com

Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/


型号：	IRF6604TR1
厂家：	Infineon
描述：	Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET
文件：	总13页 (文件大小：626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRF6604TR1 [INFINEON]

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