IRF7749L1TRPBF_技术文档

IRF7749L1TRPbF

Applications

l RoHS Compliant, Halogen Free

l Lead-Free (Qualified up to 260°C Reflow)

DirectFET Power MOSFET

Typical values (unless otherwise specified)

V_DSS

V_GS

R_DS(on)

1.1mΩ@ 10V

V_gs(th)

l Ideal for High Performance Isolated Converter

Primary Switch Socket

l Optimized for Synchronous Rectification

60V min ±20V max

Q_{g tot}

Q_gd

l Low Conduction Losses

200nC

71nC

2.9V

l High Cdv/dt Immunity

l Low Profile (<0.7mm)

S

l Dual Sided Cooling Compatible

l Compatible with existing Surface Mount Techniques

l Industrial Qualified

G

D

DirectFET ISOMETRIC

L8

Applicable DirectFET Outline and Substrate Outline

SB

SC

M2

M4

L4

L6

L8

Description

The IRF7749L1TRPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET^TMpackaging to achieve the

lowest on-state resistance in a package that has a footprint smaller than a D²PAK and only 0.7 mm profile. The DirectFET package is compatible

with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques,

when application noteAN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling

to maximize thermal transfer in power systems.

The IRF7749L1TRPbF is optimized for high frequency switching and synchronous rectification applications. The reduced total losses in the device

coupled with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliability improvements,

and makes this device ideal for high performance power converters.

Ordering Information

Standard Pack

Base part number

Package Type

Orderable Part Number

Form

Tape and Reel

Quantity

4000

IRF7749L1TRPbF

DirectFET Large Can

IRF7749L1TRPbF

Absolute Maximum Ratings

Max.

60

Parameter

Units

V

V_DS

Drain-to-Source Voltage

Gate-to-Source Voltage

±20

200

140

33

V

GS

(Silicon Limited)

(Package Limited)

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

I

@ T_C= 25°C

D

A

@ T_C= 100°C

@ T_A= 25°C

@ T_C= 25°C

375

800

260

120

DM

E_AS

I_AR

Single Pulse Avalanche Energy

Avalanche Current

mJ

A

1.60

1.40

1.20

1.00

0.80

12.0

10.0

8.0

V

= 6.0V

= 8.0V

= 10V

= 14V

T

= 25°C

I

= 120A

GS

C

D

6.0

T

= 25°C

J

4.0

= 125°C

J

2.0

0.0

40

80

120

160

200

4.0

6.0

V

8.0

10.0 12.0 14.0 16.0

I

, Drain Current (A)

, Gate-to-Source Voltage (V)

D

GS

Fig 1. Typical On-Resistance vs. Gate Voltage

Fig 2. Typical On-Resistance vs. Drain Current

Notes:

Click on this section to link to the appropriate technical paper.

Click on this section to link to the DirectFET Website.

Surface mounted on 1 in. square Cu board, steady state.

T_Cmeasured with thermocouple mounted to top (Drain) of part.

ꢀ Repetitive rating; pulse width limited by max. junction temperature.

Starting T_J= 25°C, L = 0.035mH, R_G= 25Ω, I_AS= 120A.

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February 18, 2013

IRF7749L1TRPbF

Static @ T_J= 25°C (unless otherwise specified)

Conditions

V_GS= 0V, I_D= 250μA

Parameter

Min. Typ. Max. Units

BV_DSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

Gate Threshold Voltage

60

–––

0.03

1.1

2.9

-10

–––

200

36

–––

V

Reference to 25°C, I_D= 2mA

V_GS= 10V, I_D= 120A

ΔΒV_DSS/ΔT_J

R_DS(on)

–––

2.0

––– V/°C

1.50

4.0

m

Ω

V_DS= V_GS, I_D= 250μA

V_GS(th)

V

/ T

_GS(th)Δ

Δ

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

–––

280

–––

––– mV/°C

J

V_DS= 60V, V_GS= 0V

I_DSS

20

250

100

-100

–––

300

–––

110

–––

μA

nA

S

V_DS= 48V, V_GS= 0V, T_J= 125°C

V_GS= 20V

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

V_GS= -20V

V_DS= 10V, I_D= 120A

gfs

Q_g

V_DS= 30V

Q_gs1

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

Gate Charge Overdrive

Switch Charge (Q_gs2+ Q_gd)

Output Charge

V_GS= 10V

Q_gs2

Q_gd

12

nC

I_D= 120A

See Fig. 9

71

Q_godr

100

83

Q_sw

V_DS= 16V, V_GS= 0V

Q_oss

R_G

67

nC

Gate Resistance

1.1

17

Ω

V_DD= 30V, V_GS= 10V

I_D= 120A

t_d(on)

t_r

t_d(off)

t_f

Turn-On Delay Time

–––

Rise Time

43

R_G=1.8Ω

Turn-Off Delay Time

78

ns

Fall Time

39

V_GS= 0V

C_iss

C_oss

C_rss

C_oss

Input Capacitance

––– 12320 –––

––– 1810 –––

V_DS= 25V

ƒ = 1.0MHz

Output Capacitance

pF

Reverse Transfer Capacitance

Output Capacitance

–––

850

–––

V

_GS= 0V, V_DS= 1.0V, f=1.0MHz

––– 8060 –––

––– 1310 –––

V_GS= 0V, V_DS= 120V, f=1.0MHz

Output Capacitance

Diode Characteristics

Conditions

MOSFET symbol

Parameter

Continuous Source Current

Min. Typ. Max. Units

I_S

–––

200

showing the

(Body Diode)

A

I_SM

integral reverse

Pulsed Source Current

(Body Diode)

–––

800

p-n junction diode.

T_J= 25°C, I_S= 120A, V_GS= 0V

T_J= 25°C, I_F= 120A, V_DD= 30V

di/dt = 100A/μs

V_SD

t_rr

Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

–––

45

1.3

68

V

ns

nC

Q_rr

78

120

Notes:

ꢀ Repetitive rating; pulse width limited by max. junction temperature.

Pulse width ≤ 400μs; duty cycle ≤ 2%.

2

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February 18, 2013

IRF7749L1TRPbF

Absolute Maximum Ratings

Parameter

Max.

Units

Power Dissipation

125

W

P

@T_C= 25°C

@T_C= 100°C

@T_A= 25°C

D

P

J

63

3.3

Peak Soldering Temperature

Operating Junction and

270

°C

T

-55 to + 175

Storage Temperature Range

STG

Thermal Resistance

Parameter

Typ.

–––

12.5

20

Max.

45

Units

R_θ

Junction-to-Ambient

JA

Junction-to-Ambient

Junction-to-Can

–––

1.2

JA

°C/W

JA

–––

J-Can

J-PCB

Junction-to-PCB Mounted

0.4

10

1

D = 0.50

0.20

0.10

0.05

0.1

R₁

R₂

R₃

R₄

Ri (°C/W) τi (sec)

0.02

0.01

0.10804

0.61403

0.45202

0.00001

0.000171

0.053914

0.006099

0.036168

τ

^Jτ_J

τ

^Cτ

0.01

0.001

0.0001

¹τ₁

Ci= τi/Ri

τ

²τ₂

³τ₃

⁴τ₄

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

t

, Rectangular Pulse Duration (sec)

1

Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Notes:

Mounted on minimum footprint full size board with metalized

back and with small clip heatsink.

Surface mounted on 1 in. square Cu board, steady state.

T_Cmeasured with thermocouple incontact with top (Drain) of part.

Used double sided cooling, mounting pad with large heatsink.

R is measured at T_Jof approximately 90°C.

θ

Surface mounted on 1 in. square Cu

board (still air).

Mounted on minimum footprint full size board with metalized

back and with small clip heatsink. (still air)

3

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February 18, 2013

IRF7749L1TRPbF

1000

100

10

1000

100

10

VGS

15V

VGS

15V

10V

7.0V

5.0V

4.5V

4.3V

4.0V

3.8V

TOP

10V

7.0V

5.0V

4.5V

4.3V

4.0V

3.8V

BOTTOM

≤ 60μs PULSE WIDTH

1

Tj = 25°C

3.8V

60μs PULSE WIDTH

≤

Tj = 175°C

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 4. Typical Output Characteristics

Fig 5. Typical Output Characteristics

2.0

1.5

1.0

0.5

1000

I

= 120A

= 10V

D

V

GS

100

T

= 175°C

J

= 25°C

= -40°C

10

1

V

= 25V

DS

≤ 60μs PULSE WIDTH

0.1

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

-60 -40 -20

0

20 40 60 80 100 120 140 160 180

V

, Gate-to-Source Voltage (V)

GS

T

, Junction Temperature (°C)

J

Fig 6. Typical Transfer Characteristics

Fig 7. Normalized On-Resistance vs. Temperature

100000

14

V

C

= 0V,

f = 1 MHZ

GS

I

= 120A

= C + C , C SHORTED

D

iss

gs

gd ds

12

10

8

V

= 48V

= 30V

= 12V

C

= C

DS

rss

gd

C

= C + C

ds

oss

gd

Ciss

10000

1000

100

6

Coss

Crss

4

2

0

40

Q

80

120 160 200 240 280

1

10

100

Total Gate Charge (nC)

G

V

, Drain-to-Source Voltage (V)

DS

Fig 9. Typical Total Gate Charge vs

Fig 8. Typical Capacitance vs.Drain-to-Source Voltage

Gate-to-Source Voltage

4

February 18, 2013

IRF7749L1TRPbF

10000

1000

100

10

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R

(on)

DS

100μsec

1msec

T

= 175°C

= 25°C

= -40°C

J

DC

10msec

1

Tc = 25°C

Tj = 175°C

Single Pulse

V

= 0V

GS

0.1

1

0

1

10

100

0.2

0.4

V

0.6

0.8

1.0

1.2

1.4

V

, Drain-toSource Voltage (V)

, Source-to-Drain Voltage (V)

DS

SD

Fig 10. Typical Source-Drain Diode Forward Voltage

Fig11. Maximum Safe Operating Area

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

200

I

= 1.0A

D

= 1.0mA

= 250μA

160

120

80

40

0

25

50

75

100

125

150

175

-75 -50 -25

0

J

25 50 75 100 125 150 175

, Temperature ( °C )

T

, CaseTemperature (°C)

T

C

Fig 13. Typical Threshold Voltage vs.

Fig 12. Maximum Drain Current vs. Case Temperature

Junction Temperature

1200

I

D

TOP

20A

31A

1000

800

600

400

200

0

BOTTOM 120A

25

50

75

100

125

150

175

Starting T , Junction Temperature (°C)

J

Fig 14. Maximum Avalanche Energy Vs. Drain Current

5

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February 18, 2013

IRF7749L1TRPbF

1000

100

10

Allowed avalanche Current vs avalanche

Duty Cycle = Single Pulse

pulsewidth, tav, assuming Tj = 150°C and

Δ

Tstart =25°C (Single Pulse)

0.01

0.05

0.10

Allowed avalanche Current vs avalanche

1

pulsewidth, tav, assuming

Tstart = 150°C.

j = 25°C and

ΔΤ

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T_jmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 19a, 19b.

4. P_{D (ave)}= Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

280

240

200

160

120

80

TOP

BOTTOM 1% Duty Cycle

= 120A

Single Pulse

I

D

6. I_av= Allowable avalanche current.

7. ΔT = Allowable rise in junction temperature, not to exceed

T_jmax(assumed as 25°C in Figure 15, 16).

t_{av =}Average time in avalanche.

40

0

D = Duty cycle in avalanche = t_av·f

25

50

75

100

125

150

175

Z_thJC(D, t_av) = Transient thermal resistance, see figure 11)

Starting T , Junction Temperature (°C)

J

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

Fig 16. Maximum Avalanche Energy Vs. Temperature

I_av= 2DT/ [1.3·BV·Z_th]

E_{AS (AR)}= P_{D (ave)}·t_a

Driver Gate Drive

P.W.

D.U.T

Period

D =

Period

P.W.

+

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

-

D.U.T. I Waveform

SD

+

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

-

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

• di/dt controlled by R_G

Re-Applied

Voltage

R_G

+

-

• Driver same type as D.U.T.

Body Diode

Inductor Current

Forward Drop

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

I

SD

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 17. Diode Reverse Recovery Test Circuit for N-Channel HEXFET^®Power MOSFETs

6

IRF7749L1TRPbF

Id

Vds

Vgs

L

VCC

DUT

0

Vgs(th)

20K

1K

Qgs1

Qgs2

Qgodr

Qgd

Fig 18a. Gate Charge Test Circuit

Fig 18b. Gate Charge Waveform

V

(BR)DSS

15V

t

p

DRIVER

+

L

V

DS

V

R

D.U.T

AS

GS

G

V

DD

-

I

A

20V

t

0.01Ω

p

I

AS

Fig 19b. Unclamped Inductive Waveforms

Fig 19a. Unclamped Inductive Test Circuit

R_D

V_DS

V

DS

90%

V_GS

D.U.T.

R_G

+

V_DD

-

10V

V_GS

10%

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

V

GS

t

r

t

f

d(on)

d(off)

Fig 20a. Switching Time Test Circuit

Fig 20b. Switching Time Waveforms

7

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February 18, 2013

IRF7749L1TRPbF

DirectFET Board Footprint, L8 (Large Size Can).

Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations

G = GATE

D = DRAIN

S = SOURCE

D

S

G

Note: For the most current drawing please refer to IR website at http://www.irf.com/package

8

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February 18, 2013

IRF7749L1TRPbF

DirectFET Outline Dimension, L8 Outline (LargeSize Can).

Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations

DIMENSIONS

METRIC

IMPERIAL

CODE MIN MAX

MIN MAX

9.05 9.15 0.356 0.360

6.85 7.10 0.270 0.280

5.90 6.00 0.232 0.236

0.55 0.65 0.022 0.026

0.58 0.62 0.023 0.024

1.18 1.22 0.046 0.048

0.98 1.02 0.039 0.040

0.73 0.77 0.029 0.030

0.38 0.42 0.015 0.017

1.35 1.45 0.053 0.057

2.55 2.65 0.100 0.104

5.35 5.45 0.211 0.215

0.68 0.74 0.027 0.029

0.09 0.17 0.003 0.007

0.02 0.08 0.001 0.003

A

B

C

D

E

F

G

H

J

K

L

L1

M

P

R

DirectFET Part Marking

GATE MARKING

LOGO

+

PART NUMBER

BATCH NUMBER

DATE CODE

Line above the last character of

the date code indicates "Lead-Free"

Note: For the most current drawing please refer to IR website at http://www.irf.com/package

9

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February 18, 2013

IRF7749L1TRPbF

DirectFET Tape & Reel Dimension (Showing component orientation).

LOADED TAPE FEED DIRECTION

+

NOTE:

Controlling dimensions in mm

Std reel quantity is 4000 parts. (ordered as IRF7749L1TRPBF).

REEL DIMENSIONS

STANDARD OPTION (QTY 4000)

DIMENSIONS

METRIC

IMPERIAL

NOTE: CONTROLLING

DIMENSIONS IN MM

METRIC

IMPERIAL

CODE

MIN

11.90

3.90

15.90

7.40

7.20

9.90

1.50

MAX

12.10

4.10

MAX

0.476

0.161

0.642

0.299

0.291

0.398

N.C

CODE

MIN

MAX

N.C

MAX

N.C

4.69

0.154

0.623

0.291

0.283

0.390

0.059

A

B

C

D

E

F

A

B

C

D

E

F

12.992

0.795

0.504

0.059

3.900

N.C

330.00

20.20

12.80

1.50

N.C

16.30

7.60

7.40

10.10

N.C

13.20

N.C

0.520

N.C

99.00

N.C

3.940

0.880

0.720

0.760

100.00

22.40

18.40

19.40

G

H

0.650

0.630

16.40

15.90

G

H

0.063

1.60

Note: For the most current drawing please refer to IR website at http://www.irf.com/package

Qualification Information^†

Industrial ^{†† *}

Qualification level

MSL1

Moisture Sensitivity Level

RoHS Compliant

DirectFET

(per JEDEC J-STD-020D^†††

)

Yes

Qualification standards can be found at International Rectifier’s web site

http://www.irf.com/product-info/reliability

Higher qualification ratings may be available should the user have such requirements.

Please contact your International Rectifier sales representative for further information:

http://www.irf.com/whoto-call/salesrep/

Applicable version of JEDEC standard at the time of product release.

* Industrial qualification standards except autoclave test conditions.

Revision History

Date

Comments

2/13/2013

TR1 option removed and Tape & Reel Info updated accordingly. Hyperlinks added throw-out the document

IR WORLD HEADQUARTERS: 101N Sepulveda Blvd, El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

10

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February 18, 2013


型号：	IRF7749L1TRPBF
厂家：	Infineon
描述：	DirectFETPower MOSFET
文件：	总10页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRF7749L1TRPBF [INFINEON]

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