IRF7946PBF [INFINEON]

Brushed Motor drive applications;
IRF7946PBF
型号: IRF7946PBF
厂家: Infineon    Infineon
描述:

Brushed Motor drive applications

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中文:  中文翻译
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StrongIRFET™  
IRF7946PbF  
DirectFET® Power MOSFET  
Applications  
l Brushed Motor drive applications  
l BLDC Motor drive applications  
l Battery powered circuits  
l Half-bridge and full-bridge topologies  
l Synchronous rectifier applications  
l Resonant mode power supplies  
l OR-ing and redundant power switches  
l DC/DC and AC/DC converters  
l DC/AC Inverters  
VDSS  
RDS(on) typ.  
max.  
40V  
1.1m  
1.4m  
Ω
Ω
ID  
198A  
90A  
(Silicon Limited)  
ID  
(Package Limited)  
G
S
S
D
D
Benefits  
l Improved Gate, Avalanche and Dynamic dV/dt  
Ruggedness  
DirectFET™ ISOMETRIC  
MX  
l Fully Characterized Capacitance and Avalanche  
SOA  
l Enhanced body diode dV/dt and dI/dt Capability  
l RoHS Compliant Containing no Lead, no Bromide  
and no Halogen  
Standard Pack  
Form  
Tape and Reel  
Base part number  
Package Type  
Complete Part Number  
Quantity  
IRF7946TRPbF  
DirectFET MX  
4800  
IRF7946TRPbF  
6.0  
4.0  
2.0  
0.0  
200  
150  
100  
50  
I
= 90A  
D
Limited By Package  
T
= 125°C  
J
T
= 25°C  
J
0
4
6
8
10  
12 14 16  
18 20  
25  
50  
75  
, Case Temperature (°C)  
C
100  
125  
150  
T
V
Gate -to -Source Voltage (V)  
GS,  
Fig 2. Maximum Drain Current vs. Case Temperature  
Submit Datasheet Feedback November 25, 2014  
Fig 1. Typical On-Resistance vs. Gate Voltage  
1
www.irf.com © 2014 International Rectifier  
IRF7946PbF  
Absolute Maximum Ratings  
Symbol  
ID @ TC = 25°C  
ID @ TC = 100°C  
IDM  
Parameter  
Max.  
198  
Units  
Continuous Drain Current, VGS @ 10V (Silicon Limited)  
Continuous Drain Current, VGS @ 10V (Silicon Limited)  
Pulsed Drain Current  
125  
A
793  
Maximum Power Dissipation  
Linear Derating Factor  
96  
PD @TC = 25°C  
W
W/°C  
V
0.77  
Gate-to-Source Voltage  
± 20  
VGS  
Operating Junction and  
-55 to + 150  
TJ  
°C  
Storage Temperature Range  
TSTG  
Avalanche Characteristics  
Single Pulse Avalanche Energy  
Single Pulse Avalanche Energy  
Avalanche Current  
EAS (Thermally limited)  
85  
mJ  
EAS (Thermally limited)  
200  
IAR  
See Fig. 14, 15, 22a, 22b  
A
Repetitive Avalanche Energy  
EAR  
mJ  
Thermal Resistance  
Symbol  
Parameter  
Junction-to-Ambient  
Junction-to-Ambient  
Junction-to-Ambient  
Junction-to-Case  
Typ.  
–––  
12.5  
20  
Max.  
45  
Units  
RθJA  
–––  
–––  
1.3  
RθJA  
°C/W  
RθJA  
RθJC  
–––  
1.0  
Junction-to-PCB Mounted  
–––  
RθJA-PCB  
Static @ TJ = 25°C (unless otherwise specified)  
Symbol  
Parameter  
Min.  
40  
Typ.  
–––  
0.03  
1.1  
Max. Units  
Conditions  
VGS = 0V, ID = 250μA  
V/°C Reference to 25°C, ID = 1.0mA  
V(BR)DSS  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
Static Drain-to-Source On-Resistance  
–––  
–––  
1.4  
V
ΔV(BR)DSS/ΔTJ  
–––  
–––  
mΩ  
mΩ  
V
RDS(on)  
VGS = 10V, ID = 90A  
GS = 6.0V, ID = 72A  
VDS = VGS, ID = 150μA  
DS = 40V, VGS = 0V  
DS = 40V, VGS = 0V, TJ = 125°C  
VGS = 20V  
GS = -20V  
1.7  
–––  
3.9  
V
VGS(th)  
IDSS  
Gate Threshold Voltage  
2.2  
–––  
–––  
–––  
–––  
–––  
3.0  
Drain-to-Source Leakage Current  
–––  
–––  
–––  
–––  
0.67  
1.0  
μA  
V
150  
100  
-100  
–––  
V
IGSS  
RG  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Internal Gate Resistance  
nA  
V
Ω
Notes:  
 TC measured with thermocouple mounted to top (Drain) of part.  
 Mounted on minimum footprint full size board with metalized  
back and with small clip heatsink.  
Ž Used double sided cooling , mounting pad with large heatsink.  
 Mounted on minimum  
footprint full size board with  
metalized back and with small  
 Mounted to a PCB with  
small clip heatsink (still air)  
Œ Surface mounted on 1 in. square Cu  
clip heatsink (still air)  
(still air).  
2
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November 25, 2014  
IRF7946PbF  
Dynamic @ TJ = 25°C (unless otherwise specified)  
Symbol Parameter  
Forward Transconductance  
Min.  
91  
Typ.  
–––  
141  
36  
Max. Units  
Conditions  
gfs  
–––  
212  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
S
VDS = 10V, ID = 90A  
ID = 90A  
Qg  
Total Gate Charge  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
nC  
Qgs  
Qgd  
Qsync  
td(on)  
tr  
Gate-to-Source Charge  
Gate-to-Drain ("Miller") Charge  
Total Gate Charge Sync. (Qg - Qgd  
Turn-On Delay Time  
Rise Time  
V
V
DS =20V  
GS = 10V  
44  
)
97  
ID = 90A, VDS =0V, VGS = 10V  
VDD = 20V  
20  
ns  
49  
ID = 30A  
td(off)  
tf  
Turn-Off Delay Time  
Fall Time  
54  
R
G = 2.7Ω  
41  
VGS = 10V  
Ciss  
Coss  
Crss  
Input Capacitance  
6852  
1046  
735  
1307  
1465  
pF  
VGS = 0V  
Output Capacitance  
Reverse Transfer Capacitance  
VDS = 25V  
ƒ = 1.0 MHz  
Effective Output Capacitance (Energy Related)  
Effective Output Capacitance (Time Related)  
Coss eff. (ER)  
Coss eff. (TR)  
V
GS = 0V, VDS = 0V to 32V  
VGS = 0V, VDS = 0V to 32V  
Diode Characteristics  
Symbol  
Parameter  
Min.  
Typ.  
Max. Units  
Conditions  
D
S
96  
IS  
Continuous Source Current  
–––  
–––  
A
A
V
MOSFET symbol  
(Body Diode)  
showing the  
G
ISM  
Pulsed Source Current  
–––  
–––  
793  
integral reverse  
(Body Diode)  
p-n junction diode.  
VSD  
dv/dt  
trr  
Diode Forward Voltage  
Peak Diode Recovery  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
0.75  
1.6  
49  
1.2  
–––  
–––  
–––  
–––  
–––  
–––  
TJ = 25°C, IS = 90A, VGS = 0V  
V/ns TJ = 175°C, IS = 90A, VDS = 40V  
Reverse Recovery Time  
Reverse Recovery Charge  
Reverse Recovery Current  
ns  
nC  
A
TJ = 25°C  
TJ = 125°C  
TJ = 25°C  
TJ = 125°C  
TJ = 25°C  
VR = 34V,  
50  
IF = 90A  
di/dt = 100A/μs  
Qrr  
74  
73  
IRRM  
2.6  
Notes:  
Pulse width 400μs; duty cycle 2%.  
† Coss eff. (TR) is a fixed capacitance that gives the same charging time  
as Coss while VDS is rising from 0 to 80% VDSS  
‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as  
Coss while VDS is rising from 0 to 80% VDSS  
Calculated continuous current based on maximum allowable  
junction temperature. Package limit is 90A.  
‚ Repetitive rating; pulse width limited by max. junction  
temperature.  
.
.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.021mH  
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom  
mended footprint and soldering techniques refer to application note #AN-994.  
‰ Rθ is measured at TJ approximately 90°C.  
RG = 50Ω, IAS = 90A, VGS =10V.  
„ ISD 90A, di/dt 1135A/μs, VDD V(BR)DSS, TJ 150°C.  
Š Limited by TJmax starting TJ = 25°C, L= 1mH, RG = 50Ω, IAS = 20A, VGS =10V  
3
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November 25, 2014  
IRF7946PbF  
1000  
100  
10  
1000  
100  
10  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
4.5V  
VGS  
15V  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
4.5V  
TOP  
TOP  
BOTTOM  
BOTTOM  
4.5V  
4.5V  
60μs PULSE WIDTH  
60μs PULSE WIDTH  
Tj = 150°C  
Tj = 25°C  
1
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
V
, Drain-to-Source Voltage (V)  
DS  
DS  
Fig 3. Typical Output Characteristics  
Fig 4. Typical Output Characteristics  
1000  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
I
= 90A  
D
V
= 10V  
GS  
100  
10  
T = 150°C  
J
T
= 25°C  
J
V
= 10V  
DS  
60μs PULSE WIDTH  
1.0  
2
3
4
5
6
7
8
-60 -40 -20  
0
20 40 60 80 100 120140 160  
T
J
, Junction Temperature (°C)  
V
, Gate-to-Source Voltage (V)  
GS  
Fig 6. Normalized On-Resistance vs. Temperature  
Fig 5. Typical Transfer Characteristics  
100000  
10000  
1000  
14.0  
V
= 0V,  
= C  
f = 1 MHZ  
GS  
I = 90A  
D
C
C
C
+ C , C  
SHORTED  
ds  
iss  
gs  
gd  
12.0  
= C  
rss  
oss  
gd  
= C + C  
V
V
= 32V  
= 20V  
DS  
DS  
ds  
gd  
10.0  
8.0  
6.0  
4.0  
2.0  
0.0  
C
iss  
C
C
oss  
rss  
100  
1
10  
, Drain-to-Source Voltage (V)  
100  
0
20 40 60 80 100 120 140 160 180  
, Total Gate Charge (nC)  
V
DS  
Q
G
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage  
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage  
November 25, 2014  
4
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IRF7946PbF  
1000  
100  
10  
10000  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R  
(on)  
DS  
100μsec  
T
= 150°C  
1msec  
J
Limited by  
Package  
10msec  
DC  
T
= 25°C  
J
1
Tc = 25°C  
0.1  
Tj = 150°C  
Single Pulse  
V
GS  
= 0V  
1.0  
0.01  
0.1  
1
10  
100  
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6  
, Source-to-Drain Voltage (V)  
V
, Drain-to-Source Voltage (V)  
V
DS  
SD  
Fig 10. Maximum Safe Operating Area  
Fig 9. Typical Source-Drain Diode  
Forward Voltage  
1.4  
48  
47  
46  
45  
44  
43  
42  
41  
40  
Id = 1.0mA  
V
= 0V to 32V  
DS  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
0
5
10 15 20 25 30 35 40 45  
Drain-to-Source Voltage (V)  
-60 -40 -20  
0
20 40 60 80 100 120140 160  
T , Temperature ( °C )  
J
V
DS,  
Fig 11. Drain-to-Source Breakdown Voltage  
Fig 12. Typical COSS Stored Energy  
10.0  
V
= 5.5V  
= 6.0V  
= 7.0V  
= 8.0V  
=10V  
GS  
GS  
GS  
GS  
GS  
V
V
V
V
8.0  
6.0  
4.0  
2.0  
0.0  
0
200  
400  
600  
800  
1000  
I , Drain Current (A)  
D
Fig 13. Typical On-Resistance vs. Drain Current  
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November 25, 2014  
IRF7946PbF  
10  
1
D = 0.50  
0.20  
0.10  
0.05  
0.1  
0.02  
0.01  
0.01  
Notes:  
1. Duty Factor D = t1/t2  
2. Peak Tj = P dm x Zthjc + Tc  
SINGLE PULSE  
( THERMAL RESPONSE )  
0.001  
1E-006  
1E-005  
0.0001  
0.001  
0.01  
0.1  
t
, Rectangular Pulse Duration (sec)  
1
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
1000  
100  
10  
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assuming ΔTj = 125°C and  
Tstart =25°C (Single Pulse)  
1
Allowed avalanche Current vs avalanche  
pulsewidth, tav, assumingΔΤ j = 25°C and  
Tstart = 125°C.  
0.1  
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 15. Typical Avalanche Current vs.Pulsewidth  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:  
(For further info, see AN-1005 at www.irf.com)  
1. Avalanche failures assumption:  
Purely a thermal phenomenon and failure occurs at a temperature far in  
excess of Tjmax. This is validated for every part type.  
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.  
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.  
4. PD (ave) = Average power dissipation per single avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase  
during avalanche).  
6. Iav = Allowable avalanche current.  
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as  
25°C in Figure 14, 15).  
tav = Average time in avalanche.  
D = Duty cycle in avalanche = tav ·f  
TOP  
BOTTOM 1.0% Duty Cycle  
= 90A  
Single Pulse  
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)  
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC  
Iav = 2DT/ [1.3·BV·Zth]  
25  
50  
75  
100  
125  
150  
EAS (AR) = PD (ave)·tav  
Starting T , Junction Temperature (°C)  
J
Fig 16. Maximum Avalanche Energy vs. Temperature  
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November 25, 2014  
IRF7946PbF  
16  
14  
12  
10  
8
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
I = 54A  
F
V
= 34V  
R
T = 25°C  
J
T = 125°C  
J
I
I
I
= 150μA  
= 1.0mA  
= 1.0A  
D
D
D
6
4
2
0
0
200  
400  
600  
800  
1000  
-75 -50 -25  
0
25 50 75 100 125 150  
di /dt (A/μs)  
T , Temperature ( °C )  
F
J
Fig. 18 - Typical Recovery Current vs. dif/dt  
Fig 17. Threshold Voltage vs. Temperature  
16  
350  
I = 90A  
F
I = 54A  
F
14  
V
= 34V  
V
= 34V  
R
R
300  
250  
200  
150  
100  
50  
T = 25°C  
T = 25°C  
J
J
12  
10  
8
T = 125°C  
J
T = 125°C  
J
6
4
2
0
0
200  
400  
600  
800  
1000  
0
200  
400  
600  
800  
1000  
di /dt (A/μs)  
di /dt (A/μs)  
F
F
Fig. 19 - Typical Recovery Current vs. dif/dt  
Fig. 20 - Typical Stored Charge vs. dif/dt  
400  
I = 90A  
F
V
350  
300  
250  
200  
150  
100  
50  
= 34V  
R
T = 25°C  
J
T = 125°C  
J
0
200  
400  
600  
800  
1000  
di /dt (A/μs)  
F
Fig. 21 - Typical Stored Charge vs. dif/dt  
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November 25, 2014  
IRF7946PbF  
Driver Gate Drive  
P.W.  
P.W.  
Period  
D.U.T  
Period  
D =  
+
ƒ
-
*
=10V  
V
GS  
Circuit Layout Considerations  
Low Stray Inductance  
Ground Plane  
Low Leakage Inductance  
Current Transformer  
D.U.T. I Waveform  
SD  
+
‚
-
Reverse  
Recovery  
Current  
Body Diode Forward  
„
Current  
di/dt  
-
+
D.U.T. V Waveform  
DS  
Diode Recovery  
dv/dt  

V
DD  
VDD  
Re-Applied  
Voltage  
dv/dt controlled by RG  
RG  
+
-
Body Diode  
Forward Drop  
Driver same type as D.U.T.  
ISD controlled by Duty Factor "D"  
D.U.T. - Device Under Test  
Inductor Current  
I
SD  
Ripple  
5%  
* VGS = 5V for Logic Level Devices  
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel  
HEXFET® Power MOSFETs  
V
(BR)DSS  
15V  
t
p
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
-
I
A
VGS  
Ω
0.01  
t
p
I
AS  
Fig 22b. Unclamped Inductive Waveforms  
Fig 22a. Unclamped Inductive Test Circuit  
RD  
VDS  
V
DS  
90%  
VGS  
D.U.T.  
RG  
+
VDD  
-
VGS  
10%  
Pulse Width ≤ 1 µs  
Duty Factor ≤ 0.1 %  
V
GS  
t
t
r
t
t
f
d(on)  
d(off)  
Fig 23a. Switching Time Test Circuit  
Fig 23b. Switching Time Waveforms  
Id  
Current Regulator  
Same Type as D.U.T.  
Vds  
Vgs  
50KΩ  
.2μF  
12V  
.3μF  
+
V
DS  
D.U.T.  
-
Vgs(th)  
V
GS  
3mA  
I
I
D
G
Qgs1  
Qgs2  
Qgd  
Qgodr  
Current Sampling Resistors  
Fig 24a. Gate Charge Test Circuit  
Fig 24b. Gate Charge Waveform  
Submit Datasheet Feedback November 25, 2014  
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IRF7946PbF  
DirectFET® Board Footprint, MX Outline  
(Medium Size Can, X-Designation).  
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.  
This includes all recommendations for stencil and substrate designs.  
G=GATE  
D=DRAIN  
S=SOURCE  
D
D
D
D
S
S
G
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/  
9
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November 25, 2014  
IRF7946PbF  
DirectFET® Outline Dimension, MX Outline  
(Medium Size Can, X-Designation).  
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes  
all recommendations for stencil and substrate designs.  
DIMENSIONS  
METRIC  
IMPERIAL  
CODE MIN MAX  
MIN MAX  
A
B
C
D
E
F
6.25 6.35 0.246 0.250  
4.80 5.05 0.189 0.199  
3.85 3.95 0.152 0.156  
0.35 0.45 0.014 0.018  
0.68 0.72 0.027 0.028  
0.68 0.72 0.027 0.028  
1.38 1.42 0.054 0.056  
0.80 0.84 0.031 0.033  
0.38 0.42 0.015 0.017  
0.88 1.02 0.035 0.040  
2.28 2.42 0.090 0.095  
0.59 0.70 0.023 0.028  
0.03 0.08 0.001 0.003  
0.08 0.17 0.003 0.007  
G
H
J
K
L
M
R
P
Dimensions are shown in  
millimeters (inches)  
DirectFET® Part Marking  
GATE MARKING  
LOGO  
PART NUMBER  
BATCH NUMBER  
DATE CODE  
Line above the last character of  
the date code indicates "Lead-Free"  
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/  
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November 25, 2014  
IRF7946PbF  
DirectFET® Tape & Reel Dimension (Showing component orientation).  
NOTE: Controlling dimensions in mm Std reel.  
quantity is 4800 parts. (ordered as IRF7946PBF).  
REEL DIMENSIONS  
STANDARD OPTION(QTY 4800)  
METRIC  
IMPERIAL  
CODE  
MIN  
MIN  
MAX  
N.C  
N.C  
13.2  
N.C  
N.C  
18.4  
14.4  
15.4  
MAX  
N.C  
A
B
C
D
E
F
12.992  
0.795  
0.504  
0.059  
3.937  
N.C  
330.0  
20.2  
12.8  
1.5  
N.C  
0.520  
N.C  
100.0  
N.C  
N.C  
0.724  
0.567  
0.606  
G
H
0.488  
0.469  
12.4  
11.9  
DIMENSIONS  
METRIC  
IMPERIAL  
NOTE: CONTROLLING  
DIMENSIONS IN MM  
CODE  
MIN  
MIN  
7.90  
3.90  
MAX  
0.319  
0.161  
0.484  
0.219  
0.209  
0.264  
N.C  
MAX  
8.10  
4.10  
0.311  
0.154  
0.469  
0.215  
0.201  
0.256  
0.059  
0.059  
A
B
C
D
E
F
11.90 12.30  
5.45  
5.10  
6.50  
1.50  
1.50  
5.55  
5.30  
6.70  
N.C  
1.60  
G
H
0.063  
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/  
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November 25, 2014  
IRF7946PbF  
Qualification information†  
Consumer††  
Qualification level  
(per JEDEC JESD47F††† guidelines)  
MS L 1  
(per JEDEC J-STD-020D†††  
Moisture Sensitivity Level  
RoHS compliant  
DFET 1.5  
)
Yes  
† Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/  
†† Higher qualification ratings may be available should the user have such requirements. Please contact your  
International Rectifier sales representative for further information: http:www.irf.com/whoto-call/salesrep/  
††† Applicable version of JEDEC standard at the time of product release.  
Revision History  
Date  
Comment  
Updated data sheet based on corporate template.  
Updated Qual level from "MSL3" to "MSL1" on page12.  
5/7/2014  
Updated ordering information to reflect the End-Of-life (EOL) of the mini-reel option (EOL notice #264).  
Remove IRF7946TR1PBF quantity= 1000 from ordering table on page1.  
Remove continuous drain current package limt=90A from Absolute Maximum table-on page2  
Updated EAS (L =1mH) = 200mJ on page 2  
5/30/2014  
11/25/2014  
Ω
Updated note 10 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50 , IAS = 20A, VGS =10V”. on page 3  
θJA  
Updated R  
from “60°C/W” to “45°C/W” on page 2  
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA  
To contact International Rectifier, please visithttp://www.irf.com/whoto-call/  
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www.irf.com © 2014 International Rectifier  
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November 25, 2014  

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