IRFB3077GPBF [INFINEON]
High Efficiency Synchronous Rectification in SMPS; 高效率同步整流开关电源型号: | IRFB3077GPBF |
厂家: | Infineon |
描述: | High Efficiency Synchronous Rectification in SMPS |
文件: | 总8页 (文件大小:296K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 96200
IRFB3077GPbF
Applications
l High Efficiency Synchronous Rectification in SMPS
HEXFET® Power MOSFET
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
VDSS
RDS(on) typ.
75V
2.8m
3.3m
max.
Benefits
G
l Worldwide Best RDS(on) in TO-220
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
ID
ID
210A
(Silicon Limited)
120A
S
(Package Limited)
D
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
l Halogen-Free
S
D
G
TO-220AB
IRFB3077GPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
210
Units
A
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current
150
120
850
PD @TC = 25°C
W
370
Maximum Power Dissipation
2.5
Linear Derating Factor
W/°C
V
VGS
± 20
Gate-to-Source Voltage
2.5
Peak Diode Recovery
dV/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbf in (1.1N m)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
200
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.402
–––
Units
RθJC
Junction-to-Case
RθCS
RθJA
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
62
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1
12/05/08
IRFB3077GPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
75 ––– –––
––– 0.091 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
2.8
3.3
4.0
20
VGS = 10V, ID = 75A
mΩ
V
VGS(th)
–––
VDS = VGS, ID = 250µA
IDSS
Drain-to-Source Leakage Current
––– –––
VDS = 75V, VGS = 0V
µA
––– ––– 250
––– ––– 100
––– ––– -100
VDS = 75V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
VGS = 20V
GS = -20V
f = 1MHz, open drain
nA
V
RG
–––
1.2
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 75A
160 ––– –––
S
Qg
Total Gate Charge
––– 160 220
ID = 75A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
–––
–––
–––
–––
–––
–––
37
42
25
87
69
95
–––
–––
–––
–––
–––
–––
V
DS = 38V
VGS = 10V
DD = 38V
nC
V
Rise Time
ID = 75A
ns
td(off)
tf
Turn-Off Delay Time
RG = 2.1Ω
VGS = 10V
Fall Time
Ciss
Coss
Crss
Input Capacitance
––– 9400 –––
––– 820 –––
––– 350 –––
––– 1090 –––
––– 1260 –––
V
GS = 0V
Output Capacitance
VDS = 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0MHz,See Fig. 5
pF
Coss eff. (ER)
oss eff. (TR)
VGS = 0V, VDS = 0V to 60V , See Fig.11
C
VGS = 0V, VDS = 0V to 60V
,
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max. Units
Conditions
MOSFET symbol
IS
D
S
––– –––
210
(Body Diode)
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
––– ––– 850
integral reverse
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
63
V
TJ = 25°C, IS = 75A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 64V,
IF = 75A
di/dt = 100A/µs
–––
–––
–––
–––
–––
42
50
59
86
2.5
ns
75
Qrr
Reverse Recovery Charge
89
nC
A
130
–––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
ꢀ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
.
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
Rθ is measured at TJ approximately 90°C
Limited by TJmax, starting TJ = 25°C, L = 0.028mH
RG = 25Ω, IAS = 120A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 75A, di/dt ≤ 400A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
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IRFB3077GPbF
1000
100
10
1000
100
10
VGS
15V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
≤
Tj = 25°C
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
V
= 25V
DS
≤ 60µs PULSE WIDTH
1
2.0
3.0
4.0
5.0
6.0
7.0
8.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
16000
12000
8000
4000
0
20
V
C
= 0V,
f = 1 MHZ
I = 75A
D
GS
= C + C , C SHORTED
iss
gs
gd ds
V
= 60V
DS
C
= C
rss
gd
16
12
8
VDS= 38V
VDS= 17V
C
= C + C
ds
oss
gd
Ciss
4
Coss
Crss
0
0
40
80
120 160 200 240 280
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB3077GPbF
1000.0
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100.0
10.0
1.0
100µsec
1msec
LIMITED BY PACKAGE
T
= 25°C
J
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.1
1.0
10.0
100.0
0.0
0.4
0.8
1.2
1.6
2.0
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
100
240
200
160
120
80
LIMITED BY PACKAGE
90
80
70
40
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1000
I
D
TOP
22A
40A
BOTTOM 120A
800
600
400
200
0
0
20
40
60
80
25
50
75
100
125
150
175
V
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
DS,
J
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB3077GPbF
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
R1
0.01
0.02
0.01
τ
J τJ
τ
τ
Cτ
0.0766 0.000083
0.1743 0.000995
0.1513 0.007038
τ
1τ1
τ
2 τ2
3τ3
Ci= τi/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
240
200
160
120
80
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1% Duty Cycle
= 120A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
40
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB3077GPbF
4.0
24
20
16
12
8
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250µA
3.0
2.0
1.0
I
= 30A
F
V
= 64V
R
4
T
= 125°C
= 25°C
J
T
J
0
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900 1000
T
di / dt - (A / µs)
f
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
400
24
20
16
12
8
300
200
I
= 30A
= 64V
I
= 45A
= 64V
F
F
100
0
V
V
R
R
4
0
T
= 125°C
= 25°C
T
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / µs)
f
di / dt - (A / µs)
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
400
300
200
100
0
I
= 45A
= 64V
F
V
T
R
= 125°C
= 25°C
J
T
J
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / µs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB3077GPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFB3077GPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/2008
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8
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