IRFP7718PBF [INFINEON]
Brushed Motor drive applications;
| 型号： | IRFP7718PBF |
| 厂家： | 
Infineon |
| 描述： | Brushed Motor drive applications |
| 文件： | 总10页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
StrongIRFET™
IRFP7718PbF
Application
HEXFET® Power MOSFET
Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
VDSS
75V
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC Inverters
RDS(on) typ.
1.45m
1.80m
355A
max
ID (Silicon Limited)
ID (Package Limited)
195A
D
Benefits
S
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free, RoHS Compliant
D
G
TO-247AC
G
D
S
Gate
Drain
Source
Standard Pack
Orderable Part Number
Base part number Package Type
Form
Quantity
IRFP7718PbF
TO-247
Tube
25
IRFP7718PbF
400
300
200
100
6
4
2
I
= 100A
D
Limited By Package
T = 125°C
J
T = 25°C
J
0
4
0
8
12
16
20
25
50
75
100
125
150
175
V
, Gate-to-Source Voltage (V)
GS
T
, Case Temperature (°C)
C
Fig 2. Maximum Drain Current vs. Case Temperature
Fig 1. Typical On-Resistance vs. Gate Voltage
1
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IRFP7718PbF
Absolute Maximium Rating
Symbol
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
355
250
195
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
A
ID @ TC = 25°C
IDM
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current
1590
517
PD @TC = 25°C
Maximum Power Dissipation
W
W/°C
V
Linear Derating Factor
3.5
VGS
Gate-to-Source Voltage
± 20
TJ
TSTG
Operating Junction and
Storage Temperature Range
-55 to + 175
°C
Soldering Temperature, for 10 seconds (1.6mm from case)
300
Mounting Torque, 6-32 or M3 Screw
10 lbf·in (1.1 N·m)
Avalanche Characteristics
EAS (Thermally limited)
EAS (Thermally limited)
IAR
EAR
1160
2004
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
mJ
See Fig 14, 15, 23a, 23b
Repetitive Avalanche Energy
Thermal Resistance
Symbol
Parameter
Typ.
–––
0.24
–––
Max.
0.29
–––
40
Units
Junction-to-Case
RJC
RCS
RJA
Case-to-Sink, Flat Greased Surface
°C/W
Junction-to-Ambient
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
75
––– –––
V
VGS = 0V, ID = 250µA
–––
42 ––– mV/°C Reference to 25°C, ID = 2mA
V(BR)DSS/TJ
RDS(on)
––– 1.45 1.80
––– 1.60 –––
2.1 –––
––– –––
––– ––– 150
––– ––– 100
––– ––– -100
V
V
GS = 10V, ID = 100A
GS = 6V, ID = 50A
m
V
VGS(th)
IDSS
Gate Threshold Voltage
3.7
1.0
VDS = VGS, ID = 250µA
DS =75 V, VGS = 0V
VDS =75V,VGS = 0V,TJ =125°C
V
Drain-to-Source Leakage Current
µA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
V
V
GS = 20V
GS = -20V
IGSS
RG
nA
–––
0.9
–––
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A.
Note that current limitations arising from heating of the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 233µH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 1279A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS
.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS
.
R is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 63A, VGS =10V. .
Pulse drain current is limited at 780A by source bonding technology.
2
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IRFP7718PbF
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ.
420 –––
––– 552
––– 119
––– 168
––– 384
Max. Units
Conditions
–––
830
–––
–––
–––
–––
–––
S
VDS = 10V, ID =100A
Qg
ID = 100A
VDS = 38V
VGS = 10V
Qgs
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg– Qgd)
Turn-On Delay Time
nC
Qgd
Qsync
td(on)
tr
–––
58
VDD = 38V
ID = 100A
Rise Time
––– 164
––– 266
––– 160
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
RG= 2.6
V
GS = 10V
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 29550 –––
VGS = 0V
––– 2270
––– 1395
–––
–––
VDS = 25V
ƒ = 100KHz, See Fig.7
pF
Effective Output Capacitance
(Energy Related)
Coss eff.(ER)
––– 2010
––– 2560
–––
–––
VGS = 0V, VDS = 0V to 60V
VGS = 0V, VDS = 0V to 60V
Coss eff.(TR) Output Capacitance (Time Related)
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Min. Typ.
Max. Units
Conditions
D
MOSFET symbol
showing the
––– –––
355
G
A
integral reverse
p-n junction diode.
ISM
––– ––– 1590
S
VSD
Diode Forward Voltage
––– –––
1.3
V
TJ = 25°C,IS = 100A,VGS = 0V
dv/dt
Peak Diode Recovery dv/dt
–––
–––
–––
8.6
75
80
–––
–––
–––
–––
–––
–––
V/ns TJ = 175°C,IS =100A,VDS = 75V
TJ = 25°C
VDD = 64V
IF = 100A,
trr
Reverse Recovery Time
ns
TJ = 125°C
––– 208
––– 251
TJ = 25°C di/dt = 100A/µs
Qrr
Reverse Recovery Charge
Reverse Recovery Current
nC
A
TJ = 125°C
IRRM
–––
4.8
TJ = 25°C
3
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IRFP7718PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
60µs PULSE WIDTH
4.5V
Tj = 25°C
60µs PULSE WIDTH
4.5V
1
Tj = 25°C
1
0.1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 4. Typical Output Characteristics
Fig 3. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 100A
= 10V
D
V
GS
T = 175°C
J
T = 25°C
J
1
V
= 25V
DS
60µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T , Junction Temperature (°C)
J
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
1000000
100000
10000
1000
14
V
= 0V,
f = 1 MHZ
GS
I = 100A
V
V
V
= 60V
= 38V
15V
D
DS
DS
C
C
C
= C + C , C SHORTED
iss
gs
gd
ds
gd
ds
12
10
8
= C
= C
rss
oss
+ C
DS=
gd
Ciss
6
Coss
Crss
4
2
0
100
0
100 200 300 400 500 600 700
Total Gate Charge (nC)
1
10
100
Q
G
V
, Drain-to-Source Voltage (V)
DS
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
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Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
4
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IRFP7718PbF
1000
100
10
1000
100
10
100µsec
1msec
T = 175°C
J
Limited by Package
10msec
DC
OPERATION IN THIS AREA
T = 25°C
J
LIMITED BY R (on)
DS
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
1.0
0.1
1
10
0.0
0.5
1.0
1.5
2.0
2.5
V
, Drain-toSource Voltage (V)
DS
V
, Source-to-Drain Voltage (V)
SD
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
90
5.0
Id = 2.0mA
4.0
3.0
2.0
1.0
0.0
85
80
75
0
10
20
30
40
50
60
70
80
-60 -40 -20 0 20 40 60 80 100120140160180
V
Drain-to-Source Voltage (V)
T , Temperature ( °C )
J
DS,
Fig 12. Typical Coss Stored Energy
Fig 11. Drain-to–Source Breakdown Voltage
2.2
V
V
V
V
V
= 5.5V
= 6.0V
= 7.0V
= 8.0V
= 10V
GS
GS
GS
GS
GS
2.0
1.8
1.6
1.4
0
50
100
150
200
I , Drain Current (A)
D
Fig 13. Typical On-Resistance vs. Drain Current
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IRFP7718PbF
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
0.02
0.01
0.001
SINGLE PULSE
Notes:
1. Duty Factor D = t1/t2
( THERMAL RESPONSE )
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C. (Single Pulse)
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Avalanche Current vs. Pulse width
1200
1000
800
600
400
200
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
TOP
BOTTOM 1.0% Duty Cycle
= 100A
Single Pulse
I
D
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
I
av = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)· av
t
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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IRFP7718PbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
30
25
20
15
10
5
I
= 60A
= 64V
F
V
R
T = 25°C
J
T = 125°C
J
I
= 250µA
= 1.0mA
= 1.0A
D
I
D
I
D
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
400
600
800
1000
T , Temperature ( °C )
J
di /dt (A/µs)
F
Fig 17. Threshold Voltage vs. Temperature
Fig 18. Typical Recovery Current vs. dif/dt
1000
30
I
= 60A
= 64V
F
I
= 100A
= 64V
F
V
R
V
25
20
15
10
5
R
800
600
400
200
0
T = 25°C
J
T = 25°C
J
T = 125°C
J
T = 125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
F
di /dt (A/µs)
F
Fig 20. Typical Stored Charge vs. dif/dt
Fig 19. Typical Recovery Current vs. dif/dt
1000
I
= 100A
= 64V
F
V
R
800
600
400
200
0
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig 21. Typical Stored Charge vs. dif/dt
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February 19, 2015
IRFP7718PbF
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V
(BR)DSS
t
p
15V
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
I
0.01
t
p
AS
Fig 23a. Unclamped Inductive Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 25b. Gate Charge Waveform
Fig 25a. Gate Charge Test Circuit
8
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IRFP7718PbF
TO-247AC Package Outline (Dimensions are shown in millimeters (inches))
TO-247AC Part Marking Information
Notes: This part marking information applies to devices produced after 02/26/2001
EXAMPLE: THIS IS AN IRFPE30
WITH ASSEMBLY
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE 5657
IRFPE30
135H
57
ASSEMBLED ON WW 35, 2001
IN THE ASSEMBLY LINE "H"
56
DATE CODE
YEAR 1 = 2001
WEEK 35
ASSEMBLY
LOT CODE
Note: "P" in assembly line position
indicates "Lead-Free"
LINE H
TO-247AC package is not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
9
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IRFP7718PbF
Qualification Information†
Qualification Level
Industrial
(per JEDEC JESD47F) ††
TO-247AC
N/A
Yes
Moisture Sensitivity Level
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/
†† Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comments
Updated EAS (L =1mH) = 2004mJ on page 2
Updated note 9 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 63A, VGS =10V” on page 2
02/19/2015
IR WORLD HEADQUARTERS: 101N Sepulveda Blvd, El Segundo, California 90245, USA
To contact Internaꢀonal Recꢀfier, please visit hꢁp://www.irf.com/whoto‐call/
10 www.irf.com © 2015 International Rectifier
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February 19, 2015
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