IRFPS30N60K [INFINEON]
SMPS MOSFET; 开关电源MOSFET
| 型号： | IRFPS30N60K |
| 厂家： | 
Infineon |
| 描述： | SMPS MOSFET |
| 文件： | 总8页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD- 94417A
IRFPS30N60K
SMPS MOSFET
HEXFET® Power MOSFET
Applications
VDSS
600V
RDS(on) typ.
ID
30A
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
160mΩ
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
Super-247™
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
30
19
120
A
PD @TC = 25°C
Power Dissipation
450
W
W/°C
V
Linear Derating Factor
3.6
VGS
dv/dt
TJ
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
13
V/ns
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case )
300
°C
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
Typ.
Max.
520
30
Units
mJ
–––
–––
–––
IAR
Avalanche Current
A
EAR
Repetitive Avalanche Energy
45
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Typ.
–––
Max.
0.28
–––
40
Units
RθJC
RθCS
RθJA
0.24
–––
°C/W
Junction-to-Ambient
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1
8/26/04
IRFPS30N60K
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
600 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.66 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– 160 190
3.0 ––– 5.0
mΩ VGS = 10V, ID = 18A
V
VDS = VGS, ID = 250µA
VDS = 600V, VGS = 0V
VDS = 480V, VGS = 0V, TJ = 125°C
VGS = 30V
––– ––– 50
––– ––– 250
––– ––– 100
––– ––– -100
µA
IDSS
IGSS
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 18A
ID = 30A
gfs
16 ––– –––
S
Qg
––– ––– 220
––– ––– 64
––– ––– 110
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 480V
VGS = 10V
VDD = 300V
–––
29 –––
––– 120 –––
ID = 30A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
56 –––
50 –––
RG = 3.9 Ω
VGS = 10V
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 5870 –––
––– 530 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
VDS = 25V
–––
54 –––
pF
ƒ = 1.0MHz
––– 6920 –––
––– 140 –––
––– 270 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 480V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 480V ꢀ
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
30
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 120
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Reverse RecoveryCurrent
Forward Turn-On Time
––– ––– 1.5
––– 640 960
V
TJ = 25°C, IS = 30A, VGS = 0V
ns
TJ = 25°C, IF = 30A
Qrr
IRRM
ton
––– 11
16
µC di/dt = 100A/µs
––– 31 –––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Repetitive rating; pulse width limited by
max. junction temperature.
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Starting TJ = 25°C, L = 1.1mH, RG = 25Ω,
IAS = 30A
Rθ is measured at TJ approximately 90°C
ISD ≤ 30A, di/dt ≤ 630A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C
,
2
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IRFPS30N60K
100
10
1
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
BOTTOM 5.0V
5.0V
1
5.0V
0.1
0.01
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100.0
3.0
30A
=
I
D
T
= 150°C
J
2.5
2.0
1.5
1.0
0.5
0.0
10.0
1.0
T
J
= 25°C
V
= 50V
DS
20µs PULSE WIDTH
V
= 10V
0.1
GS
5.0
6.0
7.0
8.0
9.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
°
T , Junction Temperature
( C)
V
, Gate-to-Source Voltage (V)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRFPS30N60K
1000000
20
16
12
8
V
= 0V,
f = 1 MHZ
GS
C
= C
+
C
,
C
ds
I
= 30A
iss
SHORTED
gs
gd
V
= 480V
D
DS
VDS= 300V
VDS= 120V
100000
10000
1000
100
C
= C
gd
rss
C
= C + C
oss
ds gd
Ciss
Coss
Crss
4
0
10
0
40
80
120
160
200
240
1
10
100
1000
Q
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100.0
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
10.0
1.0
T
= 150°C
J
100µsec
1msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
T
= 25°C
J
V
= 0V
GS
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1
10
100
1000
10000
V
, Source-toDrain Voltage (V)
V
, Drain-toSource Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFPS30N60K
RD
30
24
18
12
6
VDS
VGS
D.U.T.
RG
+VDD
-
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25
50
T
75
100
125
150
°
( C)
, Case Temperature
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
P
DM
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.01
t
1
t
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS30N60K
1000
800
600
400
200
0
15V
I
D
TOP
13A
19A
30A
BOTTOM
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
25
50
75
100
125
150
p
°
( C)
Starting T , Junction Temperature
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
Q
G
50KΩ
.2µF
12V
.3µF
Q
Q
GD
GS
+
V
DS
D.U.T.
-
V
V
GS
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRFPS30N60K
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFPS30N60K
Super-247™ (TO-274AA) Package Outline
0.13 [.005]
0.25 [.010]
B A
5.50 [.216]
4.50 [.178]
16.10 [.632]
15.10 [.595]
13.90 [.547]
13.30 [.524]
A
2.15 [.084]
1.45 [.058]
3.00 [.118]
2.00 [.079]
2X R
1.30 [.051]
0.70 [.028]
16.10 [.633]
15.50 [.611]
4
4
20.80 [.818]
19.80 [.780]
C
1
2
3
B
Ø 1.60 [.063]
MAX.
E
E
14.80 [.582]
13.80 [.544]
4.25 [.167]
3.85 [.152]
1.30 [.051]
1.10 [.044]
3X
1.60 [.062]
1.45 [.058]
3X
2.35 [.092]
1.65 [.065]
5.45 [.215]
2X
L E AD AS S IGNME NT S
SECTION E-E
0.25 [.010]
B
A
IGBT
MOS F ET
NOT E S:
1. DIMENS IONING AND TOLERANCING PER AS ME Y14.5M-1994.
2. DIMENSIONS ARE SHOWN IN MILLIMET E RS [INCHES ]
3. CONT ROLLING DIMENS ION: MILLIMET ER
1 - GATE
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
2 - COL L E CT OR
3 - EMITTER
4 - COL L E CT OR
4. OUTLINE CONFORMS TO JEDEC OUTLINE TO-274AA
Super-247™ (TO-274AA)Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH
ASSEMBLY LOT CODE A8B9
PART NUMBER
INTERNATIONAL RECTIFIER
IRFPS37N50A
LOGO
A8B9
0020
DATE CODE
(YYWW)
ASSEMBLY LOT CODE
YY = YEAR
WW = WEEK
TOP
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.8/04
8
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