IRFPS35N50LPBF [INFINEON]
SMPS MOSFET; 开关电源MOSFET
| 型号： | IRFPS35N50LPBF |
| 厂家： | 
Infineon |
| 描述： | SMPS MOSFET |
| 文件： | 总8页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-95140
IRFPS35N50LPbF
SMPS MOSFET
HEXFET® Power MOSFET
Applications
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
• Motor Control applications
• Lead-Free
Trr typ.
VDSS RDS(on) typ.
0.125
ID
500V
Ω
170ns 34A
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise immunity.
Super-247™
Absolute Maximum Ratings
Parameter
Max.
34
Units
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
22
IDM
140
450
Pulsed Drain Current
PD @TC = 25°C
Power Dissipation
W
Linear Derating Factor
Gate-to-Source Voltage
3.6
±30
W/°C
V
VGS
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
15
V/ns
-55 to + 150
TSTG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case )
1.1(10)
N•m (lbf•in)
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max. Units
––– ––– 34
Conditions
MOSFET symbol
I
S
(Body Diode)
A
showing the
I
Pulsed Source Current
––– ––– 140
integral reverse
SM
(Body Diode)
p-n junction diode.
V
t
T = 25°C, I = 34A, V = 0V
Diode Forward Voltage
Reverse Recovery Time
––– ––– 1.5
––– 170 250
––– 220 330
V
SD
J
S
GS
T = 25°C, I = 34A
ns
rr
J
F
TJ = 125°C, di/dt = 100A/µs
Q
T = 25°C, I = 34A, V = 0V
Reverse Recovery Charge
––– 670 1010 nC
––– 1500 2200
rr
J
S
GS
TJ = 125°C, di/dt = 100A/µs
IRRM
T = 25°C
J
Reverse Recovery Current
Forward Turn-On Time
––– 8.5 –––
A
t
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
09/14/04
IRFPS35N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
500
–––
–––
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
0.12
–––
V/°C Reference to 25°C, ID = 1mA
––– 0.125 0.145
V
V
V
GS = 10V, ID = 20A
DS = VGS, ID = 250µA
DS = 500V, VGS = 0V
Ω
V
VGS(th)
3.0
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
1.1
5.0
50
IDSS
Drain-to-Source Leakage Current
µA
2.0
mA VDS = 400V, VGS = 0V, TJ = 125°C
nA VGS = 30V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
100
-100
–––
VGS = -30V
RG
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 20A
D = 34A
DS = 400V
18
–––
–––
–––
–––
24
–––
230
65
S
–––
–––
–––
–––
–––
–––
–––
I
Qgs
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC
V
Qgd
110
–––
–––
–––
–––
VGS = 10V, See Fig. 7 & 15
VDD = 250V
td(on)
tr
100
42
ns
I
D = 34A
G = 1.2Ω
GS = 10V, See Fig. 10a & 10b
VGS = 0V
VDS = 25V
td(off)
Turn-Off Delay Time
Fall Time
R
tf
42
V
Ciss
Input Capacitance
––– 5580 –––
Coss
Output Capacitance
–––
–––
590
58
–––
–––
Crss
Reverse Transfer Capacitance
Output Capacitance
pF ƒ = 1.0MHz, See Fig. 5
Coss
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
––– 7290 –––
Coss
Output Capacitance
–––
–––
–––
160
320
220
–––
–––
–––
Coss eff.
Coss eff. (ER)
Effective Output Capacitance
Effective Output Capacitance
VGS = 0V,VDS = 0V to 400V
(Energy Related)
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
560
34
Units
mJ
A
Symbol
EAS
Avalanche Current
IAR
Repetitive Avalanche Energy
EAR
45
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.28
–––
40
Units
Junction-to-Case
Rθ
Rθ
Rθ
JC
CS
JA
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.24
–––
°C/W
Notes:
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting TJ = 25°C, L = 0.97mH, RG =25Ω,
IAS = 34A (See Figure 13)
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% VDSS
.
ISD ≤ 34A, di/dt ≤ 765A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C.
,
Rθ is measured at TJ approximately 90°C
2
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IRFPS35N50LPbF
1000
100
10
1000
100
10
VGS
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
15V
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
1
0.1
4.5V
1
4.5V
0.01
0.001
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
T = 150 C
J
°
0.1
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
34A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
100
10
°
T = 150 C
J
1
°
T = 25 C
J
0.1
0.01
V
= 50V
DS
20µs PULSE WIDTH
V
=10V
GS
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
4.0
5.0
6.0
7.0
8.0 9.0
10.0
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRFPS35N50LPbF
30
25
20
15
10
5
100000
V
= 0V,
f = 1 MHZ
GS
C
= C + C
,
C
ds
SHORTED
iss
gs
gd
C
= C
rss
gd
C
= C + C
oss
ds
gd
10000
1000
100
Ciss
Coss
Crss
10
0
1
10
100
1000
0
100
V
200
300
400
500
600
V
, Drain-to-Source Voltage (V)
DS
Drain-to-Source Voltage (V)
DS,
Fig 6. Typ. Output Capacitance
Fig 5. Typical Capacitance Vs.
Stored Energy vs. VDS
Drain-to-Source Voltage
20
16
12
8
1000
100
10
I
D
= 34A
V
V
V
= 400V
= 250V
= 100V
DS
DS
DS
°
T = 150 C
J
°
T = 25 C
J
1
4
FOR TEST CIRCUIT
SEE FIGURE 13
V
= 0 V
GS
1.4
0.1
0.2
0
0.4
0.6
0.8
1.0
1.2
1.6
0
40
80
120
160 200
240
V
,Source-to-Drain Voltage (V)
SD
Q , Total Gate Charge (nC)
G
Fig 8. Typical Source-Drain Diode
Fig 7. Typical Gate Charge Vs.
ForwardVoltage
Gate-to-SourceVoltage
4
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IRFPS35N50LPbF
RD
35
30
25
20
15
10
5
VDS
VGS
D.U.T.
RG
+VDD
-
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
°
T , Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
P
2
DM
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.001
t
1
t
2
Notes:
1. Duty factor D =
t / t
1
2. Peak T =P
x Z
+ T
thJC C
J
DM
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS35N50LPbF
1200
1000
800
600
400
200
0
1000
I
D
OPERATION IN THIS AREA LIMITED
TOP
15A
22A
BY R
DS(on)
BOTTOM 34A
100
10us
100us
10
1ms
°
T = 25 C
C
J
°
T = 150 C
10ms
1000
Single Pulse
1
1
10
100
10000
25
50
75
100
125
150
V
, Drain-to-Source Voltage (V)
DS
°
Starting T , Junction Temperature ( C)
J
Fig 12. Maximum Safe Operating Area
Fig 13. Maximum Avalanche Energy
Vs. DrainCurrent
15V
V
(BR)DSS
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01Ω
t
p
I
AS
Fig 14a. Unclamped Inductive Test Circuit
Fig 14b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
Q
G
50KΩ
.2µF
12V
VGS
.3µF
Q
Q
GD
GS
+
V
DS
D.U.T.
-
V
V
GS
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 15b. Basic Gate Charge Waveform
Fig 15a. Gate Charge Test Circuit
6
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IRFPS35N50LPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFPS35N50LPbF
Case Outline and Dimensions — Super-247
Super-247 (TO-274AA) Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH
ASSEMBLY LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
PART NUMBER
INTERNATIONAL RECTIFIER
LOGO
IRFPS37N50A
719C
17
89
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
ASSEMBLY LOT CODE
Note: "P" in assembly line position
indicates "Lead-Free"
TOP
Super TO-247™ package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/04
8
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