IRFPS37N50A [INFINEON]
Power MOSFET(Vdss=500V, Rds(on)max=0.13ohm, Id=36A); 功率MOSFET （ VDSS = 500V ， RDS（ON）最大值= 0.13ohm ，ID = 36A ）
| 型号： | IRFPS37N50A |
| 厂家： | 
Infineon |
| 描述： | Power MOSFET(Vdss=500V, Rds(on)max=0.13ohm, Id=36A) |
| 文件： | 总8页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD- 91822C
SMPS MOSFET
IRFPS37N50A
HEXFET® Power MOSFET
Applications
VDSS
500V
RDS(on) max
ID
36A
l Switch Mode Power Supply (SMPS)
l Uninterruptable Power Supply
l High Speed Power Switching
0.13Ω
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN
1001)
SUPER-247
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
36
23
A
144
PD @TC = 25°C
Power Dissipation
446
W
W/°C
V
Linear Derating Factor
3.6
VGS
dv/dt
TJ
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
3.5
V/ns
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Typical SMPS Topologies
l Full Bridge Converters
l Power Factor Correction Boost
Notes through ꢀ are on page 8
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1
12/14/99
IRFPS37N50A
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
RDS(on)
VGS(th)
Drain-to-Source Breakdown Voltage
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
500 ––– –––
––– ––– 0.13
V
Ω
V
VGS = 10V, ID = 22A
VDS = VGS, ID = 250µA
VDS = 500V, VGS = 0V
VDS = 400V, VGS = 0V, TJ = 150°C
VGS = 30V
2.0
––– 4.0
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
IGSS
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
20 ––– –––
Conditions
VDS = 50V, ID = 22A
ID = 36A
gfs
S
Qg
––– ––– 180
––– ––– 46
––– ––– 71
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 400V
VGS = 10V, See Fig. 6 and 13
–––
–––
–––
–––
23 –––
98 –––
52 –––
80 –––
VDD = 250V
ID = 36A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 2.15Ω
RD = 7.0Ω,See Fig. 10
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 5579 –––
––– 810 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
VDS = 25V
–––
36 –––
pF
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 400V ꢀ
––– 7905 –––
––– 221 –––
––– 400 –––
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
1260
36
Units
mJ
EAS
IAR
Avalanche Current
A
EAR
Repetitive Avalanche Energy
44
mJ
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
0.28
–––
40
Units
RθJC
RθCS
RθJA
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.24
–––
°C/W
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
36
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
––– ––– 144
S
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.5
––– 570 860
V
TJ = 25°C, IS = 36A, VGS = 0V
ns
TJ = 25°C, IF = 36A
Qrr
ton
––– 8.6
13
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFPS37N50A
100
10
1
1000
100
10
VGS
15V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
1
20µs PULSE WIDTH
T = 150 C
20µs PULSE WIDTH
°
°
J
T = 25 C
J
0.1
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
36A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
100
10
1
°
T = 150 C
J
°
T = 25 C
J
V
= 50V
DS
20µs PULSE WIDTH
V
= 10V
GS
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
4.0
5.0
6.0
7.0 8.0
9.0
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRFPS37N50A
20
16
12
8
100000
V
C
C
C
= 0V,
f = 1MHz
I
D
= 36A
G S
is s
= C
= C
= C
+ C
+ C
,
C
SHORTED
gs
gd
ds
gd
ds
V
V
V
= 400V
= 250V
= 100V
DS
DS
DS
rss
oss
gd
C
10000
1000
100
iss
C
C
oss
rss
4
FOR TEST CIRCUIT
SEE FIGURE 13
10
A
0
1
10
100
1000
0
40
80
120
160
200
Q
, Total Gate Charge (nC)
V
, D rain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10us
°
T = 150 C
J
100us
°
T = 25 C
J
1ms
1
10ms
°
T = 25 C
C
°
T = 150 C
Single Pulse
J
V
= 0 V
GS
1.2
0.1
0.2
1
0.4
V
0.6
0.8
1.0
1.4
10
100
1000
10000
,Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFPS37N50A
RD
40
30
20
10
0
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
T
75
100
125
150
°
, Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.01
0.10
0.05
P
DM
0.02
0.01
t
1
SINGLE PULSE
(THERMAL RESPONSE)
t
2
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T = P
x Z
+ T
C
J
DM
thJC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS37N50A
3000
2500
2000
1500
1000
500
1 5V
I
D
TOP
16A
23A
36A
BOTTOM
DRIVER
L
V
G
DS
D.U.T
R
+
V
D D
-
I
A
AS
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
0
25
50
75
100
125
150
°
Starting T , Junction Temperature ( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
5 8 0
Q
Q
GD
GS
V
G
5 6 0
5 4 0
5 2 0
5 0 0
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
A
0
1 0
2 0
3 0
4 0
V
GS
I
, Av alanche Current (A)
av
3mA
I
I
D
G
Current Sampling Resistors
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Fig 13b. Gate Charge Test Circuit
6
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IRFPS37N50A
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-channel HEXFET® Power MOSFETs
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7
IRFPS37N50A
Case Outline and Dimensions — Super-247
Dimensions are shown in millimeters
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 )
ꢀCoss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25°C, L = 1.94mH
RG = 25Ω, IAS = 36A. (See Figure 12)
as Coss while VDS is rising from 0 to 80% VDSS
ISD ≤ 36A, di/dt ≤ 145A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C
,
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
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Data and specifications subject to change without notice. 12/99
8
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