IRFR4615TRLPBF [INFINEON]

High Efficiency Synchronous Rectification in SMPS; 高效率同步整流开关电源


型号：	IRFR4615TRLPBF
厂家：	Infineon
描述：	High Efficiency Synchronous Rectification in SMPS 高效率同步整流开关电源晶体开关晶体管功率场效应晶体管脉冲
文件：	总11页 (文件大小：304K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFR4615PbF

IRFU4615PbF

HEXFET^®Power MOSFET

150V

V_DSS

Applications

l High Efficiency Synchronous Rectification in SMPS

l Uninterruptible Power Supply

l High Speed Power Switching

R_DS(on)typ.

max.

34m

42m

33A

l Hard Switched and High Frequency Circuits

I_D

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

DPak

IRFR4615PbF

IPAK

IRFU4615PbF

SOA

l Enhanced body diode dV/dt and dI/dt Capability

l Lead-Free

Gate

Drain

Source

Standard Pack

Form

Tube/Bulk

Tape and Reel Left

Orderable Part Number

Base Part Number

Package Type

Quantity

3000

IRFR4615PbF

IRFR4615TRLPbF

IRFR4615PbF

IRFR4615TRLPbF

D-PAK

I-PAK

IRFU4615PbF

Tube/Bulk

IRFU4615PbF

Absolute Maximum Ratings

Symbol

I_D@ T_C= 25°C

Parameter

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

Max.

Units

I_D@ T_C= 100°C

I_DM

140

144

0.96

± 20

P_D@T_C= 25°C

Maximum Power Dissipation

Linear Derating Factor

W/°C

V_GS

Gate-to-Source Voltage

Peak Diode Recovery

dv/dt

T_J

V/ns

-55 to + 175

Operating Junction and

T_STG

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

°C

300

Avalanche Characteristics

Single Pulse Avalanche Energy

E_{AS (Thermally limited)}

109

Avalanche Current

I_AR

See Fig. 14, 15, 22a, 22b,

Repetitive Avalanche Energy

E_AR

Thermal Resistance

Symbol

Parameter

Typ.

–––

Max.

1.045

Units

R_θJC

Junction-to-Case

R_θJA

°C/W

Junction-to-Ambient (PCB Mount)

Junction-to-Ambient

110

Notes through are on page 11

May 16, 2013

IRFR/U4615PbF

Static @ T_J= 25°C (unless otherwise specified)

Symbol

V_(BR)DSS

Parameter

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

Gate Threshold Voltage

Min. Typ. Max. Units

150 ––– –––

––– 0.19 ––– V/°C Reference to 25°C, I_D= 5mA

Conditions

V_GS= 0V, I_D= 250μA

/ T

_(BR)DSSΔ

R_DS(on)

V_GS(th)

I_DSS

–––

3.0

5.0

V_GS= 10V, I_D= 21A

–––

V_DS= V_GS, I_D= 100μA

Drain-to-Source Leakage Current

––– –––

V_DS= 150V, V_GS= 0V

μA

––– ––– 250

––– ––– 100

––– ––– -100

V_DS= 150V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Internal Gate Resistance

_GS= 20V

V_GS= -20V

R_G(int)

–––

2.7

–––

Dynamic @ T_J= 25°C (unless otherwise specified)

Symbol

gfs

Parameter

Forward Transconductance

Min. Typ. Max. Units

Conditions

V_DS= 50V, I_D= 21A

––– –––

Q_g

Total Gate Charge

–––

I_D= 21A

Q_gs

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Total Gate Charge Sync. (Q_g- Q_gd)

Turn-On Delay Time

Rise Time

8.6

9.0

–––

V_DS= 75V

Q_gd

V_GS= 10V

Q_sync

I_D= 21A, V_DS=0V, V_GS= 10V

V_DD= 98V

t_d(on)

t_r

I_D= 21A

t_d(off)

Turn-Off Delay Time

Fall Time

R = 7.3

V_GS= 10V

t_f

C_iss

Input Capacitance

––– 1750 –––

––– 155 –––

V_GS= 0V

C_oss

Output Capacitance

Reverse Transfer Capacitance

V_DS= 50V

ƒ = 1.0MHz

C_rss

–––

(See Fig.5)

C_osseff. (ER)

C_osseff. (TR)

––– 179 –––

––– 382 –––

V_GS= 0V, V_DS= 0V to 120V (See Fig.11)

V_GS= 0V, V_DS= 0V to 120V

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)

Diode Characteristics

Symbol

Parameter

Continuous Source Current

Min. Typ. Max. Units

Conditions

MOSFET symbol

I_S

––– –––

(Body Diode)

showing the

I_SM

Pulsed Source Current

(Body Diode)

integral reverse

––– ––– 140

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

Reverse Recovery Time

––– –––

1.3

–––

T_J= 25°C, I_S= 21A, V_GS= 0V

T_J= 25°C

T_J= 125°C

T_J= 25°C

T_J= 125°C

T_J= 25°C

V_R= 100V,

I_F= 21A

di/dt = 100A/μs

–––

Q_rr

Reverse Recovery Charge

––– 177 –––

––– 247 –––

I_RRM

t_on

Reverse Recovery Current

Forward Turn-On Time

–––

4.9

–––

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

May 16, 2013

IRFR/U4615PbF

1000

100

1000

100

VGS

15V

12V

VGS

15V

12V

TOP

10V

8.0V

7.0V

6.0V

5.5V

5.0V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM

5.0V

0.1

0.01

60μs PULSE WIDTH

Tj = 175°C

≤

60μs PULSE WIDTH

Tj = 25°C

≤

0.1

100

0.1

100

, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

100

3.0

2.5

2.0

1.5

1.0

0.5

= 21A

= 10V

T = 175°C

T = 25°C

= 50V

≤

60μs PULSE WIDTH

0.1

10 12 14

-60 -40 -20 0 20 40 60 80 100120140160180

, Junction Temperature (°C)

, Gate-to-Source Voltage (V)

Fig 4. Normalized On-Resistance vs. Temperature

Fig 3. Typical Transfer Characteristics

100000

10000

1000

100

14.0

= 0V,

= C

f = 1 MHZ

I = 21A

+ C , C

SHORTED

iss

12.0

= C

rss

oss

= C + C

= 120V

= 75V

10.0

8.0

6.0

4.0

2.0

0.0

VDS= 30V

iss

oss

rss

100

1000

, Drain-to-Source Voltage (V)

Q , Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage

Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

May 16, 2013

IRFR/U4615PbF

1000

100

1000

100

OPERATION IN THIS AREA

LIMITED BY R (on)

100μsec

1msec

= 175°C

10msec

= 25°C

Tc = 25°C

Tj = 175°C

Single Pulse

= 0V

1.4

0.1

1.0

100

1000

0.2

0.4

0.6

0.8

1.0

1.2

1.6

, Drain-to-Source Voltage (V)

, Source-to-Drain Voltage (V)

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

190

185

180

175

170

165

160

155

150

145

140

Id = 5mA

100

125

150

175

-60 -40 -20 0 20 40 60 80 100120140160180

, Case Temperature (°C)

T , Temperature ( °C )

Fig 10. Drain-to-Source Breakdown Voltage

Fig 9. Maxi^Cmum Drain Current vs.

Case Temperature

3.0

500

450

400

350

300

250

200

150

100

TOP

2.8A

5.3A

BOTTOM 21A

2.5

2.0

1.5

1.0

0.5

0.0

-20

20 40 60 80 100 120 140 160

Drain-to-Source Voltage (V)

100

125

150

175

Starting T , Junction Temperature (°C)

DS,

Fig 11. Typical C_OSSStored Energy

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

May 16, 2013

IRFR/U4615PbF

D = 0.50

0.20

0.10

R₁

R₂

R₃

R₄

Ri (°C/W) τi (sec)

0.1

0.02324 0.000008

^Jτ_J

0.05

0.02

0.01

^Cτ

0.26212 0.000106

0.50102 0.001115

0.25880 0.005407

¹τ₁

Ci= τi/Ri

²τ₂

³τ₃

⁴τ₄

0.01

0.001

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

0.01

0.05

0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔΤ j = 25°C and

Tstart = 150°C.

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

120

100

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of T_jmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

6. I_av= Allowable avalanche current.

7. ΔT = Allowable rise in junction temperature, not to exceed T_jmax(assumed as

25°C in Figure 14, 15).

t_{av =}Average time in avalanche.

D = Duty cycle in avalanche = t_av·f

TOP

BOTTOM 1.0% Duty Cycle

= 21A

Single Pulse

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 13)

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

100

125

150

175

I_av= 2DT/ [1.3·BV·Z_th]

E_{AS (AR)}= P_{D (ave)}·t_av

Starting T , Junction Temperature (°C)

Fig 15. Maximum Avalanche Energy vs. Temperature

May 16, 2013

IRFR/U4615PbF

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

I = 14A

= 100V

T = 25°C

T = 125°C

= 100μA

= 250uA

ID = 1.0mA

ID = 1.0A

-75 -50 -25

25 50 75 100 125 150 175

200

400

600

800

1000

T , Temperature ( °C )

di /dt (A/μs)

Fig. 17 - Typical Recovery Current vs. di_f/dt

Fig 16. Threshold Voltage vs. Temperature

800

I = 21A

I = 14A

700

600

500

400

300

200

100

= 100V

T = 25°C

T = 125°C

200

400

600

800

1000

200

400

600

800

1000

di /dt (A/μs)

Fig. 18 - Typical Recovery Current vs. di_f/dt

Fig. 19 - Typical Stored Charge vs. di_f/dt

1000

I = 21A

900

800

700

600

500

400

300

200

100

= 100V

T = 25°C

T = 125°C

200

400

600

800

1000

di /dt (A/μs)

Fig. 20 - Typical Stored Charge vs. di_f/dt

May 16, 2013

IRFR/U4615PbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

=10V

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Current

Inductor Curent

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

(BR)DSS

15V

DRIVER

D.U.T

20V

0.01

Fig 22b. Unclamped Inductive Waveforms

Fig 22a. Unclamped Inductive Test Circuit

R_D

V_DS

90%

V_GS

D.U.T.

R_G

V_DD

10V

V_GS

10%

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

d(on)

d(off)

Fig 23a. Switching Time Test Circuit

Fig 23b. Switching Time Waveforms

Current Regulator

Same Type as D.U.T.

Vds

Vgs

50KΩ

.2μF

12V

.3μF

D.U.T.

Vgs(th)

3mA

Qgs1

Qgs2

Qgd

Qgodr

Current Sampling Resistors

Fig 24a. Gate Charge Test Circuit

Fig 24b. Gate Charge Waveform

May 16, 2013

IRFR/U4615PbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER

WIT H AS S E MBL Y

LOT CODE 1234

RECTIFIER

ASSEMBLED ON WW 16, 2001

INTERNATIONAL

DAT E CODE

YEAR 1 = 2001

WEE K 16

IRFR120

116A

LOGO

IN THE ASSEMBLY LINE "A"

LINE A

Note: "P" in assembly lineposition

indicates "Lead-F ree"

AS S E MB L Y

LOT CODE

"P" in assembly lineposition indicates

"L ead-F ree" qualification to the cons umer-level

PART NUMBER

DATE CODE

INTERNATIONAL

RECTIFIER

IRFR120

P = DE S IGNAT E S L E AD-F RE E

PRODUCT (OPTIONAL)

LOGO

P = DE S IGNAT E S L E AD-F RE E

PRODUCT QUALIFIED TOTHE

CONSUMER LEVEL (OPTIONAL)

ASSEMBLY

LOT CODE

YEAR 1 = 2001

WE EK 16

A = AS S E MBL Y S IT E CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

May 16, 2013

IRFR/U4615PbF

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

PART NUMBER

EXAMPLE: THIS IS AN IRFU120

INTERNATIONAL

RECTIFIER

LOGO

WIT H AS S E MBLY

LOT CODE 5678

DAT E CODE

YEAR 1 = 2001

WE EK 19

IRFU120

119A

ASSEMBLED ON WW19, 2001

IN THE ASSEMBLY LINE "A"

LINE A

AS S E MB L Y

LOT CODE

Note: "P" in assembly lineposition

indicates Lead-Free"

PART NUMBER

DATE CODE

P = DE S IGNAT E S L E AD-F R E E

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

LOGO

IRFU120

56 78

YEAR 1 = 2001

AS S E MBL Y

LOT CODE

WE EK 19

A = AS S E MB L Y S IT E CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

May 16, 2013

IRFR/U4615PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

May 16, 2013

IRFR/U4615PbF

Qualification Information^†

Industrial

Qualification level

(per JEDEC JESD47F^††guidelines)

MSL1

D-PAK

I-PAK

(per JEDEC J-STD-020D^††)

Moisture Sensitivity Level

RoHS Compliant

Not applicable

Yes

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/product-info/reliability

†† Applicable version of JEDEC standard at the time of product release.

Notes:

ꢀ C_osseff. (TR) is a fixed capacitance that gives the same charging time

as C_osswhile V_DSis rising from 0 to 80% V_DSS

C_osseff. (ER) is a fixed capacitance that gives the same energy as

_osswhile V_DSis rising from 0 to 80% V_DSS

When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application

note #AN-994

Repetitive rating; pulse width limited by max. junction

temperature.

Limited by T_Jmax, starting T_J= 25°C, L = 0.51mH

R_G= 25Ω, I_AS= 21A, V_GS=10V. Part not recommended for use

above this value .

I_SD≤ 21A, di/dt ≤ 549A/μs, V_DD≤ V_(BR)DSS, T_J≤ 175°C.

Pulse width ≤ 400μs; duty cycle ≤ 2%.

R_θis measured at T_Japproximately 90°C

Revision History

Date

Comments

•

Updated datasheet to new IR corporate formatting template

Updated Orderable part number from "IRFR4615TRPbF" to "IRFR4615TRLPbF", on page 1

5/16/2013

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

May 16, 2013

IRFR4615TRLPBF [INFINEON]

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