IRFR7440TRPBF_技术文档

IRFR7440PbF

IRFU7440PbF

HEXFET^®Power MOSFET

Applications

D

S

V_DSS

R_DS(on)typ.

max.

40V

1.9mΩ

2.4mΩ

l Brushed Motor drive applications

l BLDC Motor drive applications

l PWM Inverterized topologies

l Battery powered circuits

l Half-bridge and full-bridge topologies

l Electronic ballast applications

l Synchronous rectifier applications

l Resonant mode power supplies

l OR-ing and redundant power switches

l DC/DC and AC/DC converters

G

I_D

180A

(Silicon Limited)

I_D

90A

(Package Limited)

D

S

D

G

Benefits

I-Pak

IRFU7440TRPbF

D-Pak

l Improved Gate, Avalanche and Dynamic dV/dt

IRFR7440TRPbF

Ruggedness

l Fully Characterized Capacitance and Avalanche

SOA

l Enhanced body diode dv/dt and dI/dt Capability

l Lead-Free

G

Gate

D

Drain

S

Source

l RoHS Compliant containing no Lead, no Bromide,

and no Halogen

Ordering Information

Orderable part number

Package Type

Standard Pack

Form

Tube/Bulk

Tape and Reel

Tube/Bulk

Complete Part Number

Quantity

75

2000

75

IRFR7440PbF

IRFR7440TRPbF

IRFU7440PbF

D-PAK

I-PAK

IRFR7440PbF

IRFR7440TRPbF

IRFU7440PbF

180

8

6

4

2

LIMITED BY PACKAGE

I

= 90A

D

160

140

120

100

80

T

= 125°C

J

60

40

= 25°C

16

20

J

0

4

25

50

75

100

125

150

175

8

12

20

T , Case Temperature (°C)

V

, Gate-to-Source Voltage (V)

C

GS

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

1

October 17, 2012

IRFR/U7440PbF

Absolute Maximum Ratings

Symbol

Parameter

Max.

180

Units

I_D@ T_C= 25°C

I_D@ T_C= 100°C

I_D@ T_C= 25°C

I_DM

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

Continuous Drain Current, V_GS@ 10V (Wire Bond Limited)

Pulsed Drain Current

125

A

90

760

140

P_D@T_C= 25°C

Maximum Power Dissipation

W

0.95

Linear Derating Factor

W/°C

V

± 20

V_GS

dv/dt

T_J

Gate-to-Source Voltage

4.4

Peak Diode Recovery

V/ns

-55 to + 175

Operating Junction and

°C

T_STG

Storage Temperature Range

300

Soldering Temperature, for 10 seconds (1.6mm from case)

Avalanche Characteristics

Single Pulse Avalanche Energy

E_{AS (Thermally limited)}

160

220

mJ

E

_AS(tested)

Single Pulse Avalanche Energy Tested Value

Avalanche Current

I_AR

A

See Fig 15,16, 23a, 23b

Repetitive Avalanche Energy

E_AR

mJ

Thermal Resistance

Symbol

Parameter

Typ.

–––

Max.

1.05

50

Units

R₈

JC

Junction-to-Case

Junction-to-Ambient (PCB Mount)

°C/W

R₈_JA

R₈

Junction-to-Ambient

110

JA

Static @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

Conditions

V_(BR)DSS

Drain-to-Source Breakdown Voltage

40

––– –––

V

V_GS= 0V, I_D= 250μA

Δ

V_(BR)DSS/ T_JBreakdown Voltage Temp. Coefficient

–––

28

1.9

2.8

3.0

––– mV/°C Reference to 25°C, I_D= 1mA

Ω

V

R_DS(on)

Static Drain-to-Source On-Resistance

2.4

–––

3.9

1

m

V_GS= 10V, I_D= 90A

V_GS= 6.0V, I_D= 50A

V_DS= V_GS, I_D= 100μA

V_GS(th)

I_DSS

Gate Threshold Voltage

2.2

Drain-to-Source Leakage Current

––– –––

μA V_DS= 40V, V_GS= 0V

V_DS= 40V, V_GS= 0V, T_J= 125°C

nA V_GS= 20V

V_GS= -20V

––– ––– 150

––– ––– 100

––– ––– -100

I_GSS

R_G

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Internal Gate Resistance

Ω

–––

2.6

–––

Notes:

Calculated continuous current based on maximum allowable junction

ꢀ Pulse width ≤ 400μs; duty cycle ≤ 2%.

temperature. Bond wire current limit is 90A. Note that current

C_osseff. (TR) is a fixed capacitance that gives the same charging time

limitations arising from heating of the device leads may occur with

some lead mounting arrangements. (Refer to AN-1140)

Repetitive rating; pulse width limited by max. junction

temperature.

Limited by T_Jmax, starting T_J= 25°C, L = 0.04mH

R_G= 50Ω, I_AS= 90A, V_GS=10V.

as C_osswhile V_DSis rising from 0 to 80% V_DSS

C_osseff. (ER) is a fixed capacitance that gives the same energy as

C_osswhile V_DSis rising from 0 to 80% V_DSS

When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

R_θis measured at T_Japproximately 90°C.

.

This value determined from sample failure population,

I_SD≤ 100A, di/dt ≤ 1306A/μs, V_DD≤ V_(BR)DSS, T_J≤ 175°C.

starting T_J= 25°C, L= 0.04mH, R_G= 50Ω, I_AS= 90A, V_GS=10V.

2

www.irf.com

October 17, 2012

IRFR/U7440PbF

Dynamic @ T_J= 25°C (unless otherwise specified)

Symbol Parameter

Min. Typ. Max. Units

Conditions

gfs

Forward Transconductance

280 –––

–––

134

–––

S

V_DS= 10V, I_D= 90A

nC I_D=90A

_DS=20V

Q_g

Total Gate Charge

–––

89

26

63

11

39

51

34

Q_gs

Q_gd

Q_sync

t_d(on)

t_r

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Total Gate Charge Sync. (Q_g- Q_gd)

Turn-On Delay Time

Rise Time

V

V_GS= 10V

I_D= 90A, V_DS=0V, V_GS= 10V

ns V_DD= 20V

I_D= 30A

R_G= 2.7Ω

V_GS= 10V

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

C_iss

C_oss

C_rss

Input Capacitance

––– 4610 –––

pF V_GS= 0V

V_DS= 25V

Output Capacitance

Reverse Transfer Capacitance

––– 690

––– 460

––– 855

–––

ƒ = 1.0 MHz, See Fig. 5

C_osseff. (ER) Effective Output Capacitance (Energy Related)

C_osseff. (TR) Effective Output Capacitance (Time Related)

V_GS= 0V, V_DS= 0V to 32V

See Fig. 12

––– 1210 –––

Diode Characteristics

Symbol

Parameter

Continuous Source Current

Min. Typ. Max. Units

Conditions

MOSFET symbol

D

S

I_S

––– ––– 180

A

V

(Body Diode)

Pulsed Source Current

showing the

integral reverse

G

I_SM

––– ––– 760

(Body Diode)

Diode Forward Voltage

Reverse Recovery Time

p-n junction diode.

T_J= 25°C, I_S= 90A, V_GS= 0V

V_SD

t_rr

–––

0.9

34

35

33

34

1.8

1.3

–––

ns T_J= 25°C

T_J= 125°C

V_R= 34V,

I_F= 90A

di/dt = 100A/μs

Q_rr

Reverse Recovery Charge

Reverse Recovery Current

nC T_J= 25°C

T_J= 125°C

I_RRM

A

T_J= 25°C

3

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October 17, 2012

IRFR/U7440PbF

1000

100

10

1000

100

10

VGS

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

4.3V

VGS

TOP

15V

10V

7.0V

6.0V

5.5V

5.0V

4.5V

4.3V

BOTTOM

4.3V

1

4.3V

V

60μs PULSE WIDTH

Tj = 25°C

≤

≤ 60μs PULSE WIDTH

Tj = 175°C

0.1

1

0.1

1

10

100

0.1

1

10

100

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 3. Typical Output Characteristics

Fig 4. Typical Output Characteristics

1000

2.0

1.5

1.0

0.5

I

= 90A

D

V

= 10V

GS

100

10

1

T

= 175°C

J

T

= 25°C

= 10V

J

V

DS

≤

60μs PULSE WIDTH

0.1

2.0

3.0

V

4.0

5.0

6.0

7.0

8.0

-60 -40 -20

0

20 40 60 80 100 120 140 160 180

, Gate-to-Source Voltage (V)

GS

T

, Junction Temperature (°C)

J

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

100000

10000

1000

16

V

C

= 0V,

f = 1 MHZ

GS

I = 90A

D

= C + C , C SHORTED

iss

gs

gd ds

C

= C

V

= 32V

= 20V

rss

gd

DS

C

= C + C

ds

12

8

oss

gd

Ciss

Coss

Crss

4

0

100

0

20

40

60

80

100

120

1

10

100

Q

Total Gate Charge (nC)

G

V

, Drain-to-Source Voltage (V)

DS

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage

4

October 17, 2012

IRFR/U7440PbF

1000

100

10

1000

100

10

100μsec

T

= 175°C

J

1msec

imited by Package

L

T

= 25°C

J

OPERATION IN THIS AREA

10msec

LIMITED BY R (on)

DS

1

Tc = 25°C

DC

Tj = 175°C

Single Pulse

V

= 0V

1.4

GS

0.1

1

10

0.2

0.4

V

0.6

0.8

1.0

1.2

1.6

V

, Drain-toSource Voltage (V)

, Source-to-Drain Voltage (V)

DS

SD

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode

Forward Voltage

49

48

47

46

45

44

43

42

41

40

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Id = 1.0mA

0

10

20

30

40

-60 -40 -20 0 20 40 60 80 100120140160180

, Temperature ( °C )

V

Drain-to-Source Voltage (V)

T

DS,

J

Fig 11. Drain-to-Source Breakdown Voltage

Fig 12. Typical C_OSSStored Energy

10.0

V

= 5.5V

= 6.0V

= 7.0V

GS

8.0

V

GS

V

GS

VGS = 8.0V

=10V

6.0

4.0

2.0

0.0

V

GS

0

20 40 60 80 100 120 140 160 180 200

I , Drain Current (A)

D

Fig 13. Typical On-Resistance vs. Drain Current

5

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October 17, 2012

IRFR/U7440PbF

10

1

D = 0.50

0.20

0.10

0.05

0.1

0.02

0.01

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

100

10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche

ΔΤ

pulsewidth, tav, assuming

Tstart = 150°C.

j = 25°C and

1

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current vs.Pulsewidth

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in

excess of T_jmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 23a, 23b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

during avalanche).

180

160

140

120

100

80

TOP

BOTTOM 1.0% Duty Cycle

= 90A

Single Pulse

I

D

6. I_av= Allowable avalanche current.

7. ΔT = Allowable rise in junction temperature, not to exceed T_jmax(assumed as

25°C in Figure 15, 16).

60

t_{av =}Average time in avalanche.

D = Duty cycle in avalanche = t_av·f

40

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 14)

20

0

P_{D (ave)}= 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC

I_av= 2DT/ [1.3·BV·Z_th]

25

50

75

100

125

150

175

E_{AS (AR)}= P_{D (ave)}·t_av

Starting T , Junction Temperature (°C)

J

Fig 16. Maximum Avalanche Energy vs. Temperature

6

October 17, 2012

IRFR/U7440PbF

8

6

4

2

0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

I

= 54A

= 34V

F

V

R

T = 25°C

J

T = 125°C

J

I

= 100μA

= 250μA

= 1.0mA

= 1.0A

D

-75 -50 -25

0

J

25 50 75 100 125 150 175

, Temperature ( °C )

0

200

400

600

800

1000

T

di /dt (A/μs)

F

Fig. 18 - Typical Recovery Current vs. di_f/dt

Fig 17. Threshold Voltage vs. Temperature

120

8

I

= 54A

= 34V

I

= 90A

= 34V

F

V

100

80

60

40

20

0

R

T = 25°C

J

6

4

2

0

T = 125°C

J

T = 125°C

J

0

200

400

600

800

1000

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 19 - Typical Recovery Current vs. di_f/dt

Fig. 20 - Typical Stored Charge vs. di_f/dt

100

I

= 90A

= 34V

F

V

R

80

60

40

20

0

T = 25°C

J

T = 125°C

J

0

200

400

600

800

1000

di /dt (A/μs)

F

Fig. 21 - Typical Stored Charge vs. di_f/dt

7

www.irf.com

October 17, 2012

IRFR/U7440PbF

Driver Gate Drive

P.W.

D =

D.U.T

Period

+

-

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Current

Inductor Curent

I

SD

Ripple

≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

V

(BR)DSS

15V

t

p

DRIVER

+

L

V

DS

D.U.T

AS

R

G

V

DD

-

I

A

2V0_GV_S

Ω

0.01

t

p

I

AS

Fig 23b. Unclamped Inductive Waveforms

Fig 23a. Unclamped Inductive Test Circuit

R_D

V_DS

V

DS

90%

V_GS

D.U.T.

R_G

+

V_DD

-

10V

V_GS

10%

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

V

GS

t

r

t

f

d(on)

d(off)

Fig 24a. Switching Time Test Circuit

Fig 24b. Switching Time Waveforms

Id

Current Regulator

Same Type as D.U.T.

Vds

Vgs

50KΩ

.2μF

12V

.3μF

+

V

DS

D.U.T.

-

Vgs(th)

V

GS

3mA

I

D

G

Qgs1

Qgs2

Qgd

Qgodr

Current Sampling Resistors

Fig 25a. Gate Charge Test Circuit

Fig 25b. Gate Charge Waveform

October 17, 2012

8

IRFR/U7440PbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER

WITH ASSEMBLY

LOT CODE 1234

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR 1 = 2001

WEE K 16

IRFR120

116A

ASSEMBLED ON WW 16, 2001

IN THE ASSEMBLY LINE "A"

12

34

LINE A

Note: "P" in assembly lineposition

ASS EMBLY

LOT CODE

indicates "L ead-F ree"

"P" in assembly line position indicates

"Lead-F ree" qualification to the cons umer-level

PART NUMBER

DATE CODE

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

OR

IRFR120

12 34

LOGO

P = DESIGNATES LEAD-FREE

PRODUCT QUALIFIED TO THE

CONSUMER LEVEL (OPTIONAL)

ASSEMBLY

LOT CODE

YEAR 1 = 2001

WEEK 16

A = AS S E MB L Y S IT E CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

9

www.irf.com

October 17, 2012

IRFR/U7440PbF

I-Pak(TO-251AA)PackageOutline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

PART NUMBER

EXAMPLE: THIS IS AN IRFU120

INTERNATIONAL

RECTIFIER

LOGO

WIT H AS S E MBLY

LOT CODE 5678

DAT E CODE

YEAR 1 = 2001

WE EK 19

IRFU120

119A

78

ASSEMBLED ON WW19, 2001

IN THE ASSEMBLY LINE "A"

56

LINE A

AS S E MB L Y

LOT CODE

Note: "P" in assembly lineposition

indicates Lead-Free"

OR

PART NUMBER

DATE CODE

P = DE S IGNAT E S L E AD-F R E E

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

LOGO

IRFU120

56 78

YEAR 1 = 2001

AS S E MBL Y

LOT CODE

WE EK 19

A = AS S E MB L Y S IT E CODE

10

www.irf.com

October 17, 2012

IRFR/U7440PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Qualification information^†

Industrial^††

(per JEDEC JESD47F^†††guidelines)

MSL1

Qualification level

D-PAK

I-PAK

(per JEDEC J-STD-020D^†††)

Not applicable

Moisture Sensitivity Level

RoHS compliant

Yes

Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/

Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information: http:www.irf.com/whoto-call/salesrep/

Applicable version of JEDEC standard at the time of product release.

Revision History

Date

Comments

10/17/2012

Added I-Pak -All pages

Data and specifications subject to change without notice.

IR WORLD HEADQUARTERS: 101N Sepulveda., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

11

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October 17, 2012


型号：	IRFR7440TRPBF
厂家：	Infineon
描述：	Brushed Motor drive applications ??有刷电机驱动应用电机驱动
文件：	总11页 (文件大小：298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFR7440TRPBF [INFINEON]

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