IRFR7740PBF_15_技术文档

StrongIRFET™

IRFR7740PbF

IRFU7740PbF

HEXFET^®Power MOSFET

Application

 Brushed motor drive applications

 BLDC motor drive applications

 Battery powered circuits

 Half-bridge and full-bridge topologies

 Synchronous rectifier applications

 Resonant mode power supplies

 OR-ing and redundant power switches

 DC/DC and AC/DC converters

 DC/AC inverters

D

V_DSS

75V

R_DS(on)typ.

6.0m

7.2m

87A

G

max

I_D

S

D

Benefits

S

D

S

 Improved gate, avalanche and dynamic dV/dt ruggedness

 Fully characterized capacitance and avalanche SOA

 Enhanced body diode dV/dt and dI/dt capability

 Lead-free, RoHS compliant

G

I-Pak

D-Pak

IRFR7740PbF

IRFU7740PbF

G

D

S

Gate

Drain

Source

Standard Pack

Form

Base part number Package Type

Orderable Part Number

Quantity

75

Tube

IRFR7740PbF

IRFR7740TRPbF

IRFU7740PbF

IRFR7740PbF

IRFU7740PbF

D-Pak

I-Pak

Tape and Reel

Tube

2000

75

20

15

10

5

100

80

60

40

20

0

I

= 52A

D

T

= 125°C

J

= 25°C

0

5

10

15

20

25

50

75

100

125

150

175

T

, Case Temperature (°C)

C

V

Gate -to -Source Voltage (V)

GS,

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

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IRFR/U7740PbF

Absolute Maximum Rating

Symbol

Parameter

Max.

Units

I_D@ T_C= 25°C

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

87

62

I_D@ T_C= 100°C Continuous Drain Current, V_GS@ 10V (Silicon Limited)

A

I_DM

Pulsed Drain Current 

Maximum Power Dissipation

Linear Derating Factor

330

140

0.95

± 20

P_D@T_C= 25°C

W

W/°C

V

V_GS

Gate-to-Source Voltage

T_J

T_STG

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

-55 to + 175

300

°C

Avalanche Characteristics

Symbol

E_{AS (Thermally limited)}

I_AR

Max.

160

242

Units

mJ

Parameter

Single Pulse Avalanche Energy 

Single Pulse Avalanche Energy 

Avalanche Current 

A

mJ

See Fig 15, 16, 23a, 23b

E_AR

Repetitive Avalanche Energy 

Thermal Resistance

Symbol

Parameter

Typ.

–––

Max.

1.05

50

Units

Junction-to-Case 

R_JC

R_JA

Junction-to-Ambient (PCB Mount) 

Junction-to-Ambient 

°C/W

110

Static @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

Conditions

V_(BR)DSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

75

––– –––

V

V_GS= 0V, I_D= 250µA

–––

51

––– mV/°C Reference to 25°C, I_D= 1mA

V_(BR)DSS/T_J

R_DS(on)

6.0

7.2

V_GS= 10V, I_D= 52A 

m



7.0 –––

V_GS= 6.0V, I_D= 26A 

V_GS(th)

I_DSS

Gate Threshold Voltage

2.1 ––– 3.7

––– ––– 1.0

––– ––– 150

––– ––– 100

––– ––– -100

V

V_DS= V_GS, I_D= 100µA

V_DS=75 V, V_GS= 0V

Drain-to-Source Leakage Current

µA

V_DS=75V,V_GS= 0V,T_J=125°C

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Gate Resistance

V

_GS= 20V

_GS= -20V

I_GSS

R_G

nA

–––

2.2 –––



Notes:

Repetitive rating; pulse width limited by max. junction temperature.



Limited by T_Jmax, starting T_J= 25°C, L = 120µH, R_G= 50, I_AS= 52A, V_GS=10V.

I_SD 52A, di/dt  570A/µs, V_DD V_(BR)DSS, T_J175°C.

Pulse width  400µs; duty cycle  2%.







C_osseff. (TR) is a fixed capacitance that gives the same charging time as C_osswhile V_DSis rising from 0 to 80% V_DSS.

C_osseff. (ER) is a fixed capacitance that gives the same energy as C_osswhile V_DSis rising from 0 to 80% V_DSS

.

R_is measured at T_Japproximately 90°C.

When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to

application note #AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf



Limited by T_Jmax, starting T_J= 25°C, L = 1mH, R_G= 50, I_AS= 22A, V_GS=10V

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IRFR/U7740PbF

Dynamic Electrical Characteristics @ T_J= 25°C (unless otherwise specified)

Symbol

gfs

Parameter

Forward Transconductance

Total Gate Charge

Min.

110

–––

Typ. Max. Units

Conditions

–––

84

20

26

58

10

36

–––

126

–––

S

V_DS= 25V, I_D= 52A

Q_g

I_D= 52A

Q_gs

Gate-to-Source Charge

Gate-to-Drain Charge

Total Gate Charge Sync. (Qg – Qgd)

Turn-On Delay Time

V_DS= 38V

V_GS= 10V 

nC

Q_gd

Q_sync

t_d(on)

t_r

V_DD= 38V

I_D= 52A

Rise Time

ns

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

–––

55

30

–––

R_G= 2.7

V

_GS= 10V 

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

4430

370

230

V_GS= 0V

V_DS= 25V

ƒ = 1.0MHz, See Fig.7

pF

Effective Output Capacitance

(Energy Related)

C_{oss eff.(ER)}

C_{oss eff.(TR)}

–––

340

440

–––

V_GS= 0V, V_DS= 0V to 60V

V_GS= 0V, V_DS= 0V to 60V

Output Capacitance (Time Related)

Diode Characteristics

Symbol

Parameter

Min.

Typ. Max. Units

Conditions

MOSFET symbol

showing the

integral reverse

p-n junction diode.

D

Continuous Source Current

(Body Diode)

I_S

–––

87

A

G

Pulsed Source Current

(Body Diode)

I_SM

–––

330

1.2

S

V_SD

Diode Forward Voltage

V

T_J= 25°C,I_S= 52A,V_GS= 0V 

dv/dt

Peak Diode Recovery dv/dt

–––

12

35

40

45

61

2.3

––– V/ns T_J= 175°C,I_S= 52A,V_DS= 75V 

–––

T_J= 25°C

V_DD= 64V

I_F= 52A,

t_rr

Reverse Recovery Time

ns

T_J= 125°C

T_J= 25°C di/dt = 100A/µs 

Q_rr

Reverse Recovery Charge

Reverse Recovery Current

nC

A

T_J= 125°C

T_J= 25°C



I_RRM

3

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IRFR/U7740PbF

1000

100

10

1000

100

10

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

TOP

4.5V

BOTTOM

4.5V

60µs PULSE WIDTH

Tj = 175°C



60µs PULSE WIDTH

Tj = 25°C



1

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

DS

V

, Drain-to-Source Voltage (V)

DS

Fig 4. Typical Output Characteristics

Fig 3. Typical Output Characteristics

3.0

1000

100

10

I

= 52A

D

V

= 10V

2.5

2.0

1.5

1.0

0.5

0.0

GS

T

= 175°C

J

T

= 25°C

J

1

V

= 25V

DS

60µs PULSE WIDTH

0.1

-60 -40 -20 0 20 40 60 80 100120140160180

2.0

3.0

4.0

5.0

6.0

T , Junction Temperature (°C)

J

V

, Gate-to-Source Voltage (V)

GS

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

100000

10000

1000

14.0

V

= 0V,

f = 1 MHZ

GS

I = 52A

D

C

= C + C , C

SHORTED

iss

gs

gd

ds

12.0

= C

rss

oss

gd

= C + C

ds

gd

V

= 60V

= 38V

= 15V

DS

10.0

8.0

6.0

4.0

2.0

0.0

C

iss

C

oss

C

rss

100

1

10

100

0

20

40

60

80

100

120

V

, Drain-to-Source Voltage (V)

DS

Q , Total Gate Charge (nC)

G

Fig 8. Typical Gate Charge vs.

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

Gate-to-Source Voltage

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IRFR/U7740PbF

1000

100

10

100µsec

1msec

100

10

T = 175°C

J

OPERATION

IN THIS

AREA

LIMITED BY

T = 25°C

J

1

R

(on)

DS

10msec

DC

1

0.1

0.01

Tc = 25°C

Tj = 175°C

Single Pulse

V

= 0V

1.2

GS

0.1

1

10

0.2

0.4

V

0.6

0.8

1.0

1.4

V

, Drain-toSource Voltage (V)

, Source-to-Drain Voltage (V)

DS

SD

Fig 10. Maximum Safe Operating Area

Fig 9. Typical Source-Drain Diode Forward Voltage

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

95

Id = 1.0mA

90

85

80

75

-10

0

10 20 30 40 50 60 70 80

-60 -40 -20

0

20 40 60 80 100120140160180

, Temperature ( °C )

T

V

Drain-to-Source Voltage (V)

J

DS,

Fig 11. Drain-to-Source Breakdown Voltage

Fig 12. Typical C_ossStored Energy

11.0

V

= 5.5V

= 6.0V

= 7.0V

= 8.0V

=10V

GS

10.0

9.0

8.0

7.0

6.0

0

50

100

150

200

I

, Drain Current (A)

D

Fig 13. Typical On-Resistance vs. Drain Current

5

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IRFR/U7740PbF

10

1

D = 0.50

0.20

0.10

0.1

0.05

0.02

0.01

Notes:

SINGLE PULSE

1. Duty Factor D = t1/t2

( THERMAL RESPONSE )

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

t

, Rectangular Pulse Duration (sec)

1

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

10

1

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150°C and

Tstart = 25°C (Single Pulse)

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming j = 25°C and

Tstart = 150°C.

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Avalanche Current vs. Pulse Width

200

160

120

80

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1.Avalanche failures assumption:

TOP

Single Pulse

BOTTOM 1.0% Duty Cycle

= 52A

I

D

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T_jmax. This is validated for every

part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not

exceeded.

3. Equation below based on circuit and waveforms shown in Figures

23a, 23b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage

increase during avalanche).

40

6. I_av= Allowable avalanche current.

7. T = Allowable rise in junction temperature, not to exceed T_jmax

(assumed as 25°C in Figure 15, 16).

0

t_av= Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

Z_thJC(D, t_av) = Transient thermal resistance, see Figures 13)

25

50

75

100

125

150

175

Starting T , Junction Temperature (°C)

J

PD (ave) = 1/2 ( 1.3·BV·I_av) = T/ Z_thJC

I

_av= 2T/ [1.3·BV·Z_th]

E_{AS (AR)}= P_{D (ave)· av}

t

Fig 16. Maximum Avalanche Energy vs. Temperature

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IRFR/U7740PbF

4.0

3.5

3.0

2.5

2.0

1.5

1.0

16

12

8

I

= 35A

= 64V

F

V

R

T = 25°C

J

T = 125°C

J

I

= 100µA

= 250µA

= 1.0mA

= 1.0A

D

I

D

I

D

4

I

D

0

-75 -50 -25

0

25 50 75 100 125 150 175

0

200

400

600

800

1000

T , Temperature ( °C )

di /dt (A/µs)

J

F

Fig 17. Threshold Voltage vs. Temperature

Fig 18. Typical Recovery Current vs. dif/dt

20

16

12

8

300

I

= 52A

= 64V

I

= 35A

= 64V

F

V

R

250

200

150

100

50

T = 25°C

J

T = 125°C

J

T = 25°C

J

T = 125°C

J

4

0

200

400

600

800

1000

0

200

400

600

800

1000

di /dt (A/µs)

F

Fig 19. Typical Recovery Current vs. dif/dt

Fig 20. Typical Stored Charge vs. dif/dt

300

I

= 52A

F

V

= 64V

R

250

200

150

100

50

T = 25°C

J

T = 125°C

J

0

200

400

600

800

1000

di /dt (A/µs)

F

Fig 21. Typical Stored Charge vs. dif/dt

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IRFR/U7740PbF

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET^®Power MOSFETs

V

(BR)DSS

t

p

15V

DRIVER

+

L

V

DS

D.U.T

AS

R

G

V

DD

-

I

A

20V

I

0.01



t

p

AS

Fig 23a. Unclamped Inductive Test Circuit

Fig 23b. Unclamped Inductive Waveforms

Fig 24a. Switching Time Test Circuit

Fig 24b. Switching Time Waveforms

Id

Vds

Vgs

VDD

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 25b. Gate Charge Waveform

Fig 25a. Gate Charge Test Circuit

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IRFR/U7740PbF

D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER

WITH ASSEMBLY

LOT CODE 1234

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR 1 = 2001

WEEK 16

IRFR120

116A

ASSEMBLED ON WW 16, 2001

IN THE ASSEMBLY LINE "A"

12

34

LINE A

Note: "P" in assembly line position

ASSEMBLY

LOT CODE

indicates "Lead-Free"

"P" in assembly line position indicates

"Lead-Free" qualification to the consumer-level

PART NUMBER

DATE CODE

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

OR

IRFR120

12 34

LOGO

P = DESIGNATES LEAD-FREE

PRODUCT QUALIFIED TO THE

CONSUMER LEVEL (OPTIONAL)

ASSEMBLY

LOT CODE

YEAR 1 = 2001

WEEK 16

A = ASSEMBLY SITE CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFR/U7740PbF

I-Pak (TO-251AA) Package Outline (Dimensions are shown in millimeters (inches))

I-Pak (TO-251AA) Part Marking Information

PART NUMBER

EXAMPLE: THIS IS AN IRFU120

WITH ASSEMBLY

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR 1 = 2001

WEEK 19

IRFU120

119A

78

LOT CODE 5678

ASSEMBLED ON WW 19, 2001

56

IN THE ASSEMBLY LINE "A"

LINE A

ASSEMBLY

LOT CODE

Note: "P" in assembly line position

indicates Lead-Free"

OR

PART NUMBER

DATE CODE

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

LOGO

IRFU120

56

78

YEAR 1 = 2001

ASSEMBLY

LOT CODE

WEEK 19

A = ASSEMBLY SITE CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

10

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IRFR/U7740PbF

D-Pak (TO-252AA) Tape & Reel Information (Dimensions are shown in millimeters (inches))

TR

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFR/U7740PbF

Qualification Information^†

Qualification Level

Industrial

(per JEDEC JESD47F) ^††

D-Pak

I-Pak

Moisture Sensitivity Level

RoHS Compliant

MSL1

Yes

†

Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/

†† Applicable version of JEDEC standard at the time of product release.

Revision History

Date

Comment

Updated E_{AS (L =1mH)}= 242mJ on page 2

Updated note 9 “Limited by T_Jmax, starting T_J= 25°C, L = 1mH, R_G= 50, I_AS= 22A, V_GS=10V” on page 2

11/5/2014

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

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型号：	IRFR7740PBF_15
厂家：	Infineon
描述：	Brushed motor drive applications
文件：	总12页 (文件大小：573K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFR7740PBF_15 [INFINEON]

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