IRFS4310ZTRLPBF [INFINEON]
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| 型号： | IRFS4310ZTRLPBF |
| 厂家： | 
Infineon |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 96894
IRFB4310
IRFS4310
IRFSL4310
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
S
VDSS
RDS(on) typ.
100V
5.6m:
G
7.0m:
140A
max.
Benefits
l Worldwide Best RDS(on) in TO-220
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
ID
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
G D S
G D S
G D S
D2Pak
IRFS4310
TO-262
IRFSL4310
TO-220AB
IRFB4310
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Max.
140c
97 c
550
Units
A
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current d
PD @TC = 25°C
330
Maximum Power Dissipation
Linear Derating Factor
W
2.2
W/°C
V
VGS
± 20
Gate-to-Source Voltage
14
Peak Diode Recovery f
Operating Junction and
dV/dt
TJ
V/ns
°C
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
980
mJ
A
Avalanche Currentꢀc
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy g
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.45
–––
62
Units
RθJC
RθCS
RθJA
RθJA
Junction-to-Case k
Case-to-Sink, Flat Greased Surface , TO-220
0.50
–––
°C/W
Junction-to-Ambient, TO-220 k
Junction-to-Ambient (PCB Mount) , D2Pak jk
–––
40
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1
11/3/04
IRF/B/S/SL4310
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
100 ––– –––
––– 0.064 ––– V/°C Reference to 25°C, ID = 1mAd
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
5.6
7.0
4.0
20
V
V
V
V
GS = 10V, ID = 75A g
mΩ
V
VGS(th)
–––
DS = VGS, ID = 250µA
IDSS
Drain-to-Source Leakage Current
––– –––
µA
DS = 100V, VGS = 0V
––– ––– 250
––– ––– 200
––– ––– -200
DS = 100V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
nA VGS = 20V
VGS = -20V
RG
–––
1.4
–––
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 75A
nC ID = 75A
DS = 80V
VGS = 10V g
DD = 65V
160 ––– –––
S
Qg
––– 170 250
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
–––
–––
–––
46
62
26
–––
–––
–––
V
ns
V
Rise Time
––– 110 –––
ID = 75A
td(off)
tf
Turn-Off Delay Time
–––
–––
68
78
–––
–––
RG = 2.6Ω
VGS = 10V g
Fall Time
Ciss
Coss
Crss
Input Capacitance
––– 7670 –––
––– 540 –––
––– 280 –––
––– 650 –––
––– 720.1 –––
pF
V
GS = 0V
Output Capacitance
VDS = 50V
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)i
Effective Output Capacitance (Time Related)h
ƒ = 1.0MHz
Coss eff. (ER)
oss eff. (TR)
V
GS = 0V, VDS = 0V to 80V j, See Fig.11
GS = 0V, VDS = 0V to 80V h, See Fig. 5
C
V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
––– –––
A
MOSFET symbol
140c
D
S
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
ISM
––– ––– 550
(Body Diode)ꢀdi
p-n junction diode.
VSD
trr
Diode Forward Voltage
––– –––
1.3
68
V
TJ = 25°C, IS = 75A, VGS = 0V g
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
45
55
82
ns
IF = 75A
83
di/dt = 100A/µs g
Qrr
120
nC
A
––– 120 180
––– 3.3 –––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
.
.
Limited by TJmax, starting TJ = 25°C, L = 0.35mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
ISD ≤ 75A, di/dt ≤ 550A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢁ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF/B/S/SL4310
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
≤ 60µs PULSE WIDTH
≤ 60µs PULSE WIDTH
4.5V
1
Tj = 175°C
Tj = 25°C
1
0.1
1
10
100
0.1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 50V
J
V
DS
≤ 60µs PULSE WIDTH
1
3.0
4.0
5.0
6.0
7.0
8.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
12000
10000
8000
6000
4000
2000
0
20
V
C
= 0V,
f = 1 MHZ
GS
I = 75A
D
= C + C , C SHORTED
iss
gs
gd ds
V
= 80V
DS
C
= C
rss
gd
16
12
8
VDS= 50V
VDS= 20V
C
= C + C
oss
ds
gd
Ciss
4
Coss
Crss
0
0
40
80
120 160 200 240 280
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRF/B/S/SL4310
1000.0
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100.0
10.0
1.0
100µsec
T
= 25°C
J
1
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
DC
V
= 0V
GS
0.1
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
1
10
100
1000
V
V
, Drain-toSource Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
140
120
100
80
120
115
110
105
100
LIMITED BY PACKAGE
60
40
20
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2400
I
D
TOP
12A
17A
75A
2000
1600
1200
800
400
0
BOTTOM
0
20
V
40
60
80
100
120
25
50
75
100
125
150
175
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
DS,
J
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRF/B/S/SL4310
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R2
R2
R1
Ri (°C/W) τi (sec)
0.1962 0.00117
τ
0.01
J τJ
τ
0.02
0.01
τ
Cτ
1τ1
Ci= τi/Ri
τ
2τ2
0.2542 0.016569
0.001
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
0.05
0.10
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
1000
800
600
400
200
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
TOP
BOTTOM 1% Duty Cycle
= 75A
Single Pulse
I
D
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRF/B/S/SL4310
20
16
12
8
5.0
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250µA
4.0
3.0
2.0
1.0
I
= 30A
= 85V
F
V
T
R
4
= 125°C
J
T
= 25°C
J
0
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
100 200 300 400 500 600 700 800 900 1000
T
di / dt - (A / µs)
f
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
500
20
400
300
200
100
0
16
12
8
I
= 30A
= 85V
I
= 45A
= 85V
F
F
V
T
V
T
R
R
4
0
= 125°C
= 25°C
= 125°C
= 25°C
J
J
T
T
J
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / µs)
f
di / dt - (A / µs)
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
500
400
300
200
100
0
I
= 45A
F
V
= 85V
R
T
= 125°C
= 25°C
J
J
T
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / µs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRF/B/S/SL4310
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRF/B/S/SL4310
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
- B -
3.78 (.149)
3.54 (.139)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
LEAD ASSIGNMENTS
1 - GATE
1
2
3
2 - DRAIN
3 - SOURCE
4 - DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
PART NUMBER
ASS EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
INT ERNAT IONAL
RECT IFIER
LOGO
Note: "P" in assembly line
position indicates "Lead-Free"
DAT E CODE
YEAR 7 = 1997
WEEK 19
AS S E MB LY
LOT CODE
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRF/B/S/SL4310
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
ASSEMBLED ON WW 19, 1997
RECTIFIER
IN THE ASSEMBLY LINE "C"
LOGO
DATE CODE
YEAR 7 = 1997
WEE K 19
Note: "P" in assembly line
pos ition indicates "L ead-F ree"
AS S E MB L Y
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
AS S E MB L Y
LOT CODE
WE E K 19
A = AS S E MB L Y S IT E CODE
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9
IRF/B/S/SL4310
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
THIS IS AN IRF530S WITH
PART NUMBER
LOT CODE 8024
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
Note: "P" in assembly line
pos ition indicates "Lead-Free"
AS S E MB L Y
LOT CODE
LINE L
OR
PART NUMBER
DATE CODE
INTERNATIONAL
RECTIFIER
LOGO
F530S
P = DE S IGNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
YEAR 0 = 2000
AS S E MB LY
LOT CODE
WEEK 02
A = AS S E MB L Y S IT E CODE
10
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IRF/B/S/SL4310
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/04
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11
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