IRLR3705ZPBF [INFINEON]
AUTOMOTIVE MOSFET HEXFET Power MOSFET; 汽车MOSFET HEXFET功率MOSFET型号: | IRLR3705ZPBF |
厂家: | Infineon |
描述: | AUTOMOTIVE MOSFET HEXFET Power MOSFET |
文件: | 总11页 (文件大小:350K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 95956
AUTOMOTIVE MOSFET
IRLR3705ZPbF
IRLU3705ZPbF
Features
l
l
l
l
l
l
l
Logic Level
Advanced Process Technology
HEXFET® Power MOSFET
UltraLowOn-Resistance
175°COperatingTemperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 55V
RDS(on) = 8.0mΩ
G
Description
ID = 42A
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features com-
bine to make this design an extremely efficient and
reliable device for use in Automotive applications
and a wide variety of other applications.
S
D-Pak
I-Pak
IRLU3705Z
IRLR3705Z
Absolute Maximum Ratings
Parameter
Max.
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
I
I
I
I
@ T = 25°C
89
D
D
D
C
@ T = 100°C
63
42
A
C
@ T = 25°C
C
360
130
DM
P
@T = 25°C Power Dissipation
W
D
C
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
0.88
± 16
W/°C
V
V
GS
EAS (Thermally limited)
110
190
mJ
Single Pulse Avalanche Energy Tested Value
Avalanche Current
EAS (Tested )
IAR
See Fig.12a, 12b, 15, 16
A
Repetitive Avalanche Energy
Operating Junction and
EAR
mJ
T
T
-55 to + 175
J
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
Max.
1.14
40
Units
Junction-to-Case
RθJC
RθJA
RθJA
Junction-to-Ambient (PCB mount)
Junction-to-Ambient
–––
°C/W
–––
110
HEXFET® isaregisteredtrademarkofInternationalRectifier.
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1
12/21/04
IRLR/U3705ZPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
55 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.053 ––– V/°C Reference to 25°C, ID = 1mA
mΩ
RDS(on)
Static Drain-to-Source On-Resistance
–––
–––
–––
1.0
6.5
–––
–––
–––
–––
–––
–––
–––
8.0
11
VGS = 10V, ID = 42A
VGS = 5.0V, ID = 34A
12
V
V
V
V
V
GS = 4.5V, ID = 21A
VGS(th)
gfs
Gate Threshold Voltage
3.0
–––
20
V
S
DS = VGS, ID = 250µA
DS = 25V, ID = 42A
Forward Transconductance
Drain-to-Source Leakage Current
89
IDSS
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA
DS = 55V, VGS = 0V
250
200
DS = 55V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA VGS = 16V
GS = -16V
––– -200
V
Qg
Qgs
Qgd
td(on)
tr
44
13
66
ID = 42A
nC VDS = 44V
VGS = 5.0V
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
–––
–––
–––
–––
–––
–––
–––
22
17
VDD = 28V
Rise Time
150
33
I
D = 42A
td(off)
tf
Turn-Off Delay Time
ns
RG = 4.2 Ω
Fall Time
70
VGS = 5.0V
D
S
LD
Internal Drain Inductance
4.5
Between lead,
nH 6mm (0.25in.)
from package
G
LS
Internal Source Inductance
–––
7.5
–––
and center of die contact
VGS = 0V
DS = 25V
pF ƒ = 1.0MHz
Ciss
Coss
Crss
Coss
Coss
Input Capacitance
––– 2900 –––
Output Capacitance
–––
–––
420
230
–––
–––
V
Reverse Transfer Capacitance
Output Capacitance
––– 1550 –––
V
V
V
GS = 0V, VDS = 1.0V, ƒ = 1.0MHz
GS = 0V, VDS = 44V, ƒ = 1.0MHz
GS = 0V, VDS = 0V to 44V
Output Capacitance
–––
–––
320
500
–––
–––
Coss eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
Continuous Source Current
–––
–––
42
MOSFET symbol
S
(Body Diode)
A
showing the
I
Pulsed Source Current
–––
–––
360
integral reverse
SM
(Body Diode)
p-n junction diode.
V
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
21
1.3
42
28
V
T = 25°C, I = 42A, V = 0V
J S GS
SD
t
ns T = 25°C, I = 42A, VDD = 28V
J F
rr
di/dt = 100A/µs
Q
14
nC
rr
t
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
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IRLR/U3705ZPbF
1000
100
10
1000
100
10
VGS
12V
10V
8.0V
5.0V
4.5V
3.5V
3.0V
2.8V
VGS
12V
10V
8.0V
5.0V
4.5V
3.5V
3.0V
2.8V
TOP
TOP
BOTTOM
BOTTOM
2.8V
2.8V
≤ 60µs PULSE WIDTH
Tj = 25°C
≤ 60µs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
100.0
10.0
100
T
= 25°C
T
= 25°C
J
J
80
60
40
20
0
T
= 175°C
J
T
= 175°C
J
V
= 15V
DS
≤ 60µs PULSE WIDTH
V
= 8.0V
DS
380µs PULSE WIDTH
1.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
, Gate-to-Source Voltage (V)
0
10 20 30 40 50 60 70 80
Drain-to-Source Current (A)
V
GS
I
D,
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
vs. Drain Current
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3
IRLR/U3705ZPbF
5000
12
10
8
V
C
= 0V,
f = 1 MHZ
GS
I
= 42A
D
= C + C , C SHORTED
iss
gs
gd ds
V = 44V
DS
VDS= 28V
VDS= 11V
C
= C
rss
gd
4000
3000
2000
1000
0
C
= C + C
ds
oss
gd
Ciss
6
4
2
Coss
Crss
0
0
20
40
60
80
100
1
10
100
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge vs.
Fig 5. Typical Capacitance vs.
Gate-to-SourceVoltage
Drain-to-SourceVoltage
10000
1000.0
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
1000
100
10
100.0
10.0
1.0
T
= 175°C
J
100µsec
1msec
10msec
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
DC
0.1
0.1
1
10
, Drain-toSource Voltage (V)
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
V
V
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRLR/U3705ZPbF
2.5
2.0
1.5
1.0
0.5
100
80
60
40
20
0
I
= 42A
D
LIMITED BY PACKAGE
V
= 10V
GS
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 10. Normalized On-Resistance
Fig 9. Maximum Drain Current vs.
vs.Temperature
CaseTemperature
10
1
0.1
D = 0.50
0.20
0.10
R1
R1
R2
R2
Ri (°C/W) τi (sec)
0.6984 0.000465
τ
J τJ
τ
τ
Cτ
0.05
1τ1
Ci= τi/Ri
τ
2τ2
0.4415 0.004358
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U3705ZPbF
500
400
300
200
100
0
15V
I
D
TOP
5.3A
7.0A
42A
DRIVER
L
V
DS
BOTTOM
D.U.T
AS
R
G
+
-
V
DD
I
A
V
20V
GS
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
vs. Drain Current
Q
G
10 V
Q
Q
2.5
2.0
1.5
1.0
0.5
0.0
GS
GD
I
I
I
= 250µA
= 150µA
= 50µA
D
D
D
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
L
VCC
DUT
0
-75 -50 -25
0
J
25 50 75 100 125 150 175
, Temperature ( °C )
1K
T
Fig 14. Threshold Voltage vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U3705ZPbF
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
120
100
80
60
40
20
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
TOP
BOTTOM 1% Duty Cycle
= 42A
Single Pulse
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
Fig 16. Maximum Avalanche Energy
EAS (AR) = PD (ave)·tav
vs.Temperature
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7
IRLR/U3705ZPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b. Switching Time Waveforms
8
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IRLR/U3705ZPbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
INTERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 9 = 1999
WEEK 16
IRFU120
916A
12
34
LINE A
Note: "P" in assembly lineposition
ASSEMBLY
LOT CODE
indicates "Lead-F ree"
OR
PART NUMBER
DAT E CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12 34
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEEK 16
A= ASSEMBLY SITE CODE
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9
IRLR/U3705ZPbF
I-Pak (TO-251AA) Package Outline
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
INTERNATIONAL
RECTIFIER
LOGO
WIT H AS S EMBLY
LOT CODE 5678
ASS EMBLED ON WW 19, 1999
IN THE ASSEMBLY LINE "A"
DATE CODE
YEAR 9 = 1999
WEEK 19
IRFU120
919A
78
56
LINE A
ASSEMBLY
LOT CODE
Note: "P" in assembly line
pos ition indicates "Lead-F ree"
OR
PART NUMBER
DATE CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPTIONAL)
INT ERNATIONAL
RECTIFIER
LOGO
IRFU120
56 78
YEAR 9 = 1999
AS S EMBLY
LOT CODE
WEEK 19
A = AS S EMBLY S ITE CODE
10
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IRLR/U3705ZPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
.
Limited by TJmax, starting TJ = 25°C, L = 0.12mH
ꢀ
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
RG = 25Ω, IAS = 42A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
This value determined from sample failure population. 100%
tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Rθ is measured at TJ approximately 90°C
Data and specifications subject to change without notice.
This product has been designed for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
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11
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