IRLR8721TRRPBF [INFINEON]

Power Field-Effect Transistor, 65A I(D), 30V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, PLASTIC, DPAK-3;


型号：	IRLR8721TRRPBF
厂家：	Infineon
描述：	Power Field-Effect Transistor, 65A I(D), 30V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, PLASTIC, DPAK-3
文件：	总12页 (文件大小：293K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRLR8721PbF

IRLU8721PbF

HEXFET^®Power MOSFET

Applications

V_DSSR_DS(on)max

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification

for Telecom and Industrial Use

l Lead-Free

8.4m

30V

8.5nC

Benefits

D-Pak

IRLR8721PbF

l Very Low RDS(on) at 4.5V V_GS

l Ultra-Low Gate Impedance

l Fully Characterized Avalanche Voltage

and Current

I-Pak

IRLU8721PbF

Gate

Drain

Source

Base Part Number Package Type

Standard Pack

Form

Tube

Orderable part number

Quantity

2000

3000

IRLR8721PbF

D-Pak

IRLR8721PbF

IRLR8721TRPbF

IRLR8721TRLPbF

IRLR8721TRRPbF

IRLU8721PbF

Tape and Reel

Tape and Reel Left

Tape and Reel Right

Tube

IRLU8721PbF

I-Pak

Absolute Maximum Ratings

Parameter

Max.

Units

V_DS

Drain-to-Source Voltage

± 20

Gate-to-Source Voltage

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

@ T_C= 25°C

@ T_C= 100°C

260

@T_C= 25°C

@T_C= 100°C

Maximum Power Dissipation

Linear Derating Factor

Operating Junction and

0.43

-55 to + 175

W/°C

°C

Storage Temperature Range

STG

Thermal Resistance

Parameter

Junction-to-Case

Typ.

–––

Max.

2.3

Units

R_JC

R_JA

Junction-to-Ambient (PCB Mount)

°C/W

Junction-to-Ambient

110

Notes through ꢀ are on page 11

December 4, 2012

IRLR/U8721PbF

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Drain-to-Source Breakdown Voltage

Min. Typ. Max. Units

Conditions

V_GS= 0V, I_D= 250μA

BV_DSS

–––

V_DSS/T_J

R_DS(on)

Breakdown Voltage Temp. Coefficient –––

––– mV/°C Reference to 25°C, I_D= 1mA



Static Drain-to-Source On-Resistance

–––

1.35

–––

6.3

8.4

V_GS= 10V, I_D= 25A

10.1 11.8

2.35

––– mV/°C

V_GS= 4.5V, I_D= 20A

V_GS(th)

V_GS(th)

I_DSS

Gate Threshold Voltage

1.9

-6.8

–––

8.5

1.9

1.2

3.4

2.0

4.6

7.9

2.3

8.8

V_DS= V_GS, I_D= 25μA

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

1.0

150

100

-100

–––

μA

_DS= 24V, V_GS= 0V

V_DS= 24V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

nA V_GS= 20V

V_GS= -20V

gfs

Q_g

V_DS= 15V, I_D= 20A

–––

Q_gs1

Q_gs2

Q_gd

Q_godr

Q_sw

Q_oss

R_G

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

–––

3.8

_DS= 15V

_GS= 4.5V

I_D= 20A

Gate Charge Overdrive

Switch Charge (Q_gs2+ Q_gd)

See Fig. 16

Output Charge

V_DS= 16V, V_GS= 0V



Gate Resistance

Turn-On Delay Time

Rise Time

t_d(on)

t_r

t_d(off)

t_f

–––

_DD= 15V, V_GS= 4.5V

I_D= 20A

Turn-Off Delay Time

Fall Time

9.4

6.5

R_G= 1.8

See Fig. 14

V_GS= 0V

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 1030 –––

–––

350

110

–––

pF V_DS= 15V

ƒ = 1.0MHz

Avalanche Characteristics

Parameter

Typ.

–––

Max.

Units

Single Pulse Avalanche Energy

E_AS

I_AR

Avalanche Current

Repetitive Avalanche Energy

E_AR

6.5

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

I_S

Continuous Source Current

–––

(Body Diode)

Pulsed Source Current

showing the

integral reverse

I_SM

–––

260

(Body Diode)

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

–––

1.0

T = 25°C, I = 20A, V = 0V

J S GS

Reverse Recovery Time

Reverse Recovery Charge

Forward Turn-On Time

ns T = 25°C, I = 20A, V_DD= 15V

J F

Q_rr

t_on

di/dt = 300A/μs

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

December 4, 2012

IRLR/U8721PbF

1000

100

1000

100

VGS

10V

VGS

10V

TOP

8.0V

5.0V

4.5V

4.0V

3.5V

3.0V

2.7V

8.0V

5.0V

4.5V

4.0V

3.5V

3.0V

2.7V

BOTTOM

2.7V

60μs PULSE WIDTH

Tj = 175°C



60μs PULSE WIDTH

Tj = 25°C



0.1

100

0.1

100

, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

2.0

= 25A

= 10V

100

= 175°C

1.5

1.0

0.5

= 25°C

= 15V

60μs PULSE WIDTH

0.1

-60 -40 -20 0 20 40 60 80 100120140160180

, Junction Temperature (°C)

, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

December 4, 2012

IRLR/U8721PbF

10000

1000

100

5.0

4.0

3.0

2.0

1.0

0.0

= 0V,

= C

f = 1 MHZ

I = 20A

= 24V

= 15V

= 6.0V

+ C , C

SHORTED

iss

= C

rss

oss

= C + C

iss

oss

rss

, Drain-to-Source Voltage (V)

100

Q , Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs.

Fig 5. Typical Capacitance vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000

100

1000

100

OPERATION IN THIS AREA

LIMITED BY R

(on)

100μsec

1msec

= 175°C

= 25°C

10msec

Tc = 25°C

Tj = 175°C

Single Pulse

= 0V

0.1

0.0

0.5

1.0

1.5

2.0

100

, Source-to-Drain Voltage (V)

, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

December 4, 2012

Fig 7. Typical Source-Drain Diode

Forward Voltage

IRLR/U8721PbF

2.5

2.0

1.5

1.0

0.5

Limited By Package

= 25μA

100

125

150

175

-75 -50 -25

25 50 75 100 125 150175 200

, Case Temperature (°C)

T , Temperature ( °C )

Fig 9. Maximum Drain Current vs.

Fig 10. Threshold Voltage vs. Temperature

Case Temperature

D = 0.50

0.20

0.10

0.05

R₁

R₂

R₃

Ri (°C/W) i (sec)

0.3501 0.000072

0.1

0.01



0.02

0.01

^J_J



^C



¹₁



²₂

³₃

1.1877 0.001239

0.7635 0.010527

Ci= iRi



Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

IRLR/U8721PbF

400

350

300

250

200

150

100

15V

TOP

1.1A

1.4A

BOTTOM 20A

DRIVER

D.U.T

20V

0.01



Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

100

125

150

175

Starting T , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

R_D

V_DS

Fig 12b. Unclamped Inductive Waveforms

V_GS

D.U.T.

R_G

⁺V_DD

Current Regulator

Same Type as D.U.T.

V_GS

PulseWidth µs

Duty Factor 

50K

.2F

12V

.3F

Fig 14a. Switching Time Test Circuit

D.U.T.

90%

3mA

10%

d(on)

d(off)

Current Sampling Resistors

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

December 4, 2012

IRLR/U8721PbF

100

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150°C and

Tstart =25°C (Single Pulse)

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming  j = 25°C and

Tstart = 150°C.

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

tav (sec)

1.0E-01

1.0E+00

1.0E+01

1.0E+02

Fig 15. Typical Avalanche Current vs. Pulsewidth

December 4, 2012

IRLR/U8721PbF

Driver Gate Drive

P.W.

D =

D.U.T

Period

=10V

Circuit Layout Considerations

 Low Stray Inductance

Ground Plane

Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

V_DD

Re-Applied

Voltage

dv/dt controlled by R_G

R_G

Body Diode

Forward Drop

Driver same type as D.U.T.

I_SDcontrolled by Duty Factor "D"

D.U.T. - Device Under Test

Inductor Curent

Ripple  5%

* V_GS= 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgodr

Qgd

Fig 16. Gate Charge Waveform

December 4, 2012

IRLR/U8721PbF

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power

losses in the switching elements of the circuit - Q1

and Q2. Power losses in the high side switch Q1,

also called the Control FET, are impacted by the R_ds(on)

of the MOSFET, but these conduction losses are only

about one half of the total losses.

 P

 P  P^*

loss

conduction

drive

output

 I_rms² R_ds(on)

loss  

 Q  V  f

Power losses in the control switch Q1 are given

by;







Q_oss



V  f  Q  V  f

P_loss= P_conduction+ P_switching+ P_drive+ P_output











 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

 I ² R_{ds(on )}

_rms



loss

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.



Q_gd

i_g



Q_gs2

i_g







 

 I 

 V  f  I 

 V  f



 



 Q  V  f





Q_oss







V  f



This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFETdata sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

December 4, 2012

IRLR/U8721PbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

December 4, 2012

IRLR/U8721PbF

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

December 4, 2012

IRLR/U8721PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Notes:

Calculated continuous current based on maximum allowable

Repetitive rating; pulse width limited by

max. junction temperature.

junction temperature. Package limitation current is 50A.

Starting T_J= 25°C, L = 0.47mH

R_G= 25, I_AS= 20A.

Pulse width  400μs; duty cycle  2%.

ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to

application note #AN-994.

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

Visit us at www.irf.com for sales contact information.

December 4, 2012

IRLR8721TRRPBF [INFINEON]

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