IRS2890DS [INFINEON]
EiceDRIVER™ 600 V half-bridge gate driver IC with typical 0.22 A source and 0.48 A sink currents in 14-Lead SOIC package with level-shift technology for IGBTs and MOSFETs. The IRS2890DS integrates over current protection and fault reporting.;
| 型号： | IRS2890DS |
| 厂家： | 
Infineon |
| 描述： | EiceDRIVER™ 600 V half-bridge gate driver IC with typical 0.22 A source and 0.48 A sink currents in 14-Lead SOIC package with level-shift technology for IGBTs and MOSFETs. The IRS2890DS integrates over current protection and fault reporting. 驱动 双极性晶体管 |
| 文件： | 总26页 (文件大小：1584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRS2890DS
Half-Bridge Driver with Overcurrent Protection
Features
Product Summary
Floating channel designed for bootstrap operation
Fully operational to +600 V
VOFFSET
VOUT
≤ 600 V
10 V – 20 V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V, 5 V, and 15 V input logic compatible
Matched propagation delay for both channels
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs
Integrated bootstrap functionality
Suitable for both trapezoidal and sinusoidal motor
control
IO+ & IO- (typ.)
tON & tOFF (typ.)
Deadtime (typ.)
220 mA & 480 mA
500 ns & 500 ns
300 ns
Overcurrent protection and fault reporting
Advanced input filter
Integrated deadtime protection
Shoot-through (cross-conduction) protection
Adjustable fault clear timing
Description
Package Options
The IRS2890D is a high voltage, high speed power
MOSFET and IGBT half bridge gate driver. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is
compatible with standard CMOS or TTL outputs, down to
3.3 V logic. The output drivers feature a high-pulse
current buffer stage designed for minimum driver cross-
conduction.The floating channel can be used to drive N-
channel power MOSFETs or IGBTs in the high side
configuration which operates up to 600 V. Propagation
delays are matched to simplify the HVIC’s use in high
frequency applications.
14-Lead SOIC
Typical Applications
Motor Control
Air Conditioners/Washing Machines
Micro/Mini inverter drives
General Purpose Inverters
Standard Pack
Base Part Number
Package Type
Orderable Part Number
Form
Quantity
Tube/Bulk
55
IRS2890DSPBF
IRS2890DSPBF
14-Lead SOIC N
Tape and Reel
2500
IRS2890DSTRPBF
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IRS2890DS
Typical Connection Diagram
DC BUS +
Vcc
Hin
Lin
VB
HO
VS
IRS2890
RFE
LO
COM
ITRIP
DC BUS -
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please
refer to Application Notes & Design Tips for proper circuit board layout.
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Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VCC
VIN
Definition
Low side supply voltage
Min.
-0.3
Max.
25†
Units
Logic input voltage (LIN, HIN, RFE, ITRIP)
High-side floating well supply voltage
High-side floating well supply return voltage
Floating gate drive output voltage
Low-side output voltage
COM - 0.3
-0.3
VCC + 0.3
625
VB
VS
VB - 25
VS - 0.3
COM - 0.3
VCC - 25
—
VB + 0.3
VB + 0.3
VCC + 0.3
VCC + 0.3
50
V
VHO
VLO
COM
dVS/dt
PD
Power ground
Allowable VS offset supply transient relative to COM
Package power dissipation @ TA +25ºC
Thermal resistance, junction to ambient
Junction temperature
V/ns
W
—
1
RthJA
TJ
—
120
ºC/W
—
150
TS
Storage temperature
-55
150
ºC
TL
Lead temperature (soldering, 10 seconds)
—
300
†
All supplies are tested at 25V
.
Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are
absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with supplies
of (VCC - COM) = (VB - VS) = 15 V.
Symbol
VCC
VIN
Definition
Low-side supply voltage
Min
10
Max
20
Units
Logic input voltage
0
VCC
VB
High-side floating well supply voltage
High-side floating well supply offset voltage†
Transient High-side floating well supply offset
voltage
VS + 10
VS + 20
600
COM - 8†
- 50††
VS
V
VSt
600
VHO
VLO
TA
Floating gate drive output voltage
Low-side output voltage
Ambient temperature
VS
COM
-40
VB
VCC
125
ºC
†
Logic operation for VS of –8 V to 200 V. Logic state held for VS of –8 V to –VBS. Please refer to Design Tip
DT97-3 for more details.
††
Operational for transient negative VS of COM - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
the Application Information section of this datasheet for more details.
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Static Electrical Characteristics
(VCC - COM) = (VB - VS) = 15 V. TA = 25 °C unless otherwise specified. The VIN and IIN parameters are referenced
to COM. The VO and IO parameters are referenced to respective VS and COM and are applicable to the respective
output leads HO or LO. The VCCUV parameters are referenced to COM. The VBSUV parameters are referenced to VS.
Symbol
Definition
Min.
8.0
6.9
—
Typ. Max. Units Test Conditions
VBSUV
VBS supply under voltage positive threshold
8.9
7.7
1.2
8.9
7.7
1.2
0.65
0.13
—
9.8
8.5
—
+
VBSUV
VBS supply under voltage negative threshold
VBS supply under voltage hysteresis
VCC supply under voltage positive threshold
VCC supply under voltage negative threshold
VCC supply under voltage hysteresis
High level output voltage drop, VBIAS-VO
Low level output voltage drop, VO
Logic “1” input voltage
-
VBSUVHY
VCCUV
8.0
6.9
—
9.8
8.5
—
+
VCCUV
-
VCCUVHY
VOH
—
—
IO = 20 mA
V
VOL
—
—
VIH
2.2
—
—
VIL
Logic “0” input voltage
—
0.8
2.2
—
VRFE+
VRFE-
VITRIP+
VITRIP-
VITRIP HYS
ILK
RFE positive going threshold
—
1.9
1.1
RFE negative going threshold
0.8
ITRIP positive going threshold
ITRIP negative going threshold
ITRIP hysteresis
0.475 0.500 0.525
—
—
—
—
—
0.43
0.07
—
—
—
High-side floating well offset supply leakage
Quiescent VBS supply current
50
VB = VS = 600 V
VIN = 0 V or 4 V
IQBS
45
70
µA
IQCC
Quiescent VCC supply current
—
3000
VO = 0 V
PW ≤ 10 µs
VO = 15 V
IO+
Output high short circuit pulsed current
Output low short circuit pulsed current
—
—
220
480
—
—
mA
IO-
IRFE+
IRFE-
PW ≤ 10 µs
Input bias current (RFE)
—
1
0
0
1
—
10
1
Logic “1”
Input bias current (RFE)
Logic “0”
Input bias current (LIN, HIN)
IIN+
—
—
—
—
—
—
5
Logic “1”
VIN = 4 V
VIN = 0 V
VIN = 4 V
VIN = 0 V
µA
Input bias current (LIN, HIN)
IIN-
—
5
Logic “0”
Input bias current (ITRIP)
IITRIP+
IITRIP-
RBS
10
1
Logic “1”
Input bias current (ITRIP)
—
200
40
Logic “0”
Bootstrap resistance
RFE mos resistance
—
100
Ω
Ω
RON, RFE
Io = 1.5mA
Please refer to Application Section for integrated bootstrap description.
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Dynamic Electrical Characteristics
VCC = VB = 15 V, VS = COM, TA = 25 oC, and CL = 1000 pF unless otherwise specified.
Symbol
Definition
Min.
350
350
—
Typ.
500
500
85
Max. Units
Test Conditions
tON
tOFF
tR
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
650
650
—
VS =0 V or 600 V
—
tF
Turn-off fall time
30
—
VS = 0 V
Dead time, LO turn-off to HO turn-on & HO
turn-off to LO turn-on
ns
DT
MT
200
300
—
430
50
—
Delay matching time (tON, tOFF
)
Enable low to output shutdown propagation
delay
Enable input filter time
FAULT clear time
(R = 2 MΩ, C = 1 nF)
tEN
270
100
1.35
400
200
1.75
530
300
2.1
TFIL,EN
TFLTCLR
ms
ns
VDD = 3.3 V
TITRIP
TBL
ITRIP to output shutdown propagation delay
ITRIP blanking time
500
300
450
720
500
680
950
700
900
TFLT
ITRIP to FAULT propagation delay
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Functional Block Diagram
VB
HO
VS
S
R
Input
Noise
filter
VSS/COM
Level
Shifter
Latch
&
UV Detect
HV Level
Shifter
HIN
Driver
Deadtime &
Shoot-Through
Prevention
Input
Noise
filter
LIN
Integrated
BootFet
COM
UV
Detect
VCC
ITRIP
RFE
ITRIP
Noise
filter
VSS/COM
Level
Shifter
Delay
LO
Driver
COM
Noise
filter
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Lead Definitions
Pin
Symbol Description
1
2
3
VCC
HIN
LIN
Low side and logic fixed supply
Logic input for high side gate driver output (HO), in phase
Logic input for low side gate driver output (LO), in phase
Analog input for over-current shutdown. When active, ITRIP shuts down outputs and
activates RFE low. When ITRIP becomes inactive, RFE stays active low for an externally set
time tFLTCLR, then automatically becomes inactive (open-drain high impedance).
No connection
4
ITRIP
5
6
NC
COM
Low side return
Integrated fault reporting function like over-current (ITRIP), or low-side undervoltage lockout
and the fault clear timer. This pin has negative logic and an open-drain output. The use of
over-current protection requires the use of external components.
7
RFE
8
NC
LO
NC
NC
VS
No connection
9
Low side gate drive output
No connection
10
11
12
13
14
No connection
High side floating supply return
High side gate drive output
High side floating supply
HO
VB
Lead Assignments
VB
HO
VS
VCC
HIN
LIN
1
2
3
4
5
6
7
14
13
12
11
10
ITRIP
NC
NC
NC
LO
COM
RFE
9
NC
8
14-Lead SOIC N
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Application Information and Additional Details
Information regarding the following topics are included as subsections within this section of the datasheet.
IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Input Logic Compatibility
Undervoltage Lockout Protection
Shoot-Through Protection
Enable Input
Fault Reporting and Programmable Fault Clear Timer
Over-Current Protection
Truth Table: Undervoltage lockout, ITRIP, and ENABLE
Daisy Chain Multiple Devices
Advanced Input Filter
Short-Pulse / Noise Rejection
Integrated Bootstrap Functionality
Negative VS Transient SOA
PCB Layout Tips
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS2890D HVICs are designed to drive MOSFET or IGBT power devices. Figures 1 and 2 illustrate several
parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive
the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is
defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes
generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage.
VB
VB
(or VCC
)
(or VCC)
IO+
HO
HO
(or LO)
(or LO)
+
IO-
VHO (or VLO)
-
VS
VS
(or COM)
(or COM)
Figure 1: HVIC sourcing current
Figure 2: HVIC sinking current
Switching and Timing Relationships
The relationships between the input and output signals of the IRS2890D are illustrated below in Figures 3. From
these figures, we can see the definitions of several timing parameters (i.e., PWIN, PWOUT, tON, tOFF, tR, and tF)
associated with this device.
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PWIN
50%
50%
LIN, HIN
LO, HO
ton
toff
tr
tf
PWOUT
90%
90%
10%
10%
Figure 3: Switching time waveforms
The following two figures illustrate the timing relationships of some of the functionality of the IRS2890D; this
functionality is described in further detail later in this document.
During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches
at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the
high- and low-side output are held in the off state.
Interval B of Figures 4 and 5 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a
result, all of the gate drive outputs have been disabled (i.e., see that HO has returned to the low state; LO is also
held low), and a fault condition is reported on the RFE pin, which goes 0V. Once the ITRIP input has returned to the
low state, the output will remain disabled and the fault condition reported until the voltage on the RFE pin charges
up to VRFE+ threshold (see interval C in Figure 4); the charging characteristics are dictated by the RC network
attached to the RFE pin.
During interval E of Figure 4 and 6, we can see that the RFE pin has been pulled low (as is the case when the
driver IC has received a command from the control IC to shutdown); these results in the outputs (HO and LO) being
held in the low state until the RFE pin is pulled high.
B
C
D
E
A
HIN
LIN
ITRIP
RFE
HO
LO
Figure 4: Input/output timing diagram
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VIT,TH+
VIT,TH-
ITRIP
RFE
VRFE+
50%
tFLT
tFLTCLR
tTRIP
90%
HO, LO
Figure 5: Detailed view of B interval
RFE
VRFE-
tEN
90%
LO, HO
Figure 6: Detailed view of E interval
Deadtime
This HVIC features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a
time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to
ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This
minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external
deadtimes larger than DT are not modified by the gate driver.
Matched Propagation Delays
The IRS2890D HVIC is designed with propagation delay matching circuitry. With this feature, the IC’s response at
the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side
channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT).
The propagation turn-on delay (tON) of the IRS2890D is matched to the propagation turn-on delay (tOFF).
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50%
50%
HIN
LIN
LO
HO
10%
MT
MT
HO
90%
LO
Figure 7: Delay Matching Waveform Definition
Input Logic Compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2890D has been designed to
be compatible with 3.3 V and 5 V logic-level signals. Figure 8 illustrates an input signal to the IRS2890D, its input
threshold values, and the logic state of the IC as a result of the input signal.
Figure 8: HIN & LIN input thresholds
Undervoltage Lockout Protection
This HVIC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and
the VBS (high-side circuitry) power supply. Figure 9 is used to illustrate this concept; VCC (or VBS) is plotted over
time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled
or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the
VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize
a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the
low state to inform the controller of the fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the
VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize
a fault condition, and shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be
driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this
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IRS2890DS
could result in very high conduction losses within the power device and could lead to power device failure.
VCC
(or VBS
)
VCCUV+
(or VBSUV+
)
VCCUV-
(or VBSUV-
)
Time
UVLO Protection
(Gate Drive Outputs Disabled)
Normal
Normal
Operation
Operation
Figure 9: UVLO protection
Shoot-Through Protection
The IRS2890D is equipped with shoot-through protection circuitry (also known as cross-conduction prevention
circuitry). Figure 10 shows how this protection circuitry prevents both the high- and low-side switches from
conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth
table.
Shoot-through
protection enabled
HIN
LIN
HO
LO
Figure 10: Illustration of shoot-through protection circuitry
IRS2890D
HIN
0
LIN
0
HO
0
LO
0
0
1
1
0
1
0
0
1
1
1
0
0
Table 1: Input/output truth table for IRS2890D
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Enable Input
The IRS2890D provides an enable functionality that allows it to shutdown or enable the HVIC. When the RFE pin
is in the high state the HVIC is able to operate normally (assuming no other under voltage fault conditions on Vcc).
When the RFE pin is in a low state, the gate drive outputs are pulled low until the enable condition is restored. The
enable circuitry of the IRS2890D features an input filter; the minimum input duration is specified by tFIL,EN. Please
refer to the RFE pin parameters VRFE+, VRFE-, and IRFE for the details of its use. Table 2 gives a summary of this
pin’s functionality.
Enable Input
Enable input high
Enable input low
Outputs enabled*
Outputs disabled
Table 2: Enable functionality truth table
(*assumes no undervoltage fault on Vcc)
Fault Reporting and Programmable Fault Clear Timer
The IRS2890D provides an integrated fault reporting output and an adjustable fault clear timer. There are two
situations that would cause the HVIC to report a fault via the RFE pin. The first is an undervoltage condition of VCC
and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the RFE pin is internally
pulled to COM and the fault clear timer is activated. The RFE output stays in the low state until the fault condition
has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the RFE pin
will return to its external pull-up voltage.
The length of the fault clear time period (tFLTCLR) is determined by exponential charging characteristics of the
capacitor where the time constant is set by RRFE and CRFE. Figure 11 shows that RRFE is connected between the
external supply (VDD) and the RFE pin, while CRFE is placed between the RFE and COM pins.
VCC
HIN U
LIN U
HIN
LIN
HIN V
LIN V
HIN W
LIN W
VDD
uC
HO
VS
GK
RRFE
RFE
LO
CRFE
COM
ITRIP
R
DC - BUS
Figure 11 Programming the fault clear timer
The design guidelines for this network are shown in Table 3.
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≤1 nF
Ceramic
CRFE
0.5 MΩ to 2 MΩ
>> RON,RCIN
RRFE
Table 3: Design guidelines
The length of the fault clear time period can be determined by using the formula below.
vC(t) = Vf*(1-e-t/RC
)
tFLTCLR = -(RRFE*CRFE)*ln(1-VRFE+/VDD ) + 100ns
The voltage on the RFE pin should not exceed the VDD of the uC power supply.
Over-Current Protection
The IRS2890D HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current
events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are
shutdown, and RFE is pulled to COM.
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0,
R1, and R2) connected to ITRIP as shown in Figure 12, and the ITRIP threshold (VITRIP+). The circuit designer will
need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the
voltage at node VX reaches the over-current threshold (VITRIP+) at that current level.
VITRIP+ = R0*IDC-(R1/(R1+R2))
DC BUS +
Vcc
VB
Hin
Lin
HO
RFE
ITRIP
VS
To load
LO
COM
R2
R1
DC BUS -
Vx
R0
IDC-
Figure 12 Programming the over-current protection
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to
exceed 5 V; if necessary, an external voltage clamp may be used.
Truth Table: Undervoltage lockout, ITRIP, and ENABLE
Table 4 provides the truth table for the IRS2890D. The first line shows that the UVLO for VCC has been tripped; the
RFE output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and
when VCC is greater than VCCUV, the FAULT output returns the driver is functional.
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The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have
been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new rising
transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP
trip threshold has been reached and that the gate drive outputs have been disabled. This condition is stored in the
external RC network waiting for fault clear time. The last case shows when the HVIC has received an enable
command through the RFE input to shutdown; as a result, the gate drive outputs have been disabled.
VCC
VBS
ITRIP
—
RFE
0
LO
0
HO
0
<
UVLO VCC
UVLO VBS
—
VCCUV
15 V
15 V
15 V
15 V
<
0 V
HIGH
HIGH
0
LIN
LIN
0
0
VBSUV
15 V
15 V
15 V
Normal operation
ITRIP fault
0 V
HIN
0
>VITRIP+
0 V
Enable command
0
0
0
Table 4: IRS2890D UVLO, ITRIP, FLT/EN/RCIN
Daisy Chain Multiple Devices
The IRS2890D can be daisy chained together for applications which require more than one device, such as in the
three phase circuit shown below. In Figure 13, the three IRS2890D RFE pins are connected together. The ITRIP
sensing is only used on the first HVIC; the other two ITRIP pins are disabled by tying them to COM. The
programmable fault clear timing components, RRFE and CRFE, are populated only once for the RFE pin. When a
fault occurs, either from ITRIP or UVLO, or an external command, all three HVICs are disabled simultaneously via
the daisy chained RFE pin being pulled low to COM.
DC + BUS
VCC
VCC
VCC
HIN U
LIN U
HIN
LIN
HIN V
LIN V
HIN W
LIN W
VDD
HIN
LIN
uC
HIN
LIN
HO
VS
HO
VS
HO
VS
V
W
To
GK
RRFE
Load
U
RFE
RFE
RFE
LO
LO
LO
CRFE
COM
ITRIP
COM
ITRIP
COM
ITRIP
RSH
DC - BUS
Figure 13: Daisy Chain Circuit with Single Shunt
In Figure 14 we want to be able to measure two of the individual leg currents. The RFE pins are connected together
with the components for the pin only populated for the first HVIC. Two of the ITRIP pins are used, one for each leg,
with the third ITRIP tied to COM. A fault can occur by the ITRIP sensing network for either of the two legs, shutting
down all three IRS2890D HVICs simultaneously.
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DC + BUS
VCC
VCC
VCC
HIN U
LIN U
HIN
LIN
HIN V
LIN V
HIN W
LIN W
VDD
HIN
LIN
uC
HIN
LIN
HO
VS
HO
VS
HO
VS
V
W
To
Load
GK
RRFE
U
RFE
RFE
RFE
LO
LO
LO
CRFE
COM
ITRIP
COM
ITRIP
COM
ITRIP
RSH
RSH
DC - BUS
Figure 14: Daisy Chain circuit with Multiple Shunt
Advanced Input Filter
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject
noise spikes and short pulses. This input filter has been applied to the HIN ans LIN inputs. The working principle
of the new filter is shown in Figures 15 and 16.
Figure 15 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms
(Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting output is approximately the
difference between the input signal and tFIL,IN. The lower pair of waveforms (Example 2) show an input signal with
a duration slightly longer then tFIL,IN; the resulting output is approximately the difference between the input signal
and tFIL,IN
.
Figure 16 shows the advanced input filter of the IRS2890D and the symmetry between the input and output. The
upper pair of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the resulting
output is approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an
input signal with a duration slightly longer then tFIL,IN; the resulting output is approximately the same duration as the
input signal.
IN
IN
tFIL,IN
tFIL,IN
OUT
OUT
IN
IN
tFIL,IN
tFIL,IN
OUT
OUT
Figure 15: Typical input filter
Figure 16: Advanced input filter
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Short-Pulse / Noise Rejection
This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of
the input signal is less than tFIL,IN, the output will not change states. Example 1 of Figure 17 shows the input and
output in the low state with positive noise spikes of durations less than tFIL,IN; the output does not change states.
Example 2 of Figure 17 shows the input and output in the high state with negative noise spikes of durations less
than tFIL,IN; the output does not change states.
IN
tFIL,IN
OUT
IN
tFIL,IN
OUT
Figure 17: Noise rejecting input filters
Figures 18 and 19 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF
pulses.
The input filter characteristic is shown in Figure 18; the left side illustrates the narrow pulse ON (short positive
pulse) characteristic while the right shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of
Figure 18 shows the duration of PWIN, while the y-axis shows the resulting PWOUT duration. It can be seen that for
a PWIN duration less than tFIL,IN, that the resulting PWOUT duration is zero (e.g., the filter rejects the input
signal/noise). We also see that once the PWIN duration exceed tFIL,IN, that the PWOUT durations mimic the PWIN
durations very well over this interval with the symmetry improving as the duration increases. To ensure proper
operation of the HVIC, it is suggested that the input pulse width for the high-side inputs be ≥ 500 ns.
The difference between the PWOUT and PWIN signals of both the narrow ON and narrow OFF cases is shown in
Figure 19; the careful reader will note the scale of the y-axis. The x-axis of Figure 19 shows the duration of PWIN,
while the y-axis shows the resulting PWOUT–PWIN duration. This data illustrates the performance and near
symmetry of this input filter.
Narrow Pulse OFF
Narrow Pulse ON
1000
800
600
400
200
0
1000
800
600
400
200
0
PWOUT
PWIN
PWOUT
PWIN
0
200
400
Time (ns)
600
800
1000
0
200
400
600
800
1000
Time (ns)
Figure 18: Input filter characteristic
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Narrow Pulse OFF
Narrow Pulse ON
120
100
80
60
40
20
0
120
100
80
60
40
20
0
PWOUT-PWIN
PWOUT-PWIN
Short
Pulse
Filtered
Short
Pulse
Filtered
0
200
400
600
800
1000
0
200
400
600
Time (ns)
800
1000
Time (ns)
Figure 19: Difference between the input pulse and the output pulse
Integrated Bootstrap Functionality
The IRS2890D embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a
wide range of applications.
A bootstrap FET is connected between the floating supply VB and VCC (see Fig. 20).
BootFet
Vcc
Vb
Figure 20: Simplified BootFET connection
The bootstrap FET is suitable for most PWM modulation schemes, including trapezoidal control, and can be used
either in parallel with the external bootstrap network (diode+ resistor) or as a replacement of it. The use of the
integrated bootstrap as a replacement of the external bootstrap network may have some limitations at very high
PWM duty cycle due to bootstrap FET equivalent resistance (RBS, see page 3).
The integrated bootstrap FET is turned on during the time when LO is ‘high’, and it has a limited source current due
to RBS. The VBS voltage will be charged each cycle depending on the on-time of LO and the value of the CBS
capacitor, the drain-source (collector-emitter) drop of the external IGBT (or MOSFET), and the low-side free-
wheeling diode drop.
The bootstrap FET follows the state of low-side output stage (i.e., the bootstrap FET is ON when LO is high, unless
the VB voltage is higher than approximately VCC. In that case, the bootstrap FET is designed to remain off until VB
returns below that threshold; this concept is illustrated in Figure 21.
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Figure 21: BootFET timing diagram
Tolerant to Negative VS Transients
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical three phase
inverter circuit is shown in Figure 22; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 23 and 24) switches off, while the U phase current is flowing to
an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the
low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive DC
bus voltage to the negative DC bus voltage.
DC+ BUS
D3
D1
D5
Q1
Q3
Q5
W
VS3
V
To
Input
Voltage
VS2
U
Load
VS1
D4
D2
D6
Q4
Q2
Q6
DC- BUS
Figure 22: Three phase inverter
DC+ BUS
DC+ BUS
D1
Q1
ON
Q1
OFF
IU
VS1
VS1
IU
D2
D2
Q2
Q2
OFF
OFF
DC- BUS
DC- BUS
Figure 23: Q1 conducting
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IRS2890DS
Also when the V phase current flows from the inductive load back to the inverter (see Figures 25 and 26), and Q4
IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
DC+ BUS
DC+ BUS
D3
D3
Q3
OFF
Q3
OFF
IV
VS2
VS2
IV
D4
Q4
Q4
OFF
ON
DC- BUS
DC- BUS
Figure 25: D3 conducting
Figure 26: Q4 conducting
However, in a real inverter circuit the VS voltage swing does not stop at the level of the negative DC bus but instead
swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 27 depicts one leg of the three phase inverter; Figures 28 and 29 show a simplified
illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit
from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the high-side switch
is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic
elements of the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-
side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these figures). This
current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage
between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin).
DC+ BUS
DC+ BUS
DC+ BUS
LC1
+
VLC1
-
D1
D1
Q1
Q2
Q1
ON
Q1
OFF
+
IU
LE1
LC2
VLE1
-
VS1
VS1
VS1
-
IU
VLC2
+
D2
D2
-
Q2
OFF
Q2
OFF
VD2
+
-
LE2
DC- BUS
VLE2
+
DC- BUS
DC- BUS
Figure 27: Parasitic Elements
Figure 28: VS positive
Figure 29: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is
greater than in normal operation.
Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
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indication of the IRS2890D’s robustness can be seen in Figure 30, where the IRS2890D Safe Operating Area is
shown at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area
(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage
to the IC do not appear if negative Vs transients fall inside the SOA.
time [ns]
0
100
200
300
400
500
600
700
800
900
1000
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Figure 30: Negative VS transient SOA for IRS2890D @ VBS=15 V
Even though the IRS2890D has been shown to be able to handle these large negative VS transient conditions, it is
highly recommended that the circuit designer always limit the negative VS transients as much as possible by
careful PCB layout and component use.
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components
tied to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please
see the Case Outline information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near
the high voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see
Figure 31). In order to reduce the EM coupling and improve the power switch turn on/off performance, the
gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate
drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate
loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility of a self
turn-on effect.
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IGC
VBX
(or VCC)
CGC
RG
HOX
(or LOX)
Gate Drive
Loop
VGE
VSX
(or COM)
Figure 31: Antenna Loops
Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A
ceramic 1 μF ceramic capacitor is suitable for most applications. This component should be placed as
close as possible to the pins in order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage
transients at the switch node; it is recommended to limit the phase voltage negative transients. In order to
avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector
distance, and 2) minimize the low-side emitter to negative bus rail stray inductance. However, where
negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes
placing a resistor (5 Ω or less) between the VS pin and the switch node (see Figure 32), and in some
cases using a clamping diode between COM and VS (see Figure 33). See DT04-4 at www.infineon.com
for more detailed information.
DC+ BUS
DC+ BUS
DBS
DBS
VCC
VB
VCC
VB
CBS
CBS
HO
VS
HO
VS
RVS
RVS
DVS
To
Load
To
Load
LO
LO
COM
VSS
COM
VSS
DC- BUS
DC- BUS
Figure 32: VS resistor
Additional Documentation
Figure 33: VS clamping diode
Several technical documents related to the use of HVICs are available at www.infineon.com; use the Site Search
function and the document number to quickly locate them. Below is a short list of some of these documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs
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Package Details: 14-Lead SOIC
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Tape and Reel Details: 14-Lead SOIC
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Part Marking Information
Part number
Date code
IRS2890DS
YWW ?
IR logo
Pin 1
Identifier
? XXXX
Lot Code
(Prod mode –
4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Non-Lead Free Released
Assembly site code
Per SCOP 200-002
14-Lead SOIC8
IRS2890DSPBF
Qualification Information
Industrial†
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level
is granted by extension of the higher Industrial level.
Qualification Level
MSL2††, 260C
(per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
14 Lead SOIC
Class 1C
Human Body Model
(per JEDEC standard JESD22-A114)
Class B
ESD
Machine Model
(per EIA/JEDEC standard EIA/JESD22-A115)
C3
(per JEDEC standard JS-002-2014)
Class II, Level A
(per JESD78)
Charged Device Model
IC Latch-Up Test
RoHS Compliant
Yes
†
Higher qualification ratings may be available should the user have such requirements. Please contact
your Infineon sales representative for further information.
††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
Infineon sales representative for further information.
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Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated
herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims
any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of
intellectual property rights of any third party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated
in this document and any applicable legal requirements, norms and standards concerning customer’s products
and any use of the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your
nearest Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications
where a failure of the product or any consequences of the use thereof can reasonably be expected to result in
personal injury.
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