IRU3004CW-TR [INFINEON]
Switching Controller, Voltage-mode, 500kHz Switching Freq-Max, PDSO20, PLASTIC, SOIC-20;
| 型号： | IRU3004CW-TR |
| 厂家： | 
Infineon |
| 描述： | Switching Controller, Voltage-mode, 500kHz Switching Freq-Max, PDSO20, PLASTIC, SOIC-20 控制器 |
| 文件： | 总17页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94140
IRU3004
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK
CONTROLLER IC WITH DUAL LDO CONTROLLER
FEATURES
DESCRIPTION
The IRU3004 controller IC is specifically designed to meet
Meets latest VRM 8.4 specification for PentiumIII
Provides single chip solution for Vcore, GTL+ and Intel specifications for Pentium IIIä microprocessor
clock supply applications as well as the next generation P6 family
On-Board DAC programs the output voltage from processors. The IC provides a single chip controller IC
1.3V to 3.5V. The IRU3004 remains on for VID code for the Vcore, GTL+ and clock supplies required for the
of (11111)
Pentium III applications. The IRU3004 features a pat-
Dual linear regulator controller on-board for 1.5V ented topology, that in combination with a few external
GTL+ and 2.5V clock supplies
Loss-less Short Circuit Protection
components as shown in the typical application circuit,
will provide in excess of 20A of output current for an on-
Synchronous operation allows maximum efficiency board DC-DC converter while automatically providing the
Patented architecture allows fixed frequency opera- right output voltage via the 5-bit internal DAC meeting
tion as well as 100% duty cycle during dynamic the latest VRM specification. The IRU3004 also features
load
loss-less current sensing by using the RDS(on) of the high
side power MOSFET as the sensing resistor and a Power
Good window comparator that switches its open collec-
Minimum Part Count, No External Compensation
Soft-Start Function
High current totem pole driver for direct driving of the tor output low when the output is outside of a ±10%
external power MOSFET
Power Good Function
window. Other features of the device are: under-voltage
lockout for both 5V and 12V supplies, an external pro-
grammable soft-start function as well as programming
the oscillator frequency by using an external capacitor.
APPLICATIONS
Pentium III & next generation processor DC to DC
converter application
Low Cost Pentium with AGP
TYPICAL APPLICATION
Note:Pentium III is trademark of Intel Corp.
L2
Q1
5V
L1
VOUT3
R16
R17
C16
C5
R1
C7
R4
Q2
C13
C3
C10
R2
R3
R12
R13
3.3V
C4
C6
Q3
VOUT1
12V
C11
R18
R7
R8
V12
Ct
V5
D3
CS+
HDrv
CS-
LDrv
Gnd
VFB3
R11
C9
Lin1
C15
C1
IRU3004
SS
D4
VFB1
Q4
C2
VOUT2
D2
D1
D0
VFB2
PGd
Lin2
3.3V
C12
R14
R15
VID4
VID3
VID2
VID1
VID0
R5
C8
R9
Power Good
C14
Figure 1 - Typical application of the IRU3004.
PACKAGE ORDER INFORMATION
TA (8C)
DEVICE
PACKAGE
0 To 70
0 To 70
IRU3004CW
IRU3004CF
20-Pin Plastic SOIC (W)
20-Pin Plastic TSSOP (F)
Rev. 1.7
07/16/02
www.irf.com
1
IRU3004
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 10V
V12 Supply Voltage .................................................. 20V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
PACKAGE INFORMATION
20-PIN WIDE BODY PLASTIC SOIC (W)
20-PIN PLASTIC TSSOP (F)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
20
Ct
Lin1
VFB1
VFB2
V5
1
2
20 Lin2
Ct
Lin1
VFB1
Lin2
19 D 0
18
19
18
D 0
D 1
3
D 1
V
17 D 2
16 D 3
4
17 D 2
16
FB2
V5
5
D 3
15 D 4
14
15
D 4
PGd
CS-
6
PGd
CS-
7
14 VFB3
13 SS
VFB3
13 SS
CS+
HDrv
Gnd
8
CS+
HDrv
9
12
11
12
V12
V12
10
Gnd 10
11 LDrv
LDrv
θJA =858C/W
θJA =908C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer
to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
VID Section
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
0.98Vs
Vs
1.02Vs
0.1
0.5
V
%
%
V
0.4
VID Input HI
2
V
VID Input Internal Pull-Up
Resistor to V5
27
KΩ
Power Good Section
Under-Voltage lower trip point
Under-Voltage upper trip point
UV Hysteresis
Over-Voltage upper trip point
Over-Voltage lower trip point
OV Hysteresis
Power Good Output LO
Power Good Output HI
Soft-Start Section
VOUT Ramping Down
VOUT Ramping Up
0.89Vs 0.90Vs 0.91Vs
V
V
V
V
V
V
V
V
0.92Vs
0.015Vs 0.02Vs 0.025Vs
1.09Vs 1.10Vs 1.11Vs
VOUT Ramping Up
VOUT Ramping Down
1.08Vs
0.015Vs 0.02Vs 0.025Vs
RL=3mA
RL=5K Pull-Up to 5V
0.4
4.8
Soft-Start Current
CS+=0V, CS-=5V
10
µA
Rev. 1.7
07/16/02
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2
IRU3004
PARAMETER
SYM
TEST CONDITION
Supply Ramping Up
Supply Ramping Up
MIN
TYP
MAX
UNITS
UVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Error Comparator Section
Input Bias Current
9.2
0.3
4.1
0.2
10
10.8
0.5
4.5
0.4
V
V
V
V
0.4
4.3
0.3
2
+2
µA
mV
ns
Input Offset Voltage
Delay to Output
-2
VDIFF=10mV
100
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
Supply Current
160
-5
200
240
+5
2
µA
mV
%
Css=0.1µF
Operating Supply Current
CL=3000pF:
V5
20
14
mA
V12
Output Drivers Section
Rise Time
Fall Time
CL=3000pF
CL=3000pF
CL=3000pF
70
70
100
130
300
ns
ns
ns
Dead Band Time
Oscillator Section
Osc Frequency
Osc Valley
100
160
200
Ct=150pF
220
V5
260
0.2
KHz
V
V
Osc Peak
LDO Controller Section
VFB1 & VFB2
Input Bias Current
Lin1 or Lin2 Drive Current
1.455
1.500
50
1.545
2
V
µA
mA
Note 1: Vs refers to the set point voltage given in Table 1.
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes.
Rev. 1.7
07/16/02
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IRU3004
PIN DESCRIPTIONS
PIN# PIN SYMBOL
PIN DESCRIPTION
1
2
Ct
This pin programs the oscillator frequency in the range of 50KHz to 500KHz with an
external capacitor connected from this pin to the ground.
This pin controls the gate of an external transistor for either the GTL+ linear regulator or
Clock supply.
Lin1
3
4
5
6
VFB1
VFB2
V5
This pin provides the feedback for the linear regulator that its output drive is Lin1 pin.
This pin provides the feedback for the linear regulator that its output drive is Lin2 pin.
5V supply voltage.
This pin is an open collector output that switches LO when the output of the converter is
not within ±10% (typical) of the nominal output voltage. When Power Good pin switches
LO the sat voltage is less than 0.4V at 3mA.
PGd
7
8
CS-
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the CS threshold depending on the RDS of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
CS+
9
10
HDrv
Gnd
Output driver for the high-side power MOSFET.
This pin serves as the ground pin and must be connected directly to the ground plane. A
high frequency capacitor (0.1 to 1µF) must be connected from V5 and V12 pins to this
pin for noise free operation.
11
12
LDrv
V12
Output driver for the synchronous power MOSFET.
This pin is connected to the 12 V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (0.1 to 1µF) must be connected directly from this pin
to ground pin in order to supply the peak current to the power MOSFET duringthe transi-
tions.
13
SS
This pin provides the soft-start for the switching regulator. An internal current source
charges an external capacitor that is connected from this pin to the ground which ramps
up the outputs of the switching regulator, preventing the outputs from overshooting as
well as limiting the input current. The second function of the Soft-Start cap is to provide
long off time (HICCUP) for the synchronous MOSFET during current limiting.
This pin is connected directly to the output of the Core supply to provide feedback to the
Error comparator.
This pin selects a range of output voltages for the DAC. When in the LOW state the
range is 1.3V to 2.05V. For VID codes of all "1" the IRU3004 keeps all the outputs on.
MSB input to the DAC that programs the output voltage. This pin can be pulled-up exter-
nally by a 10K resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage. This pin can be pulled up externally
by a 10K resistor to either 3.3V or 5V supply.
Input to the DAC that programs the output voltage. This pin can be pulled up externally
by a 10KΩ resistor to either 3.3V or 5V supply.
LSB input to the DAC that programs the output voltage. This pin can be pulled-up exter-
nally by a 10K resistor to either 3.3V or 5V supply.
This pin controls the gate of an external transistor for either the GTL+ linear regulator or
Clock supply.
14
15
16
17
18
19
20
VFB3
D4
D3
D2
D1
D0
Lin2
Rev. 1.7
07/16/02
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4
IRU3004
BLOCK DIAGRAM
14
VFB3
Enable
V12
V12
Vset
Enable
9
HDrv
12
V12
UVLO
PWM
Control
5
V5
+
Vset
11
Slope
Comp
LDrv
19
18
17
16
15
Enable
D0
D1
D2
D3
D4
Osc
5Bit
DAC,
Ctrl
7
8
CS-
Over
Current
Soft
Start &
Fault
CS+
Logic
200uA
Logic
Enable
1
Ct
4
VFB2
13
SS
20
1.1Vset
Lin2
6
PGd
Gnd
1.5V
2
10
Lin1
0.9Vset
VFB1 3
Figure 2 - Simplified block diagram of the IRU3004.
Rev. 1.7
07/16/02
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5
IRU3004
TYPICAL APPLICATION
Pentium III
L2
L1
Q1
VOUT3
5V
R16
R17
C16
C 5
R 1
C 7
Q2
C13
C 3
C 4
C10
R 4
R 2
R 3
R12
R13
3.3V
12V
C 6
Q3
VOUT1
C11
R18
R 7
R 8
V12
Ct
V5
CS+
HDrv
CS-
LDrv
Gnd
V FB3
Lin1
R11
C15
C 1
IRU3004
SS
D 4
VFB1
Q4
C 2
VOUT2
D 3
D 2
D 1
D 0
V
PGd
Lin2
3.3V
FB2
C 9
C12
VID4
VID3
VID2
VID1
VID0
R14
R15
R 5
R 9
C14
C 8
Power Good
Figure 3 - Typical application of IRU3004 in an on-board DC-DC converter providing the Core, GTL+,
and Clock supplies for the Pentium II microprocessor.
Rev. 1.7
07/16/02
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6
IRU3004
IRU3004 APPLICATION PARTS LIST
Ref Desig Description
Qty
1
1
1
1
1
1
1
2
2
1
1
3
1
1
6
1
1
1
1
1
3
2
2
1
3
1
1
1
1
Part #
IRL3103S, TO-263 package
IRL3103D1S, TO-263 package
MPS2222A, SOT-23 package
IRLR024, TO-252 package
L=1µH, 5052 core with 4 turns of 1.0mm wire
L=2.7µH, 5052B core with 7 turns of 1.2mm wire
150pF, 0603
Manuf
IR
Q1
Q2
Q3
Q4
L1
MOSFET
MOSFET
IR
Bipolar Trans, GP
MOSFET
Motorola
IR
Inductor
MicroMetal
Micro Metal
L2
Inductor
C1
C2, 6
C3
C4
C5
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Electrolytic
Capacitor, Ceramic
Capacitor, Ceramic
1µF, 0603
10MV1200GX, 1200µF,10V
1µF, 0805
Sanyo
220pF, 0603
C7, 14, 15 Capacitor, Ceramic
1000pF, 0603
C8
Capacitor, Ceramic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Ceramic
Resistor
0.1µF, 0603
C9
6MV1000GX, 1000µF, 6.3V
6MV1500GX, 1500µF, 6.3V
6MV150GX, 150µF, 6.3V
6MV1000GX, 1000µF, 6.3V
10MV470GX, 470µF, 10V
4.7µF, 1206
Sanyo
Sanyo
Sanyo
Sanyo
Sanyo
C10
C11
C12
C13
C16
R1
3.3KΩ, 5%, 0603
R2, 3, 4
R5, 15
R7, 12
R8
Resistor
4.7Ω, 5%, 1206
Resistor
10KΩ, 5%, 0603
Resistor
100Ω, 1%, 0603
Resistor
150Ω, 1%, 0603
R9, 11, 14 Resistor
100Ω, 5%, 0603
R13
R16
R17
R18
Resistor
Resistor
Resistor
Resistor
22KΩ, 1%, 0603
220Ω, 1%, 0603
330Ω, 1%, 0603
10Ω, 5%, 0603
Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient
voltage.
Note 2: R14 and R15 set the 1.5V approximately 1% higher to account for the trace resistance drop.
Rev. 1.7
07/16/02
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7
IRU3004
TYPICAL APPLICATION
Pentium with AGP
L2
L1
Q1
V
OUT3
5V
R16
R17
C16
C5
R1
C7
R4
Q2
C13
C3
C4
C10
R2
R3
R12
R13
3.3V
12V
Q3
C6
C9
C11
R18
R7
R8
V12
Ct
V5
D3
CS+
HDrv
CS-
LDrv
Gnd
VFB3
R11
Lin1
C15
C1
IRU3004
VFB1
SS
D4
C2
Q4
D2
D1
D0
V
FB2
PGd
Lin2
3.3V
3.3V
C12
VID4
R14
R15
VID3
VID2
VID1
VID0
R5
C8
R9
C14
Power Good
Figure 4 - Typical application of IRU3004 in a Pentium with AGP where the power dissipation of the 3.3V
linear regulator is equally distributed between Q3 and Q4 pass transistors. This equal distribution is
possible by accurately regulating the first regulator using the IRU3004 linear controller and its internal
1% reference voltage while the second controller regulates the output of the first regulator from 4.17V to
3.3V, thereby distributing the power dissipation equally.
Rev. 1.7
07/16/02
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8
IRU3004
IRU3004 APPLICATION PARTS LIST
Ref Desig Description
Qty
Part #
Manuf
Q1
MOSFET
MOSFET
MOSFET
Inductor
1
IRL3103s, TO-263 package
IR
Q2
1
2
1
IRL3103D1S, TO-263 package
IRL3303S, TO-263 package
L=1µH, 5052 core with 4 turns of
1.0mm wire
IR
IR
Q3, 4
L1
Micro Metal
L2
Inductor
1
L=2.7µH, 5052B core with 7 turns of
1.2mm wire
Micro Metal
Sanyo
C1
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Electrolytic
Capacitor, Ceramic
Capacitor, Ceramic
1
2
2
1
1
3
1
1
6
1
1
1
1
1
3
2
1
2
3
1
1
1
1
1
150pF, 0603
C2, 6
C3
1µF, 0603
10MV1200GX, 1200µF, 10V
1µF, 0805
C4
C5
220pF, 0603
C7, 14, 15 Capacitor, Ceramic
1000pF, 0603
C8
Capacitor, Ceramic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Ceramic
Resistor
0.1µF, 0603
C9
6MV1000GX, 1000µF, 6.3V
6MV1500GX, 1500µF, 6.3V
6MV150GX, 150µF, 6.3V
6MV1000GX, 1000µF, 6.3V
10MV470GX, 470µF, 10V
4.7µF, 1206
Sanyo
Sanyo
Sanyo
Sanyo
Sanyo
C10
C11
C12
C13
C16
R1
3.3KΩ, 5%, 0603
R2, 3, 4
R5, 15
R7
Resistor
4.7Ω, 5%, 1206
Resistor
10KΩ, 5%, 0603
Resistor
267Ω, 1%, 0603
R8
Resistor
150Ω, 1%, 0603
R9, 11, 14 Resistor
100Ω, 5%, 0603
R12
R13
R16
R17
R18
Resistor
Resistor
Resistor
Resistor
Resistor
100Ω, 1%, 0603
22KΩ, 1%, 0603
220Ω, 1%, 0603
330Ω, 1%, 0603
10Ω, 5%, 0603
Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient
voltage.
Rev. 1.7
07/16/02
www.irf.com
9
IRU3004
APPLICATION INFORMATION
An example of how to calculate the components for the output capacitor ESR at the cost of load regulation. One
application circuit is given below.
can show that the new ESR requirement eases up by
half the total trace resistance. For example, if the ESR
Assuming, two sets of output conditions that this regu- requirement of the output capacitors without voltage level
lator must meet:
a) Vo=2.8V, Io=14.2A, ∆Vo=185mV, ∆Io=14.2A
b) Vo=2V, Io=14.2A, ∆Vo=140mV, ∆Io=14.2A
shifting must be 7mΩ, then after level shifting the new
ESR will only need to be 9.5mΩ if the trace resistance
is 5mΩ (7 + 5/2=9.5). However, one must be careful that
the combined “voltage level shifting” and the transient
The regulator design will be done such that it meets the response is still within the maximum tolerance of the
worst case requirement of each condition.
Intel specification. To insure this, the maximum trace
resistance must be less than:
Output Capacitor Selection
(Vspec - 0.02 × Vo - ∆Vo)
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total ∆Vo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as:
Rs ≤ 2 ×
∆I
Where:
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage specification
Vo = Output voltage
∆Vo = Output ripple voltage
∆I = load current step
100
14.2
ESR ≤
= 7mΩ
For example, assuming:
Vspec = ±140mV = ±0.1V for 2V output
Vo = 2V
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typical.
Selecting 6 of these capacitors in parallel has an ESR
of » 6mΩ which achieves our low ESR goal.
∆Vo = assume 10mV = 0.01V
∆I = 14.2A
Then the Rs is calculated to be:
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic FA series or the
Nichicon PL series.
(0.140 - 0.02 × 2 - 0.01)
Rs ≤ 2 ×
= 12.6mΩ
14.2
Reducing the Output Capacitors Using Voltage Level However, if a resistor of this value is used, the maximum
Shifting Technique power dissipated in the trace (or if an external resistor is
The trace resistance or an external resistor from the output being used) must also be considered. For example if
of the switching regulator to the Slot 1 can be used to Rs=12.6mΩ, the power dissipated is:
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
Io2×Rs = 14.22×12.6 = 2.54W
when transition from light load to full load and vice versa. This is a lot of power to be dissipated in a system. So, if
To accomplish this, the output of the regulator is typi- the Rs=5mΩ, then the power dissipated is about 1W
cally set about half the DC drop that results from light which is much more acceptable. If level shifting is not
load to full load. For example, if the total resistance from implemented, then the maximum output capacitor ESR
the output capacitors to the Slot 1 and back to the Gnd was shown previously to be 7mΩ which translated to » 6
pin of the device is 5mΩ and if the total ∆I, the change of the 1500µF, 6MV1500GX type Sanyo capacitors. With
from light load to full load is 14A, then the output voltage Rs=5mΩ, the maximum ESR becomes 9.5mΩ which is
measured at the top of the resistor divider which is also equivalent to » 4 caps. Another important consideration
connected to the output capacitors in this case, must is that if a trace is being used to implement the resistor,
be set at half of the 70mV or 35mV higher than the DAC the power dissipated by the trace increases the case
voltage setting. This intentional voltage level shifting temperature of the output capacitors which could seri-
during the load transient eases the requirement for the ously effect the life time of the output capacitors.
Rev. 1.7
07/16/02
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10
IRU3004
Output Inductor Selection
In our example for Vo=2.8V and 14.2A load, assuming
The output inductance must be selected such that un- IRL3103 MOSFET for both switches with maximum on-
der low line and the maximum output voltage condition, resistance of 19mΩ, we have:
the inductor current slope times the output capacitor
1
T =
= 5µs
ESR is ramping up faster than the capacitor voltage is
drooping during a load current step. However, if the in-
ductor is too small, the output ripple current and ripple
voltage become too large. One solution to bring the ripple
current down is to increase the switching frequency,
however that will be at the cost of reduced efficiency and
higher system cost. The following set of formulas are
derived to achieve the optimum performance without
many design iterations.
200000
Vsw = Vsync = 14.2 × 0.019 = 0.27V
2.8 + 0.27
5 - 0.27 + 0.27
TON = 0.61 × 5 = 3.1µs
D »
= 0.61
TOFF = 5 - 3.1 = 1.9µs
1.9
∆Ir = (2.8 + 0.27) ×
= 1.94A
3
∆Vo = 1.94 × 0.006 = 0.011V = 11mV
The maximum output inductance is calculated using the
following equation:
Power Component Selection
Assuming IRL3103 MOSFETs as power components,
we will calculate the maximum power dissipation as fol-
lows:
VIN(MIN) - Vo(MAX)
L = ESR×C×
(
)
2 × DI
Where:
VIN(MIN) = Minimum input voltage
Vo = 2.8V , ∆I = 14.2A
For high-side switch the maximum power dissipation
happens at maximum Vo and maximum duty cycle.
(2.8 + 0.27)
(4.75 - 0.27 + 0.27)
PDH = DMAX × Io2 × RDS(MAX)
4.75 - 2.8
L = 0.006×9000×
= 3.7µH
DMAX »
= 0.65
( 2×14.2 )
Assuming that the programmed switching frequency is
set at 200KHz, an inductor is designed using the
Micrometals’ powder iron core material. The summary
of the design is outlined below:
PDH = 0.65 × 14.22 × 0.029 = 3.8W
RDS(MAX) = Maximum RDS(ON) of the MOSFET (1258C)
For synchronous MOSFET, maximum power dissipa-
The selected core material is Powder Iron, the selected tion happens at minimum Vo and minimum duty cycle.
core is T50-52D from Micro Metal wound with 8 turns of
#16 AWG wire, resulting in 3µH inductance with » 3mΩ
of DC resistance.
(2 + 0.27)
(5.25 - 0.27 + 0.27)
DMIN »
= 0.43
PDS = (1 - DMIN) × Io2 × RDS(MAX)
PDS = (1 - 0.43) × 14.22 × 0.029 = 3.33W
Assuming L=3µH and Fsw=200KHz (switching fre-
quency), the inductor ripple current and the output ripple
voltage is calculated using the following set of equations: Heat Sink Selection
Selection of the heat sink is based on the maximum
T º Switching Period
D º Duty Cycle
allowable junction temperature of the MOSFETS. Since
we previously selected the maximum RDS(on) at 1258C,
then we must keep the junction below this temperature.
Selecting TO-220 package gives θJC=1.88C/W (from the
venders’ data sheet) and assuming that the selected
heat sink is black anodized, the heat-sink-to-case ther-
mal resistance is θCS=0.058C/W, the maximum heat sink
temperature is then calculated as:
Vsw º High side Mosfet ON Voltage
RDS º Mosfet On Resistance
Vsync º Synchronous MOSFET ON Voltage
∆Ir º Inductor Ripple Current
∆Vo º Output Ripple Voltage
1
Fsw
TON = D×T
T =
TOFF = T - TON
Ts = TJ - PD × (θJC + θCS)
Vsw = Vsync = Io×RDS
TOFF
L
∆Ir = (Vo + Vsync)×
∆Vo = ∆Ir×ESR
Ts = 125 - 3.82 × (1.8 + 0.05) = 1188C
Vo + Vsync
VIN - Vsw + Vsync
D »
Rev. 1.7
07/16/02
www.irf.com
11
IRU3004
With the maximum heat sink temperature calculated in Switcher Timing Capacitor Selection
the previous step, the heat-sink-to-air thermal resistance The switching frequency can be programmed using an
(θSA) is calculated as follows:
Assuming TA = 358C:
external timing capacitor. The value of Ct can be ap-
proximated using the equation below:
3.5 × 10-5
Fsw y
∆T = Ts - TA = 118 - 35 = 838C
Temperature Rise Above Ambient
Ct
Where:
Ct = Timing Capacitor
Fsw = Switching Frequency
∆T 83
PD 3.82
θSA =
=
= 228C/W
Next, a heat sink with lower θSA than the one calculated If Fsw = 200KHz:
in the previous step must be selected. One way is to
3.5 × 10-5
Ct y
= 175pF
simply look at the graphs of the “Heat Sink Temp Rise
Above the Ambient” vs. the “Power Dissipation” given in
the heat sink manufacturers’ catalog and select a heat
200 × 103
LDO Power MOSFET Selection
sink that results in lower temperature rise than the one The first step in selecting the power MOSFET for the
calculated in previous step. The following heat sinks from linear regulators is to select its maximum RDS(ON) based
AAVID and Thermalloy meet this criteria.
on the input to output Dropout voltage and the maximum
load current.
Company Part #
Thermalloy............................6078B
AAVID..................................577002
For Vo = 1.5V, VIN = 3.3V and IL = 2A:
(VIN - Vo) (3.3 - 1.5)
RDS(max) =
=
= 0.9Ω
IL
2
Following the same procedure for the Schottky diode
results in a heat sink with θSA=258C/W. Although it is Note that since the MOSFETs RDS(ON) increases with
possible to select a slightly smaller heat sink, for sim- temperature, this number must be divided by » 1.5, in
plicity, the same heat sink as the one for the high side order to find the RDS(on) max at room temperature. The
MOSFET is also selected for the synchronous MOSFET. Motorola MTP3055VL has a maximum of 0.18Ω RDS(ON)
at room temperature, which meets our requirement.
Switcher Current Limit Protection
The PWM controller uses the MOSFET RDS(ON) as the To select the heat sink for the LDO MOSFET the first
sensing resistor to sense the MOSFET current and com- step is to calculate the maximum power dissipation of
pares to a programmed voltage which is set externally the device and then follow the same procedure as for the
via a resistor (Rcs) placed between the drain of the switcher.
MOSFET and the “CS+” terminal of the IC as shown in
the application circuit. For example, if the desired cur-
PD = (VIN - Vo) × IL
rent limit point is set to be 22A and from our previous
selection, the maximum MOSFET RDS(ON)=19mΩ, then
the current sense resistor, Rcs is calculated as:
Where:
PD = Power Dissipation of the Linear Regulator
IL = Linear Regulator Load Current
Where:
For the 1.5V and 2A load:
PD = (3.3 - 1.5) × 2 = 3.6W
Assuming TJ(max) = 1258C then:
IB = 200µA is the internal current setting of the de-
vice
Vcs = ICL × RDS = 22 × 0.019 = 0.418V
Ts = TJ - PD × (θJC + θCS)
Vcs
0.418V
200µA
Rcs =
=
= 2.1KΩ
Ts = 125 - 3.6 × (1.8 + 0.05) = 118°C
IB
Rev. 1.7
07/16/02
www.irf.com
12
IRU3004
With the maximum heat sink temperature calculated in Disabling the LDO Regulators
the previous step, the heat-sink-to-air thermal resistance The LDO controllers can easily be disabled by connect-
(θSA) is calculated as follows:
ing the feedback pins (VFB1 and VFB2) to a voltage higher
than 1.5V such as 5V for all devices.
Assuming TA = 358C:
Switcher Output Voltage Adjust
∆T = Ts - TA = 118 - 35 = 838C
Temperature Rise Above Ambient
As was discussed earlier, the trace resistance from the
output of the switching regulator to the Slot 1 can be
used to the circuit advantage and possibly reduce the
number of output capacitors, by level shifting the DC
∆T
PD
83
3.6
qSA =
=
= 238C/W
The same heat sink as the one selected for the switcher regulation point when transitioning from light load to full
MOSFETs is also suitable for the 1.5V regulator. It is load and vice versa. To account for the DC drop, the
also possible to use TO-263 package or even the output of the regulator is typically set about half the DC
MTD3055VL in D-Pak if the load current is less than drop that results from light load to full load. For example,
1.5A. For the 2.5V regulator, since the dropout voltage if the total resistance from the output capacitors to the
is only 0.8V and the load current is less than 0.5A, for Slot 1 and back to the Gnd pin of the part is 5mΩ and if
most applications, the same MOSFET without heat sink the total ∆I, the change from light load to full load is
or for low cost applications, one can use PN2222A in 14A, then the output voltage measured at the top of the
TO-92 or SOT-23 package.
resistor divider which is also connected to the output
capacitors in this case, must be set at half of the 70mV
or 35mV higher than the DAC voltage setting. To do this,
LDO Regulator Component Selection
Since the internal voltage reference for the linear regula- the top resistor of the resistor divider (R12 in the appli-
tors is set at 1.5V for all devices, there is no need to cation circuit) is set at 100Ω, and the R13 is calculated.
divide the output voltage for the 1.5V, GTL+ regulator.
For example, if DAC voltage setting is for 2.8V and the
For the 2.5V Clock supply, the resistor dividers are se- desired output under light load is 2.835V, then R13 is
lected per following:
calculated using the following formula:
VDAC
Rt
R13 = 100×
(Ω)
Vo =
×VREF
1+
(
(
)
( )
RB
(Vo - 1.004×VDAC)
Where:
2.8
R13 = 100×
= 11.76KΩ
)
Rt = Top resistor divider
RB = Bottom resistor divider
Vref = 1.5V typical
(2.835 - 1.004×2.800)
Select 11.8KΩ, 1%
Note:The value of the top resistor must not exceed 100Ω.
The bottom resistor can then be adjusted to raise the
output voltage.
Assuming Rt = 100Ω, for Vo = 2.5V:
Rt
Vo
100
2.5
RB =
=
= 150Ω
- 1
- 1
Soft-Start Capacitor Selection
The soft-start capacitor must be selected such that dur-
ing the start up, when the output capacitors are charg-
(VREF) (1.5 )
For 1.5V output, Rt can be shorted and RB left open. ing up, the peak inductor current does not reach the
However, it is recommended to leave the resistor divid- current limit threshold. A minimum of 1µF capacitor in-
ers as shown in the typical application circuit so that sures this for most applications. An internal 10µA cur-
the output voltage can be adjusted higher to account for rent source charges the soft-start capacitor which slowly
the trace resistance in the final board layout.
ramps up the inverting input of the PWM comparator
VFB3. This insures the output voltage to ramp at the same
It is also recommended that an external filter be added rate as the soft-start cap thereby limiting the input cur-
on the linear regulators to reduce the amount of the high rent. For example, with 1µF and the 10µA internal cur-
frequency ripple at the output of the regulators. This can rent source the ramp up rate is (∆V/∆t)=(I/C)=1V/100ms.
simply be done by the resistor capacitor combination Assuming that the output capacitance is 9000µF, the
as shown in the application circuit.
maximum start up current will be:
I = 9000µF × (1V / 100ms) = 0.09A
Rev. 1.7
07/16/02
www.irf.com
13
IRU3004
Input Filter
Note:Although, the PWM controller does not require
R12-15 resistors, and the feedback pins 3 and 14
can be directly connected to their respective outputs,
they can be used to set the outputs slightly higher to
account for any output drop at the load due to the
trace resistance.
It is recommended to place an inductor between the
system 5V supply and the input capacitors of the switch-
ing regulator to isolate the 5V supply from the switching
noise that occurs during the turn on and off of the switch-
ing components. Typically an inductor in the range of 1
to 3µH will be sufficient in this type of application.
8) Place R11, C15, Q3 and C11 close to each other and
do the same with R9, C14, Q4 and C12.
Switcher External Shutdown
The best way to shutdown the switcher is to pull down
on the soft-start pin using an external small signal tran-
sistor such as 2N3904 or 2N7002 small signal MOSFET.
This allows slow ramp up of the output, the same as the
power up.
Note: It is better to place the linear regulator compo-
nents close to the IC and then run a trace from the
output of each regulator to its respective load such
as 2.5V to the clock and 1.5V for GTL + termination.
However, if this is not possible then the trace from
the linear drive output pins, pins 2 and 20 must be
routed away from any high frequency data signals.
It is critical, to place high frequency ceramic capaci-
tors close to the clock chip and termination resistors
to provide local bypassing.
Layout Considerations
Switching regulators require careful attention to the lay-
out of the components, specifically power components
since they switch large currents. These switching com-
ponents can create large amount of voltage spikes and
high frequency harmonics if some of the critical compo-
nents are far away from each other and are connected 9) Place timing capacitor C1 close to pin 1 and soft
with inductive traces. The following is a guideline of how
to place the critical components and the connections
between them in order to minimize the above issues.
start capacitor C2 close to pin 13.
Component connections:
Note: It is extremely important that no data bus should
Start the layout by first placing the power components: be passing through the switching regulator section spe-
1) Place the input capacitors C3 and the high side cifically close to the fast transition nodes such as PWM
MOSFET, Q1 as close to each other as possible.
drives or the inductor voltage.
2) Place the synchronous MOSFET, Q2 and the Q1 as Using the 4 layer board, dedicate on layer to ground,
close to each other as possible with the intention another layer as the power layer for the 5V, 3.3V, Vcore,
that the source of Q1 and drain of the Q2 has the 1.5V and if it is possible for the 2.5V. Connect all grounds
shortest length.
to the ground plane using direct vias to the ground plane.
Use large low inductance/low impedance plane to con-
nect the following connections either using component
side or the solder side:
3) Place the snubber R4 & C7 between Q1 & Q2.
4) Place the output inductor, L2 and the output capaci-
tors, C10 between the MOSFET and the load with
output capacitors distributed along the slot 1 and
close to it.
a) C3 to Q1 Drain
b) Q1 Source to Q2 Drain
c) Q2 drain to L2
d) L2 to the output capacitors, C10
e) C10 to the slot 1
f) Input filter L1 to the C3
g) C9 to Q4 drain
5) Place the bypass capacitors, C4 and C6 right next to
12V and 5V pins. C4 next to the 12V, pin 12 and C6
next to the 5V, pin 5.
h) C12 to the Q4 source
6) Place the controller IC such that the PWM output Connect the rest of the components using the shortest
drives, pins 9 and 11 are relatively short distance from connection possible.
gates of Q1 and Q2.
IR WORLD HEADQUARTERS : 233 Kansas St.,
El Segundo,California 90245,
7) Place resistor dividers, R7 & R8 close to pin 3, R12
USA Tel: (310) 252-7105
& R13 (see note) close to pin 14 and R14 and R15
(see note) close to pin 20.
TAC Fax: (310) 252-7903
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Data and specifications subject to change without notice. 02/01
Rev. 1.7
07/16/02
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14
IRU3004
(F) TSSOP Package
20-Pin
A
L
Q
R 1
C
B
1.0 DIA
R
E
N
M
P
O
PIN NUMBER 1
F
D
DETAIL A
DETAIL A
G
J
H
K
20-PIN
NOM
0.65 BSC
SYMBOL
DESIG
A
MIN
4.30
0.19
MAX
4.50
0.30
B
4.40
C
6.40 BSC
---
D
E
1.00
1.00
6.50
---
F
6.40
---
6.60
1.10
0.95
0.15
G
H
J
0.85
0.05
0.90
---
K
L
128 REF
M
N
128 REF
08
---
88
O
P
1.00 REF
0.60
0.20
---
0.50
0.75
Q
R
0.09
0.09
---
---
R1
---
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 1.7
07/16/02
www.irf.com
15
IRU3004
(W) SOIC Package
20-Pin Surface Mount, Wide Body
H
A
B
C
R
E
DETAIL-A
L
PIN NO. 1
D
0.51±0.020 x 458
DETAIL-A
I
K
F
T
G
J
SYMBOL
20-PIN
MIN MAX
A
B
C
D
E
F
G
I
12.598 12.979
1.018 1.524
0.66 REF
0.33
7.40
0.508
7.60
2.64
0.30
0.32
2.032
0.10
0.229
J
10.008 10.654
08 88
0.406 1.270
0.63 0.89
2.337 2.642
K
L
R
T
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 1.7
07/16/02
www.irf.com
16
IRU3004
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
F
TSSOP Plastic
20
20
74
38
2500
1000
Fig A
Fig B
W
SOIC, Wide Body
1
1
1
1
1
1
Feed Direction
Figure A
Feed Direction
Figure B
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.7
07/16/02
www.irf.com
17
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