IRU3005CW-TRPBF_技术文档

IRU3004, IRU3005

5-BIT PROGRAMMABLE SYNCHRONOUS BUCK

CONTROLLER IC WITH DUAL LDO CONTROLLER

FEATURES

DESCRIPTION

The IRU3004/IRU3005 series of controller ICs are spe-

cifically designed to meet Intel specifications for Pentium

IIIä microprocessor applications as well as the next

generation P6 family processors. The IC provides a single

chip controller IC for the Vcore, GTL+ and clock sup-

plies required for the Pentium III applications. These

devices feature a patented topology, that in combina-

tion with a few external components as shown in the

typical application circuit, will provide in excess of 20A

of output current for an on-board DC-DC converter while

automatically providing the right output voltage via the

five-bit internal DAC meeting the latest VRM specifica-

tion. These products also feature loss-lesscurrent sens-

Meets latest VRM 8.4 specification for PIII

Provides single chip solution for Vcore, GTL+ and

clock supply

On-board DAC programs the output voltage from

1.3V to 3.5V. The IRU3004/IRU3005 remains on for

VID code of (11111).

Dual linear regulator controller on-board for 1.5V

GTL+ and 2.5V clock supplies

Loss-less short circuit protection

Synchronous operation allows maximum efficiency

Patented architecture allows fixed frequency opera-

tion as well as 100% duty cycle during dynamic

load

ing by using the R

of the high side power MOSFET

Minimum part count. No external compensation.

Soft start

High current totem pole driver for direct driving of the

external power MOSFET

DS(on)

as the sensing resistor and a Power Good window com-

parator that switches its open collector output low when

the output is outside of a ±10% window. Other features

of the device are: Undervoltage lockout for both 5V and

12V supplies, an external programmable soft start func-

tion as well as programming the oscillator frequency by

using an external capacitor.

Power Good function

APPLICATIONS

Pentium III & next generation processor DC to DC

converter application

Low cost Pentium with AGP

TYPICAL APPLICATION

L1

L2

Q1

5V

Vout 3

R16

R17

C16

C5

R1

C7

R4

Q2

C13

C3

C4

C10

R2

R3

R12

R13

3.3V

12V

C6

Q3

Vout 1

Vout 2

C11

R18

12

V12

5

V5

8

CS+

9

7

CS-

11

10

Gnd

14

Vfb3

R7

R8

HDrv

LDrv

R11

C15

1

Ct

Lin1 2

C1

IRU3004

13 SS

D4

Vfb1

Lin2

3

Q4

C2

D3

16

D2

17

D1

18

D0

19

PGd

6

Vfb2

4

15

20

C9

C12

R14

R15

VID4

3004app2-2.0

VID3

VID2

VID1

VID0

R9

3.3V

C14

R5

PowerGood

C8

Notes: Pentium III is trademark of Intel Corp.

PACKAGE ORDER INFORMATION

Ta (°C)

0 TO 70

Device

IRU3004CW

IRU3005CW

Package

20-pin Plastic SOIC WB

2.5V Output Voltage

Adjustable

Fixed

Rev. 1.2

12/8/00

4-3

IRU3004, IRU3005

ABSOLUTE MAXIMUM RATINGS

V5 supply Voltage ................................................. 10V

V12 Supply Voltage ................................................. 20V

Storage Temperature Range ...................................... -65 TO 150°C

Operating Junction Temperature Range ...................... 0 TO 125°C

PACKAGE INFORMATION

20-PIN WIDE BODY PLASTIC SOIC (W)

TOP VIEW

1

2

3

4

5

6

7

8

9

20

19

18

17

16

Ct / En

Lin1

Vfb1

Vfb2

V5

Lin2

D0

D1

D2

D3

PGd

CS-

15 D4

14 Vfb3

13 SS

CS+

HDrv

12 V12

11 LDrv

Gnd 10

qJA=85°C/W

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over,V12 = 12V, V5 = 5V and Ta=0 to 70°C. Typical values

refer to Ta =25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the

ambient temperature.

PARAMETER

SYM

TEST CONDITION

MIN

TYP

MAX

UNITS

VID Section

DAC output voltage

0.99Vs

Vs

1.01Vs

V

(note 1)

DAC Output Line Regulation

DAC Output Temp Variation

VID Input LO

0.1

0.5

0.4

%

V

VID Input HI

2

V

VID input internal pull-up

resistor to V5

27

kW

Power Good Section

Under voltage lower trip point

Under voltage upper trip point

UV Hysterises

Vout ramping down

Vout ramping up

0.89Vs

0.90Vs

0.92Vs

.02Vs

0.91Vs

V

.015Vs

1.09Vs

.025Vs

1.11Vs

Over voltage upper trip point

Over voltage lower trip point

OV Hysterises

Vout ramping up

1.10Vs

1.08Vs

.02Vs

Vout ramping down

.015Vs

4.8

.025Vs

0.4

Power Good Output LO

Power Good Output HI

Soft Start Section

Soft Start Current

RL=3mA

RL=5K pull up to 5V

CS+ =0V, CS- =5V

10

mA

Rev. 1.2

12/8/00

4-4

IRU3004, IRU3005

PARAMETER

UVLO Section

SYM

TEST CONDITION

Supply ramping up

MIN

TYP

MAX

UNITS

UVLO Threshold-12V

UVLO Hysterises-12V

UVLO Threshold-5V

UVLO Hysterises-5V

Error Comparator Section

Input bias current

9.2

0.3

4.1

0.2

10

10.8

0.5

4.5

0.4

V

0.4

4.3

0.3

2

+2

100

mA

mV

nS

Input Offset Voltage

Delay to Output

-2

Vdiff=10mV

Current Limit Section

C.S Threshold Set Current

C.S Comp Offset Voltage

Hiccup Duty Cycle

Supply Current

160

-5

200

240

+5

2

mA

mV

%

Css=0.1mF

Operating Supply Current

CL=3000pF

V5

20

14

V12

mA

Output Drivers Section

Rise Time

Fall Time

Dead Band Time

Oscillator Section

Osc Frequency

Osc Valley

CL=3000pF

70

200

100

130

300

nS

100

190

Ct=150pF

220

V5

250

0.2

Khz

V

Osc Peak

V

LDO Controller Section

Vfb1 & Vfb2 (IRU3004)

Vfb2 (IRU3005)

Vfb1 (IRU3005)

Input bias current

Lin1 or Lin2 Drive Current

1.477

1.500

2.500

50

1.522

2

V

mA

Note 1: Vs refers to the set point voltage given in Table 1.

D4

0

D3

1

0

D2

1

0

1

0

D1

1

0

1

0

1

0

1

0

D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Vs

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

D4

1

D3

1

0

D2

1

0

1

0

D1

D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Vs

1

0

1

0

1

0

1

0

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Table 1 - Set point voltage vs. VID codes

Rev. 1.2

12/8/00

4-5

IRU3004, IRU3005

PIN DESCRIPTIONS

PIN# PIN SYMBOL

PIN DESCRIPTION

19

18

17

16

15

6

D0

D1

LSB input to the DAC that programs the output voltage. This pin can be pulled up

externally by a 10k resistor to either 3.3V or 5V supply.

Input to the DAC that programs the output voltage. This pin can be pulled up externally

by a 10kW resistor to either 3.3V or 5V supply.

D2

Input to the DAC that programs the output voltage. This pin can be pulled up externally

by a 10k resistor to either 3.3V or 5V supply.

D3

MSB input to the DAC that programs the output voltage. This pin can be pulled up

externally by a 10k resistor to either 3.3V or 5V supply.

D4

This pin selects a range of output voltages for the DAC. When in the LOW state the

range is 1.3V to 2.05V. For VID codes of all "1" the IRU3004 keeps all the outputs on.

PGd

This pin is an open collector output that switches LO when the output of the con-

verter is not within ±10% (typ) of the nominal output voltage. When PWRGD pin switches

LO the sat voltage is less than 0.4V at 3mA.

14

8

Vfb3

CS+

This pin is connected directly to the output of the Core supply to provide feedback to the

Error comparator.

This pin is connected to the Drain of the power MOSFET of the Core supply and it

provides the positive sensing for the internal current sensing circuitry. An external resis

tor programs the C.S threshold depending on the R

of the power MOSFET. An

DS

external capacitor is placed in parallel with the programming resistor to provide high

frequency noise filtering.

7

CS-

SS

This pin is connected to the Source of the power MOSFET for the Core supply and it

provides the negative sensing for the internal current sensing circuitry.

13

This pin provides the soft start for the switching regulator. An internal current source

charges an external capacitor that is connected from this pin to the GND which ramps

up the outputs of the switching regulator, preventing the outputs from overshooting as

well as limiting the input current. The second function of the Soft Start cap is to provide

long off time (HICCUP) for the synchronous MOSFET during current limiting.

1

2

Ct

This pin programs the oscillator frequency in the range of 50kHZ to 500kHZ with an

external capacitor connected from this pin to the GND.

Lin1

Vfb1

Lin2

This pin controls the gate of an external transistor for either the GTL+ linear regulator or

Clock supply.

3

This pin provides the feedback for the linear regulator that its output drive is Lin1 pin. For

IRU3005, this pin is connected to the 2.5V regulator, eliminating the external dividers.

20

This pin controls the gate of an external transistor for either the GTL+ linear regulator or

Clock supply.

4

Vfb2

Gnd

This pin provides the feedback for the linear regulator that its output drive is Lin2 pin.

10

This pin serves as the ground pin and must be connected directly to the ground plane.

A high frequency capacitor (0.1 to 1mF) must be connected from V5 and V12 pins to

this pin for noise free operation.

11

9

LDrv

HDrv

V12

Output driver for the synchronous power MOSFET.

Output driver for the high-side power MOSFET.

12

This pin is connected to the 12 V supply and serves as the power Vcc pin for the output

drivers. A high frequency capacitor (0.1 to 1mF) must be connected directly from this pin

to GND pin in order to supply the peak current to the power MOSFET during the transi

tions.

5

V5

5V supply voltage.

Rev. 1.2

12/8/00

4-6

IRU3004, IRU3005

BLOCK DIAGRAM

Vfb3

Enable

Vset

V12

Vset

Enable

HDrv

V12

UVLO

PWM

Control

V5

+

V12

Slope

Comp

LDrv

Enable

D0

D1

D2

D3

D4

Osc

5Bit

DAC,

Ctrl

CS-

Over

Current

Soft

Start &

Fault

CS+

Logic

200uA

Logic

Enable

Ct / En

SS

Vfb2

Lin2

1.1Vset

PGd

Gnd

1.5V

Lin1

Vfb1

0.9Vset

3004blk2-1.3

Figure 1 - Simplified block diagram of the IRU3004

Rev. 1.2

12/8/00

4-7

IRU3004, IRU3005

TYPICAL APPLICATION

Pentium III

L1

L2

Q1

5V

Vout 3

R16

R17

C16

C5

R1

C7

R4

Q2

C13

C3

C4

C10

R2

R3

R12

R13

3.3V

12V

C6

Q3

Vout 1

C11

12

5

8

9

7

11

10

14

Vfb3

R18

R7

R8

V12

V5

CS+

HDrv

CS-

LDrv

Gnd

R11

C15

1

Ct

Lin1

2

C1

IRU3004

13 SS

D4

15

Vfb1

Lin2

20

3

Q4

C2

Vout 2

D3

16

D2

17

D1

18

D0

19

PGd

6

Vfb2

4

C9

C12

R14

VID4

3004app2-2.0

VID3

VID2

VID1

VID0

R9

3.3V

C14

R15

R5

Power Good

C8

Figure 2 - Typical application of IRU3004 or IRU3005 in an on-board DC-DC converter providing the

Core, GTL+, and Clock supplies for the Pentium II microprocessor

Part #

IRU3004

IRU3005

R7 Value

See Parts List

Short

R8 Value

See Parts List

Open

Table 2 - Describes the differences between IRU3004 and IRU3005 applications

Rev. 1.2

12/8/00

4-8

IRU3004, IRU3005

IRU3004/IRU3005 Application Parts List

Ref Design Description Qty

Part #

Manuf

Q1

Q2

Q3

Q4

L1

MOSFET

1

2

1

3

1

6

1

3

2

1

3

1

IRL3103S, TO-263 package

IRL3103D1S, TO-263 package

MPS2222A, SOT-23 package

IRLR024, TO-252 package

IR

MOSFET

Bipolar Trans, GP

MOSFET

Motorola

IR

Inductor

L=1mH, 5052 core with 4 turns of 1.0mm wire

L=2.7mH, 5052B core with 7 turns of 1.2mm wire

150pF, 0603

MicroMetal

Micro Metal

L2

Inductor

C1

Capacitor, Ceramic

Capacitor, Electrolytic

Capacitor, Ceramic

C2, 6

C3

1uF, 0603

10MV1200GX, 1200mF,10V

1mF, 0805

Sanyo

C4

C5

220pF, 0603

C7, 14, 15 Capacitor, Ceramic

1000pF, 0603

C8

C9

Capacitor, Ceramic

Capacitor, Electrolytic

Capacitor, Ceramic

Resistor

0.1mF, 0603

6MV1000GX, 1000mF, 6.3V

6MV1500GX, 1500mF, 6.3V

6MV150GX, 150mF, 6.3V

6MV1000GX, 1000mF, 6.3V

10MV470GX, 470mF, 10V

4.7mF, 1206

Sanyo

C10

C11

C12

C13

C16

R1

3.3kW, 5%, 0603

R2, 3, 4 Resistor

4.7W, 5%, 1206

R5, 15

R7, 12

R8

Resistor

10kW, 5%, 0603

100W, 1%, 0603

150W, 1%, 0603

R9, 11, 14 Resistor

100W, 5%, 0603

R13

R16

R17

R18

Resistor

22kW, 1%, 0603

220W, 1%, 0603

330W, 1%, 0603

10W, 5%, 0603

Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient voltage

Note 2: R14 and R15 set the 1.5V approximately 1% higher to account for the trace resistance drop

Rev. 1.2

12/8/00

4-9

IRU3004, IRU3005

TYPICAL APPLICATION

Pentium with AGP

L1

L2

Q1

5V

Vout 3

R16

R17

C16

C5

R1

C7

R4

Q2

C13

C3

C4

C10

R2

R3

R12

R13

3.3V

12V

Q3

C6

C9

C11

12

5

8

9

7

11

10

14

Vfb3

Lin1

R18

R7

R8

V12

V5

CS+

HDrv

CS-

LDrv

Gnd

R11

1

Ct

2

3

C15

C1

IRU3004

13 SS

Vfb1

C2

D4

15

D3

16

D2

17

D1

18

D0

19

PGd

6

Vfb2

4

Lin2

20

Q4

3.3V

C12

R9

VID4

R14

VID3

VID2

VID1

VID0

C14

3.3V

3004app3-1.4

R15

R5

Power Good

C8

Figure 3 - Typical application of IRU3004 in a Pentium with AGP where the power dissipation of the 3.3V

linear regulator is equally distributed between Q3 and Q4 pass transistors. This equal distribution is

possible by accurately regulating the first regulator using the IRU3004 linear controller and its internal

1% reference voltage while the second controller regulates the output of the first regulator from 4.17V to

3.3V, thereby distributing the power dissipation equally.

Rev. 1.2

12/8/00

4-10

IRU3004, IRU3005

IRU3004 Application Parts List

Ref Desig Description

Qty

Part #

Manuf

Q1

Q2

MOSFET

Inductor

1

IRL3103s, TO-263 package

IRL3103D1S, TO-263 package

IRL3303S, TO-263 package

L=1mH, 5052 core with 4 turns of

1.0mm wire

IR

1

2

1

IR

Q3,4

L1

Micro Metal

L2

Inductor

1

L=2.7mH, 5052B core with 7 turns of

1.2mm wire

Micro Metal

Sanyo

C1

C2,6

C3

Capacitor, Ceramic

Capacitor, Electrolytic

Capacitor, Ceramic

1

2

1

3

1

6

1

3

2

1

2

3

1

150pF, 0603

1mF, 0603

10MV1200GX, 1200mF,10V

1mF, 0805

C4

C5

220pF, 0603

C7,14,15 Capacitor, Ceramic

1000pF, 0603

C8

C9

Capacitor, Ceramic

Capacitor, Electrolytic

Capacitor, Ceramic

Resistor

0.1mF, 0603

6MV1000GX, 1000mF, 6.3V

6MV1500GX, 1500mF, 6.3V

6MV150GX, 150mF, 6.3V

6MV1000GX, 1000mF, 6.3V

10MV470GX, 470mF, 10V

4.7mF, 1206

Sanyo

C10

C11

C12

C13

C16

R1

3.3kW, 5%, 0603

R2,3,4

R5,15

R7

Resistor

4.7W, 5%, 1206

Resistor

10kW, 5%, 0603

Resistor

267W, 1%, 0603

R8

Resistor

150W, 1%, 0603

R9,11,14 Resistor

100W, 5%, 0603

R12

R13

R16

R17

R18

Resistor

100W, 1%, 0603

22kW, 1%, 0603

220W, 1%, 0603

330W, 1%, 0603

10W, 5%, 0603

Note 1: R16, R17, C16, R12, and R13 set the Vcore 2% higher for level shift to reduce CPU transient voltage

Rev. 1.2

12/8/00

4-11

IRU3004, IRU3005

shifting during the load transient eases the requirement

for the output capacitor ESR at the cost of load regula-

tion. One can show that the new ESR requirement eases

up by half the total trace resistance. For example, if the

ESR requirement of the output capacitors without volt-

age level shifting must be 7mW, then after level shifting

the new ESR will only need to be 9.5mW if the trace

resistance is 5mW (7+5/2=9.5). However, one must be

careful that the combined “voltage level shifting” and the

transient response is still within the maximum tolerance

of the Intel specification. To insure this, the maximum

trace resistance must be less than:

APPLICATION INFORMATION

An example of how to calculate the components for the

application circuit is given below.

Assuming, two sets of output conditions that this regu-

lator must meet,

a) Vo=2.8V, Io=14.2A, DVo=185mV, DIo=14.2A

b) Vo=2V, Io=14.2A, DVo=140mV, DIo=14.2A

The regulator design will be done such that it meets the

worst case requirement of each condition.

Output Capacitor Selection

Rs£ 2(Vspec - 0.02*Vo - DVo)/DI

Where :

The first step is to select the output capacitor. This is

done primarily by selecting the maximum ESR value

that meets the transient voltage budget of the total DVo

specification. Assuming that the regulators DC initial

accuracy plus the output ripple is 2% of the output volt-

age, then the maximum ESR of the output capacitor is

calculated as:

Rs=Total maximum trace resistance allowed

Vspec=Intel total voltage spec

Vo=Output voltage

DVo=Output ripple voltage

DI=load current step

For example, assuming:

Vspec=±140 mV=±0.1V for 2V output

Vo=2V

DVo=assume 10mV=0.01V

DI=14.2A

100

ESR £

= 7 mW

14.2

The Sanyo MVGX series is a good choice to achieve

both the price and performance goals. The 6MV1500GX,

1500mF, 6.3V has an ESR of less than 36mW typical.

Selecting 6 of these capacitors in parallel has an ESR

of »6mW which achieves our low ESR goal.

Then the Rs is calculated to be:

Rs£ 2(0.140 - 0.02*2 - 0.01)/14.2=12.6mW

However, if a resistor of this value is used, the maximum

power dissipated in the trace (or if an external resistor is

being used) must also be considered. For example if

Other type of Electrolytic capacitors from other manu-

facturers to consider are the Panasonic FA series or the

Nichicon PL series.

Rs=12.6mW,

the

power

dissipated

is

(Io^2)*Rs=(14.2^2)*12.6=2.54W. This is a lot of power to

be dissipated in a system. So, if the Rs=5mW, then the

power dissipated is about 1W which is much more ac-

ceptable. If level shifting is not implemented, then the

maximum output capacitor ESR was shown previously

to be 7mW which translated to » 6 of the 1500mF,

6MV1500GX type Sanyo capacitors. With Rs=5mW, the

maximum ESR becomes 9.5mW which is equivalent to

» 4 caps. Another important consideration is that if a

trace is being used to implement the resistor, the power

dissipated by the trace increases the case temperature

of the output capacitors which could seriously effect the

life time of the output capacitors.

Reducing the Output Capacitors Using Voltage Level

Shifting Technique

The trace resistance or an external resistor from the output

of the switching regulator to the Slot 1 can be used to

the circuit advantage and possibly reduce the number of

output capacitors, by level shifting the DC regulation point

when transitioning from light load to full load and vice

versa. To accomplish this, the output of the regulator is

typically set about half the DC drop that results from

light load to full load. For example, if the total resistance

from the output capacitors to the Slot 1 and back to the

GND pin of the device is 5mW and if the total DI, the

change from light load to full load is 14A, then the output

voltage measured at the top of the resistor divider which

is also connected to the output capacitors in this case,

must be set at half of the 70mV or 35mV higher than the

DAC voltage setting. This intentional voltage level

Output Inductor Selection

The output inductance must be selected such that un-

der low line and the maximum output voltage condition,

the inductor current slope times the output capacitor

ESR is ramping up faster than the capacitor voltage is

Rev. 1.2

12/8/00

4-12

IRU3004, IRU3005

drooping during a load current step. However, if the in- Power Component Selection

ductor is too small, the output ripple current and ripple

voltage become too large. One solution to bring the ripple Assuming IRL3103 MOSFETs as power components,

current down is to increase the switching frequency, we will calculate the maximum power dissipation as fol-

however that will be at the cost of reduced efficiency and lows:

higher system cost. The following set of formulas are

For high-side switch the maximum power dissipation

derived to achieve the optimum performance without

happens at maximum Vo and maximum duty cycle.

many design iterations.

Dmax » ( 2.8 + 0.27 ) / ( 4.75 - 0.27 + 0.27 ) = 0.65

The maximum output inductance is calculated using the

following equation:

L = ESR * C * ( Vinmin - Vomax ) / ( 2* DI )

Where:

Vinmin = Minimum input voltage

For Vo = 2.8 V , DI = 14.2 A

Pdh = Dmax * Io^2*R

DS(max)

Pdh= 0.65*14.2^2*0.029=3.8 W

=Maximum R of the MOSFET at 125°C

R

DS(max) DS(on)

For synch MOSFET, maximum power dissipation hap-

pens at minimum Vo and minimum duty cycle.

Dmin » ( 2 + 0.27 ) / ( 5.25 - 0.27 + 0.27 ) = 0.43

L =0.006 * 9000 * ( 4.75 - 2.8) / (2 * 14.2) = 3.7mH

Pds = (1-Dmin)*Io^2*R

Pds=(1 - 0.43) * 14.2^2 * 0.029 = 3.33 W

DS(max)

Assuming that the programmed switching frequency is

set at 200KHZ, an inductor is designed using the Heatsink Selection

Micrometals’ powder iron core material. The summary

of the design is outlined below:

Selection of the heat sink is based on the maximum

allowable junction temperature of the MOSFETS. Since

we previously selected the maximum R at 125°C,

then we must keep the junction below this temperature.

Selecting TO-220 package gives qjc=1.8°C/W (from the

venders’ datasheet ) and assuming that the selected

heatsink is black anodized, the heat-sink-to-case ther-

mal resistance is; qcs=0.05°C/W, the maximum heat

sink temperature is then calculated as:

The selected core material is Powder Iron, the selected

core is T50-52D from Micro Metal wounded with 8 turns

of # 16 AWG wire, resulting in 3mH inductance with » 3

mW of DC resistance.

DS(on)

Assuming L = 3mH and the switching frequency; Fsw =

200KHZ , the inductor ripple current and the output ripple

voltage is calculated using the following set of equations:

T = 1/Fsw

T º Switching Period

D » ( Vo + Vsync ) / ( Vin - Vsw + Vsync )

D º Duty Cycle

Ts = Tj - Pd * (qjc + qcs)

Ts = 125 - 3.82 * (1.8 + 0.05) = 118 °C

With the maximum heat sink temperature calculated in

the previous step, the heat-sink-to-air thermal resistance

(qsa) is calculated as follows:

Ton = D * T

Vsw º High side Mosfet ON Voltage = Io * R

DS

R

º Mosfet On Resistance

DS

Assuming Ta=35 °C

DT = Ts - Ta = 118 - 35 = 83 °C Temperature Rise

Above Ambient

qsa = DT/Pd

qsa = 83 / 3.82 = 22 °C/W

T

= T - T

off

on

Vsync º Synchronous MOSFET ON Voltage=Io * R

DS

DIr = ( Vo + Vsync ) * T /L

off

DIr º Inductor Ripple Current

DVo = DIr * ESR

Next, a heat sink with lower qsa than the one calculated

in the previous step must be selected. One way to do

DVo º Output Ripple Voltage

In our example for Vo = 2.8V and 14.2 A load, assuming this is to simply look at the graphs of the “Heat Sink

IRL3103 MOSFET for both switches with maximum on- Temp Rise Above the Ambient” vs. the “Power Dissipa-

resistance of 19mW, we have:

T = 1 / 200000 = 5mSec

Vsw =Vsync= 14.2*0.019=0.27 V

D » ( 2.8 + 0.27 ) / ( 5 - 0.27 + 0.27 ) = 0.61

tion” given in the heatsink manufacturers’ catalog and

select a heat sink that results in lower temperature rise

than the one calculated in previous step. The following

heat sinks from AAVID and Thermalloy meet this crite-

ria.

T

off

= 0.61 * 5 = 3.1mSec

= 5 - 3.1 = 1.9mSec

on

Co.

Part #

6078B

577002

DIr = ( 2.8 + 0.27 ) * 1.9 / 3 = 1.94A

DVo = 1.94 * .006 = .011 V = 11mV

Thermalloy

AAVID

Rev. 1.2

12/8/00

4-13

IRU3004, IRU3005

Following the same procedure for the Schottky diode

results in a heatsink with qsa = 25 °C/W. Although it is

possible to select a slightly smaller heatsink, for sim-

plicity the same heatsink as the one for the high side

MOSFET is also selected for the synchronous MOSFET.

Note that since the MOSFETs R

DS(on)

increases with

temperature, this number must be divided by » 1.5, in

order to find the R max at room temperature. The

DS(on)

Motorola MTP3055VL has a maximum of 0.18W R

DS(on)

at room temperature, which meets our requirement.

Switcher Current Limit Protection

To select the heatsink for the LDO MOSFET the first

step is to calculate the maximum power dissipation of

the device and then follow the same procedure as for the

switcher.

The PWM controller uses the MOSFET R

DS(on)

as the

sensing resistor to sense the MOSFET current and com-

pares to a programmed voltage which is set externally

via a resistor (Rcs) placed between the drain of the

MOSFET and the “CS+” terminal of the IC as shown in

the application circuit. For example, if the desired cur-

rent limit point is set to be 22A and from our previous

Pd = ( Vin - Vo ) * IL

Where :

Pd = Power Dissipation of the Linear Regulator

IL = Linear Regulator Load Current

selection, the maximum MOSFET R

the current sense resistor, Rcs is calculated as:

=19mW, then

DS(on)

For the 1.5V and 2A load:

Vcs=IcL*Rds=22*0.019=0.418V

Rcs=Vcs/Ib=(0.418V)/(200uA)=2.1kW

Where: Ib=200mA is the internal current setting of the

device

Pd = (3.3 - 1.5)*2=3.6 W

Assuming Tj-max=125°C

Ts = Tj - Pd * (qjc + qcs)

Ts = 125 - 3.6 * (1.8 + 0.05) = 118 °C

Switcher Timing Capacitor Selection

With the maximum heat sink temperature calculated in

the previous step, the heat-sink-to-air thermal resistance

(qsa) is calculated as follows:

The switching frequency can be programmed using an

external timing capacitor. The value of Ct can be ap-

proximated using the equation below:

Assuming Ta=35 °C

DT = Ts - Ta = 118 - 35 = 83 °C Temperature Rise

Above Ambient

3.5´ 10^{- 5}

F

SW

»

CT

qsa = DT/Pd

qsa = 83 / 3.6 = 23 °C/W

Where:

Cr = Timing Capacitor

FSW = Switching Frequency

The same heat sink as the one selected for the switcher

MOSFETs is also suitable for the 1.5V regulator. It is

also possible to use TO-263 package or even the

MTD3055VL in D-Pak if the load current is less than

1.5A. For the 2.5V regulator since the dropout voltage is

only 0.8V and the load current is less than 0.5A, for

most applications the same MOSFET without heat sink

or for low cost applications, one can use PN2222A in

TO-92 or SOT-23 package.

If, FSW = 200kHz:

3.5 ´ 10^{- 5}

200 ´ 10³

C

T

»

= 175pF

LDO Power MOSFET Selection

LDO Regulator Component Selection

The first step in selecting the power MOSFET for the

linear regulators is to select its maximum R

on the input to output Dropout voltage and the maximum

load current.

based

Since the internal voltage reference for the linear regula-

tors is set at 1.5V for all devices, there is no need to

divide the output voltage for the 1.5V, GTL+ regulator.

DS(on)

R

= (V - Vo) / IL

DS(max)

in

For Vo = 1.5V, and V = 3.3V , IL=2A

in

R

= (3.3 - 1.5)/2= 0.9W

DS(max)

Rev. 1.2

12/8/00

4-14

IRU3004, IRU3005

For the 2.5V, Clock supply the resistor dividers are se-

lected per following:

14A, then the output voltage measured at the top of the

resistor divider which is also connected to the output

capacitors in this case, must be set at half of the 70 mV

or 35mV higher than the DAC voltage setting. To do this,

the top resistor of the resistor divider (R12 in the appli-

cation circuit) is set at 100W, and the R13 is calculated.

For example, if DAC voltage setting is for 2.8V and the

desired output under light load is 2.835V, then R13 is

calculated using the following formula:

Vo=(1+Rt/Rb)*Vref

Where:

Rt=Top resistor divider

Rb=Bottom resistor divider

Vref=1.5V typical

Assuming Rt=100W, for Vo=2.5V

Rb=Rt / [(Vo/Vref) - 1]

Rb=100 / [(2.5/1.5) - 1]=150W

R13= 100*{Vdac /(Vo - 1.004*Vdac)} [W]

R13= 100*{2.8 /(2.835 - 1.004*2.800)} = 11.76 kW

Select 11.8 kW , 1%

For 1.5V output, Rt can be shorted and Rb left open.

However, it is recommended to leave the resistor divid-

ers as shown in the typical application circuit so that

the output voltage can be adjusted higher to account for

the trace resistance in the final board layout.

Note: The value of the top resistor must not exceed 100W.

The bottom resistor can then be adjusted to raise the

output voltage.

It is also recommended that an external filter be added

on the linear regulators to reduce the amount of the high

frequency ripple at the output of the regulators. This can

simply be done by the resistor capacitor combination

as shown in the application circuit.

Soft Start Capacitor Selection

The soft start capacitor must be selected such that dur-

ing the start up when the output capacitors are charging

up, the peak inductor current does not reach the current

limit threshold. A minimum of 1mF capacitor insures this

for most applications. An internal 10mA current source

charges the soft start capacitor which slowly ramps up

the inverting input of the PWM comparator Vfb3. This

insures the output voltage to ramp at the same rate as

the soft start cap thereby limiting the input current. For

example, with 1mF and the 10mA internal current source

the ramp up rate is (DV/ Dt)=I/C = 1V/100mS. Assum-

ing that the output capacitance is 9000mF, the maxi-

mum start up current will be:

For IRU3005 that includes the resistor dividers internally,

Vfb1 can be directly connected to the output voltage

without any external resistors for a preset voltage of 2.5V.

The disadvantage is that the output voltage is not ad-

justable anymore. The application circuit given for

Pentium II can use either the IRU3004 or IRU3005 fam-

ily of parts for maximum flexibility.

Disabling the LDO Regulators

The LDO controllers can easily be disabled by connect-

ing the feedback pins, Vfb1 and Vfb2 to a voltage higher

than 2.5V such as 5V for all devices.

I=9000mF*(1V/100mS)=0.09A

Input Filter

Switcher Output Voltage Adjust

It is highly recommended to place an inductor between

the system 5V supply and the input capacitors of the

switching regulator to isolate the 5V supply from the

switching noise that occurs during the turn on and off of

the switching components. Typically an inductor in the

range of 1 to 3mH will be sufficient in this type of appli-

cation.

As it was discussed earlier, the trace resistance from

the output of the switching regulator to the Slot 1 can be

used to the circuit advantage and possibly reduce the

number of output capacitors, by level shifting the DC

regulation point when transitioning from light load to full

load and vice versa. To account for the DC drop, the

output of the regulator is typically set about half the DC

drop that results from light load to full load. For example,

if the total resistance from the output capacitors to the

Slot 1 and back to the GND pin of the part is 5mW and if

the total DI, the change from light load to full load is

Switcher External Shutdown

The best way to shutdown the switcher is to pull down

on the soft start pin using an external small signal tran-

sistor such as 2N3904 or 2N7002 small signal MOSFET.

This allows slow ramp up of the output, the same as the

power up.

Rev. 1.2

12/8/00

4-15

IRU3004, IRU3005

Layout Considerations

Switching regulators require careful attention to the lay-

out of the components, specifically power components

since they switch large currents. These switching com-

ponents can create large amount of voltage spikes and

high frequency harmonics if some of the critical compo-

nents are far away from each other and are connected

with inductive traces. The following is a guideline of how

to place the critical components and the connections

between them in order to minimize the above issues.

8) Place R11, C15, Q3 and C11 close to each other and

do the same with R9, C14, Q4 and C12.

Note: It is better to place the linear regulator compo-

nents close to the IC and then run a trace from the

output of each regulator to its respective load such

as 2.5V to the clock and 1.5V for GTL + termination.

However, if this is not possible then the trace from

the linear drive output pins, pins 2 and 20 must be

routed away from any high frequency data signals.

Start the layout by first placing the power components:

It is critical, to place high frequency ceramic capaci-

tors close to the clock chip and termination resistors

to provide local bypassing.

1) Place the input capacitors C3 and the high side

MOSFET, Q1 as close to each other as possible

2) Place the synchronous MOSFET, Q2 and the Q1 as

close to each other as possible with the intention

that the source of Q1 and drain of the Q2 has the

shortest length.

9) Place timing capacitor C1 close to pin 1 and soft

start capacitor C2 close to pin 13.

Component connections:

3) Place the snubber R4 & C7 between Q1 & Q2.

Note: It is extremely important that no data bus should

be passing through the switching regulator section spe-

cifically close to the fast transition nodes such as PWM

drives or the inductor voltage.

4) Place the output inductor, L2 and the output capaci-

tors, C10 between the MOSFET and the load with

output capacitors distributed along the slot 1 and

close to it.

Using the 4 layer board, dedicate on layer to GND, an-

other layer as the power layer for the 5V, 3.3V, Vcore,

1.5V and if it is possible for the 2.5V.

5) Place the bypass capacitors, C4 and C6 right next to

12V and 5V pins. C4 next to the 12V, pin 12 and C6

next to the 5V, pin 5.

Connect all grounds to the ground plane using direct

vias to the ground plane.

6) Place the controller IC such that the PWM output

drives, pins 9 and 11 are relatively short distance from

gates of Q1 and Q2.

Use large low inductance/low impedance plane to con-

nect the following connections either using component

side or the solder side.

7) Place resistor dividers, R7 & R8 close to pin 3, R12

& R13 (note 1) close to pin 14 and R14 and R15

(note 1) close to pin 20.

a) C3 to Q1 Drain

b) Q1 Source to Q2 Drain

c) Q2 drain to L2

Note 1: Although, the PWM controller does not re-

quire R12-15 resistors, and the feedback pins 3 and

14 can be directly connected to their respective out-

puts, they can be used to set the outputs slightly

higher to account for any output drop at the load due

to the trace resistance.

d) L2 to the output capacitors, C10

e) C10 to the slot 1

f) Input filter L1 to the C3

g) C9 to Q4 drain

h) C12 to the Q4 source

Connect the rest of the components using the shortest

connection possible.

Rev. 1.2

12/8/00

4-16


型号：	IRU3005CW-TRPBF
厂家：	Infineon
描述：	Switching Controller, 250kHz Switching Freq-Max, PDSO20, PLASTIC, SOIC-20 光电二极管
文件：	总14页 (文件大小：83K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRU3005CW-TRPBF [INFINEON]

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