IRU3007CW [INFINEON]
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRONOUS,ADJUSTABLE LDO AND 200mA ON-BOARD LDO; 5位可编程同步降压,非同步,可调LDO至200mA内置的LDO型号: | IRU3007CW |
厂家: | Infineon |
描述: | 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRONOUS,ADJUSTABLE LDO AND 200mA ON-BOARD LDO |
文件: | 总17页 (文件大小:101K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet No. PD94142
IRU3007
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRO-
NOUS, ADJUSTABLE LDO AND 200mA ON-BOARD LDO
FEATURES
DESCRIPTION
Provides Single Chip Solution for Vcore, GTL+,
Clock Supply & 3.3V Switcher On-Board
Second switcher provides simple control for the
on-board 3.3V supply
The IRU3007 controller IC is specifically designed to meet
Intel specification for Pentium IIä microprocessor ap-
plications as well as the next generation of P6 family
processors. The IRU3007 provides a single chip control-
ler IC for the Vcore, LDO controller for GTL+ and an
200mA On-Board LDO Regulator
Designed to meet Intel VRM 8.2 and 8.3 specifica- internal 200mA regulator for clock supply which are re-
tion for Pentium IIä
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear Regulator Controller On-Board for 1.5V
GTL+ supply
Loss-less Short Circuit Protection
quired for the Pentium II applications. It also contains a
switching controller to convert 5V to 3.3V regulator for
on-board applications that uses either AT type power
supply or is desired not to rely on the ATX power supply’s
3.3V output. These devices feature a patented topology
that in combination with a few external components, as
Synchronous Operation allows maximum efficiency shown in the typical application circuit, will provide in
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Minimum Part Count
Soft-Start
High current totem pole drivers for directly driving
the external Power MOSFETs
Power Good function monitors all outputs
Over-Voltage Protection circuitry protects the
switcher outputs and generates a fault output
Thermal Shutdown
excess of 14A of output current for an on-board DC/DC
converter while automatically providing the right output
voltage via the 5-bit internal DAC. The IRU3007 also fea-
tures, loss-less current sensing for both switchers by
using the RDS(on) of the high-side power MOSFET as the
sensing resistor, internal current limiting for the clock
supply, a Power Good window comparator that switches
its open collector output low when any one of the out-
puts is outside of a pre-programmed window. Other fea-
tures of the device are: Under-Voltage Lockout for both
5V and 12V supplies, an external programmable soft-
start function, programming the oscillator frequency via
an external resistor, Over-Voltage Protection (OVP) cir-
cuitry for both switcher outputs and an internal thermal
shutdown.
APPLICATIONS
Total Power Solution for Pentium II processor
application
TYPICAL APPLICATION
Note: Pentium II and Pentium Pro are trademarks of Intel Corp.
5V
SWITCHER2
CONTROL
SWITCHER1
CONTROL
V
OUT
2
3
V
OUT
1
4
IRU3007
LINEAR
CONTROL
LINEAR
REGULATOR
VOUT
VOUT
Figure 1 - Typical application of IRU3007.
PACKAGE ORDER INFORMATION
TA (°C)
DEVICE
PACKAGE
0 To 70
IRU3007CW
28-pin Plastic SOIC WB (W)
Rev. 2.1
08/20/02
www.irf.com
1
IRU3007
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage .................................................... 7V
V12 Supply Voltage .................................................. 20V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
PACKAGE INFORMATION
28-PIN WIDE BODY PLASTIC SOIC (W)
TOP VIEW
UGate2
Phase2
VID4
1
2
3
4
5
6
7
8
9
28 V12
27 UGate1
26
Phase1
VID3
25 LGate1
24 PGnd
VID2
23
VID1
OCSet1
VID0
22 VSEN1
21
20
PGood
OCSet2
Fb1
NC
Fb2 10
11
19 Fb3
18
V5
Gate3
SS 12
17 Gnd
Fault / Rt 13
16 VOUT4
14
15
VSEN2
Fb4
θJA =808C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer
to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX UNITS
Supply UVLO Section
UVLO Threshold-12V
UVLO Hysteresis-12V
UVLO Threshold-5V
UVLO Hysteresis-5V
Supply Current
Supply Ramping Up
10
V
V
V
V
0.4
4.3
0.3
Supply Ramping Up
Operating Supply Current
V12
V5
6
30
mA
Switching Controllers; Vcore (VOUT1) and I/O (VOUT2)
VID Section (Vcore only)
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
0.99Vs
Vs 1.01Vs
V
%
%
V
0.1
0.5
0.8
VID Input HI
2
V
VID Input Internal Pull-Up
Resistor to V5
27
KΩ
VFB2 Voltage
2
V
Oscillator Section (Internal)
KHz
Osc Frequency
Rt=Open
200
Rev. 2.1
08/20/02
www.irf.com
2
IRU3007
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX UNITS
Error Comparator Section
Input Bias Current
Input Offset Voltage
Delay to Output
2
+2
100
µA
mV
ns
-2
VDIFF=10mV
Current Limit Section
CS Threshold Set Current
CS Comp Offset Voltage
Hiccup Duty Cycle
200
10
µA
mV
%
-5
+5
CSS=0.1µF
Output Drivers Section
Rise Time
Fall Time
Dead Band Time Between
High Side and Synch Drive
(Vcore Switcher Only)
2.5V Regulator (VOUT4)
Reference Voltage
CL=3000pF
CL=3000pF
CL=3000pF
70
70
200
ns
ns
ns
VO4
TA=258C, VOUT4=Fb4
1.260
1.260
0.6
V
V
V
Reference Voltage
Dropout Voltage
IO=200mA
Load Regulation
Line Regulation
1mA<IO<200mA
3.1V<VI/O<4V, VO=2.5V
0.5
0.2
%
%
Input Bias Current
Output Current
Current Limit
Thermal Shutdown
1.5V Regulator (VOUT3)
Reference Voltage
Reference Voltage
2
2
µA
mA
mA
8C
200
300
145
VO3 TA=258C, Gate3=Fb3
1.260
1.260
V
V
µA
mA
Input Bias Current
Output Drive Current
Power Good Section
Core UV Lower Trip Point
Core UV Upper Trip Point
Core UV Hysteresis
Core OV Upper Trip Point
Core OV Lower Trip Point
Core OV Hysteresis
I/O UV lower trip point
I/O UV Upper Trip Point
Fb4 Lower Trip Point
Fb4 Upper Trip Point
Fb3 Lower Trip Point
Fb3 Upper Trip Point
Power Good Output LO
Power Good Output HI
Fault (Over-Voltage) Section
Core OV Upper Trip Point
Core OV Lower Trip Point
Soft-Start Section
Pull-Up Resistor to 5V
I/O OV Upper Trip Point
I/O OV Lower Trip Point
Fault Output HI
50
VSEN1 Ramping Down
VSEN1 Ramping Up
0.90Vs
0.92Vs
0.02Vs
1.10Vs
1.08Vs
0.02Vs
2.4
2.6
0.95
1.05
0.95
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VSEN1 Ramping Up
VSEN1 Ramping Down
VSEN2 Ramping Down
VSEN2 Ramping Up
Fb4 Ramping Down
Fb4 Ramping Up
Fb3 Ramping Down
Fb3 Ramping Up
RL=3mA
1.05
0.4
4.8
RL=5K Pull Up to 5V
VSEN1 Ramping Up
VSEN1 Ramping Down
1.17Vs
1.15Vs
V
V
OCSet=0V, Phase=5V
VSEN2 Ramping Up
VSEN2 Ramping Down
IO=3mA
23
4.3
4.2
10
KΩ
V
V
V
Rev. 2.1
08/20/02
www.irf.com
3
IRU3007
Note 1: Vs refers to the set point voltage given in Table 1
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
Table 1 - Set point voltage vs. VID codes
PIN DESCRIPTIONS
PIN#
PIN SYMBOL
PIN DESCRIPTION
1
2
UGate2
Phase2
Output driver for the high-side power MOSFET for the I/O supply.
This pin is connected to the Source of the power MOSFET for the I/O supply and it
provides the negative sensing for the internal current sensing circuitry.
This pin selects a range of output voltages for the DAC. When in the LO state the range
is 1.3V to 2.05V and when it switches to HI state the range is 2.0V to 3.5V. This pin is
TTL compatible that realizes a logic “1” as either HI or Open. When left open, this pin is
pulled up internally by a 27KΩ resistor to 5V supply.
3
VID4
4
5
6
7
8
9
VID3
VID2
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by
a 27KΩ resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by a
27KΩ resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that real-
izes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by a
27KΩ resistor to 5V supply.
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic “1” as either HI or Open. When left open, this pin is pulled up internally by
a 27KΩ resistor to 5V supply.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under voltage trip point. It also switches low when VSEN1 pin is more than
10% above the DAC voltage setting.
This pin is connected to the Drain of the power MOSFET of the I/O supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor pro-
grams the CS threshold depending on the RDS of the power MOSFET. An external ca-
pacitor is placed in parallel with the programming resistor to provide high frequency noise
filtering.
VID1
VID0
PGood
OCSet2
Rev. 2.1
08/20/02
www.irf.com
4
IRU3007
PIN#
PIN SYMBOL
PIN DESCRIPTION
10
Fb2
This pin provides the feedback for the non-synchronous switching regulator. A resistor
divider is connected from this pin to VOUT2 and ground that sets the output voltage. The
value of the resistor connected from VOUT2 to Fb2 must be less than 100Ω.
5V supply voltage. A high frequency capacitor (0.1 to 1µF) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the soft-start for the 2 switching regulators. An internal resistor charges
an external capacitor that is connected from 5V supply to this pin which ramps up the
outputs of the switching regulators, preventing the outputs from overshooting as well as
limiting the input current. The second function of the Soft-Start cap is to provide long off
time (HICCUP) for the synchronous MOSFET during current limiting.
11
12
V5
SS
13
Fault / Rt
This pin has dual function. It acts as an output of the OVP circuitry or it can be used to
program the frequency using an external resistor. When used as a fault detector, if any of
the switcher outputs exceed the OVP trip point, the Fault pin switches to 12V and the
soft-start cap is discharged. If the Fault pin is to be connected to any external circuitry,
it needs to be buffered as shown in the application circuit.
14
15
Fb4
VSEN2
This pin provides the feedback for the internal LDO regulator that its output is VOUT4.
This pin is connected to the output of the I/O switching regulator. It is an input that
provides sensing for the Under/Over-voltage circuitry for the I/O supply as well as the
power for the internal LDO regulator.
16
17
18
19
20
21
VOUT4
Gnd
Gate3
Fb3
NC
Fb1
This pin is the output of the internal LDO regulator.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Gate3.
No connection.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to VOUT1 and ground to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from VOUT1 to Fb1 must be less than 100Ω.
This pin is internally connected to the undervoltage and overvoltage comparators sensing
the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it
provides the positive sensing for the internal current sensing circuitry. An external resis-
tor programs the CS threshold depending on the RDS of the power MOSFET. An external
capacitor is placed in parallel with the programming resistor to provide high frequency
noise filtering.
22
23
VSEN1
OCSet1
24
PGnd
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor
(typically 1µF) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the Source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
25
26
LGate1
Phase1
27
28
UGate1
V12
Output driver for the high-side power MOSFET for the Core supply.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1µF) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for noise free
operation.
Rev. 2.1
08/20/02
www.irf.com
5
IRU3007
BLOCK DIAGRAM
4.3V
21
27
Fb1
Enable
V12
V12
Over
Voltage
Vset
Enable
UGate1
28
V12
UVLO
1.17Vset
2.5V
PWM
Control
11
V5
+
Vset
25
Slope
Comp
LGate1
7
VID0
Osc
6
VID1
26
23
2
Phase1
OCSet1
Phase2
OCSet2
5Bit
DAC
5
VID2
Over
Current
Soft
Start &
Fault
1.1Vset
4
VID3
Enable
3
VID4
Logic
9
200uA
22
VSEN1
13
1
Fault / Rt
UGate2
19
18
15
Fb3
0.9Vset
0.9V
V12
V12
V5
Slope
Comp
Gate3
PWM
Control
+
1.26V
24
17
PGnd
Gnd
V
SEN
2
2.0V
Enable
16
14
8
VOUT
4
10
12
Fb2
SS
Fb4
PGood
Figure 2 - Simplified block diagram of the IRU3007.
Rev. 2.1
08/20/02
www.irf.com
6
IRU3007
TYPICAL APPLICATION
R22
12V
L1
R12
C10
R9
C8
C5
C14
5V
C2
C3
OCSet2 V12 OCSet1
R10
R13
Q3
Q1
UGate1
Phase1
UGate2
Phase2
L2
L3
VOUT2
3.0V - 3.5V
VOUT1
1.8V - 3.5V
C16
C1
R14
C4
R1
Q4
C13
R15
LGate1
D1
R16
R21
PGnd
VSEN1
Fb1
VSEN2
Fb2
R2
R17
C15
U1
IRU3007
R19
R3
5V
C19
V5
PGood
PGood
Fault/Rt
Q2
Gate3
Fb3
R5
VOUT3
1.5V
VID0
VID1
VID2
VID3
VID4
C17
R6
VOUT4
2.5V
VOUT4
Fb4
C18
R7
R8
5V
SS
Gnd
C9
Figure 3 - Typical application of IRU3007 for an on-board DC-DC converter providing power
for the Vcore, GTL+, Clock supply as well as an on-board 3.3V I/O supply
for the Deschutes and the next generation processor applications.
Rev. 2.1
08/20/02
www.irf.com
7
IRU3007
IRU3007 APPLICATION PARTS LIST
Ref Desig Description
Qty
Part #
Manuf
Q1
Q2
Q3
Q4
D1
L1
MOSFET
1
IRL3103S, TO-263 package
IR
MOSFET
1
1
1
1
1
IRLR024, TO-252 package
IRL3103S, TO-263 package
IRL3103D1S, TO-263 package
MBRB1035, TO-263 package
L=1µH, 5052 core with 4 turns of
1.0mm wire
IR
MOSFET
IR
MOSFET with Schottky
Diode
IR
IR
Inductor
Micro Metal
L2
L3
Inductor
Inductor
1
1
L=4.7µH, 5052 core with 11 turns of
1.0mm wire
Micro Metal
Micro Metal
L=2.7µH, 5052B core with 7 turns of
1.2mm wire
C1
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
2
1
1
2
2
1
3
2
6
1
1
4
6MV1500GX, 1500µF, 6.3V
10MV470GX, 470µF, 10V
10MV1200GX, 1200µF, 10V
1000pF, 0603
Sanyo
Sanyo
Sanyo
C2
C3
C4, 13
C5, 10
C8
220pF, 0603
1µF, 0805
C9, 15, 19 Capacitor, Ceramic
1µF, 0603
C14
C16
C17
C18
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
10MV1200GX, 1200µF, 10V
6MV1500GX, 1500µF, 6.3V
6MV1000GX, 1000µF, 6.3V
6MV150GX, 150µF, 6.3V
4.7Ω, 5%, 1206
Sanyo
Sanyo
Sanyo
Sanyo
R1, 5, 13, Resistor
14
R2
Resistor
1
4
1
1
1
1
3
1
1
75Ω, 1%, 0603
100Ω, 1%, 0603
19.1Ω, 1%, 0603
1.5KΩ, 5%, 0603
10Ω, 5%, 1206
3.3KΩ, 5%, 0603
2.2KΩ, 1%, 0603
220KΩ, 1%, 0603
10Ω, 5%, 0603
R3, 6, 7, 8 Resistor
R5
Resistor
Resistor
Resistor
Resistor
R9
R10
R12
R16, 17, 21 Resistor
R19
R22
Resistor
Resistor
Rev. 2.1
08/20/02
www.irf.com
8
IRU3007
TYPICAL APPLICATION
(Dual Layout with HIP6019)
R22
12V
5V
L1
C5
R9
C8
R12
C10
C14
C2
C3
OCSet2
UGate2
V12 OCSet1
UGate1
R10
R13
Q3
Q4
Q1
L3
L2
VOUT2
3.0V - 3.5V
Phase2
Phase1
LGate1
VOUT1
1.8V - 3.5V
C16
C1
R14
C4
R1
C13
R15
D1
R16
R21
PGnd
VSEN1
VSEN2
Fb2
U1
Fb1
R2
R17
IRU3007
C15
R19
R11
C12
V5/Comp2
NC/Comp1
C6
R3
C11
R18
C19
R4
R5
C7
PGood
Fault/Rt
VID0
PGood
Q2
Gate3
Fb3
VOUT3
1.5V
C17
C18
R6
VID1
VID2
VOUT4
2.5V
VOUT4
Fb4
VID3
R7
R8
VID4
Gnd
SS
5V
C20
C9
Figure 4 - Typical application of IRU3007 in a dual layout with HIP6019 for an on-board DC-DC converter
providing power for the Vcore, GTL+, Clock supply as well as an on-board 3.3V I/O supply for the
Deschutes and the next generation processor application.
Components that need to be modified to make the dual layout work for HIP6019 and IRU3007:
Part #
HIP6019
IRU3007
R4
V
O
R11
O
S
R18
V
O
C6
V
O
C7
V
O
C9
O
V
C11
V
O
C12
V
O
C19
O
V
C20
V
O
S - Short
O - Open
V - See IR or Harris parts list for the value
Table 2 - Dual layout component table.
Rev. 2.1
08/20/02
www.irf.com
9
IRU3007
IRU3007 APPLICATION PARTS LIST
Dual Layout with HIP6019
Ref Desig Description
Qty
Part #
Manuf
Q1
Q2
Q3
Q4
D1
L1
MOSFET
1
IRL3103S, TO-263 package
IR
MOSFET
1
1
1
1
1
IRLR024, TO-252 package
IRL3103S, TO-263 package
IRL3103D1S, TO-263 package
MBRB1035, TO-263 package
L=1µH, 5052 core with 4 turns of
1.0 mm wire
IR
MOSFET
IR
MOSFET with Schottky
Diode
IR
IR
Inductor
Micro Metal
L2
L3
Inductor
Inductor
1
1
L=4.7µH, 5052 core with 11 turns of
1.0mm wire
Micro Metal
Micro Metal
L=2.7µH, 5052B core with 7 turns of
1.2mm wire
C1
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Ceramic
Capacitor, Ceramic
2
1
1
2
2
5
6MV1500GX, 1500µF, 6.3V
10MV470GX, 470µF, 10V
10MV1200GX, 1200µF, 10V
1000pF, 0603
Sanyo
Sanyo
Sanyo
C2
C3
C4, 13
C5, 10
220pF, 0603
C6,7,11,12 Capacitor, Ceramic
20
See Table 2, dual layout component
0603 × 5
C8
Capacitor, Ceramic
1
3
2
6
1
1
4
1µF, 0805
C9,15,19 Capacitor, Ceramic
1µF, 0603
C14
C16
C17
C18
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
Capacitor, Electrolytic
10MV1200GX, 1200µF, 10V
6MV1500GX, 1500µF, 6.3V
6MV1000GX, 1000µF, 6.3V
6MV150GX, 150µF, 6.3V
4.7Ω, 5%, 1206
Sanyo
Sanyo
Sanyo
Sanyo
R1,13,14 Resistor
15
R2
Resistor
1
4
2
75Ω, 1%, 0603
R3,6,7,8 Resistor
100Ω, 1%, 0603
See Table 2, dual layout component
0603 × 2
R4, 18
Resistor
R5
Resistor
Resistor
Resistor
Resistor
Resistor
1
1
1
1
1
3
1
1
19.1Ω, 1%, 0603
1.5KΩ, 5%, 0603
10Ω, 5%, 1206
R9
R10
R11
R12
0Ω, 0603
3.3KΩ, 5%, 0603
2.2KΩ, 1%, 0603
220KΩ, 1%, 0603
10Ω, 5%, 0603
R16,17,21 Resistor
R19
R22
Resistor
Resistor
Rev. 2.1
08/20/02
www.irf.com
10
IRU3007
APPLICATION INFORMATION
light load to full load. For example, if the total resistance
from the output capacitors to the Slot 1 and back to the
Gnd pin of the IRU3007 is 5mΩ and if the total ∆I, the
change from light load to full load is 14A, then the output
voltage measured at the top of the resistor divider which
is also connected to the output capacitors in this case,
must be set at half of the 70mV or 35mV higher than the
DAC voltage setting. This intentional voltage level shift-
ing during the load transient eases the requirement for
the output capacitor ESR at the cost of load regulation.
One can show that the new ESR requirement eases up
by half the total trace resistance. For example, if the
ESR requirement of the output capacitors without volt-
age level shifting must be 7mΩ then after level shifting
the new ESR will only need to be 8.5mΩ if the trace
resistance is 5mΩ (7+5/2=9.5). However, one must be
careful that the combined “voltage level shifting” and the
transient response is still within the maximum tolerance
of the Intel specification. To insure this, the maximum
trace resistance must be less than:
An example of how to calculate the components for the
application circuit is given below.
Assuming, two set of output conditions that this regula-
tor must meet for Vcore:
a) Vo=2.8V , Io=14.2A, ∆Vo=185mV, ∆Io=14.2A
b) Vo=2V , Io=14.2A, ∆Vo=140mV, ∆Io=14.2A
Also, the on-board 3.3V supply must be able to provide
10A load current and maintain less than ±5% total out-
put voltage variation.
The regulator design will be done such that it meets the
worst case requirement of each condition.
Output Capacitor Selection
Vcore
The first step is to select the output capacitor. This is
done primarily by selecting the maximum ESR value
that meets the transient voltage budget of the total ∆Vo
specification. Assuming that the regulators DC initial
accuracy plus the output ripple is 2% of the output volt-
age, then the maximum ESR of the output capacitor is
calculated as:
(Vspec - 0.02 × Vo - ∆Vo)
Rs ≤ 2 ×
∆I
Where :
Rs = Total maximum trace resistance allowed
Vspec = Intel total voltage spec
Vo = Output voltage
∆Vo = Output ripple voltage
∆I = load current step
100
14.2
ESR ≤
= 7mΩ
The Sanyo MVGX series is a good choice to achieve
both the price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typical.
Selecting 6 of these capacitors in parallel has an ESR
of » 6mΩ which achieves our low ESR goal.
For example, assuming:
Vspec = ±140mV = ±0.1V for 2V output
Vo = 2V
∆Vo = assume 10mV = 0.01V
∆I = 14.2A
Other type of Electrolytic capacitors from other manu-
facturers to consider are the Panasonic FA series or the
Nichicon PL series.
Then the Rs is calculated to be:
(0.140 - 0.02 × 2 - 0.01)
Rs £ 2 ×
= 12.6mΩ
3.3V supply
14.2
For the 3.3V supply, since there is not a fast transient
requirement, 2 of the 1500µF capacitors is sufficient.
However, if a resistor of this value is used, the maximum
power dissipated in the trace (or if an external resistor is
being used) must also be considered. For example if
Rs=12.6mΩ, the power dissipated is:
Reducing the Output Capacitors Using Voltage Level
Shifting Technique
The trace resistance or an external resistor from the output
of the switching regulator to the Slot 1 can be used to
the circuit advantage and possibly reduce the number of
output capacitors, by level shifting the DC regulation point
when transitioning from light load to full load and vice
versa. To accomplish this, the output of the regulator is
typically set about half the DC drop that results from
Io2×Rs = 14.22×12.6 = 2.54W
This is a lot of power to be dissipated in a system. So, if
the Rs=5mΩ, then the power dissipated is about 1W,
which is much more acceptable. If level shifting is not
implemented, then the maximum output capacitor ESR
was shown previously to be 7mΩ which translated to » 6
Rev. 2.1
08/20/02
www.irf.com
11
IRU3007
T = 1 / Fsw
of the 1500µF, 6MV1500GX type Sanyo capacitors. With
Rs=5mΩ, the maximum ESR becomes 9.5mΩ which is
equivalent to » 4 caps. Another important consideration
is that if a trace is being used to implement the resistor,
the power dissipated by the trace increases the case
temperature of the output capacitors which could seri-
ously affect the life span of the output capacitors.
Vsw = Vsync = Io×RDS
D » (Vo + Vsync) / (VIN - Vsw + Vsync)
TON = D×T
TOFF = T - TON
∆Ir = (Vo + Vsync)×TOFF / L
∆Vo = ∆Ir×ESR
Output Inductor Selection
The output inductance must be selected such that un- In our example for Vo = 2.8V and 14.2 A load, assuming
der low line and the maximum output voltage condition, IRL3103 MOSFET for both switches with maximum on
the inductor current slope times the output capacitor resistanceof19mΩ, we have:
ESR is ramping up faster than the capacitor voltage is
T = 1 / 200000 = 5µs
drooping during a load current step. However, if the in-
Vsw = Vsync = 14.2×0.019 = 0.27V
D » (2.8 + 0.27) / (5 - 0.27 + 0.27) = 0.61
TON = 0.61×5 = 3.1µs
ductor is made too small, the output ripple current and
ripple voltage will become too large. One solution to bring
the ripple current down is to increase the switching fre-
quency, however that will be at the cost of reduced effi-
ciency and higher system cost. The following set of for-
mulas are derived to achieve optimum performance with-
out many design iterations.
TOFF = 5 - 3.1 = 1.9µs
∆Ir = (2.8 + 0.27)×1.9 / 3 = 1.94A
∆Vo = 1.94×0.006 = 0.011V = 11mV
The maximum output inductance is calculated using the Power Component Selection
following equation:
Vcore
Assuming IRL3103 MOSFETs as power components,
we will calculate the maximum power dissipation as fol-
lows:
(VIN(MIN) - Vo(MAX))
L = ESR × C ×
(2 × ∆I)
Where:
VIN(MIN) = Minimum input voltage
For Vo = 2.8V and ∆I = 14.2A, we get:
For high side switch the maximum power dissipation
happens at maximum Vo and maximum duty cycle.
(4.75 - 2.8)
(2 × 14.2)
L = 0.006 × 9000 ×
= 3.7µH
DMAX » (2.8 + 0.27) / (4.75 - 0.27 + 0.27) = 0.65
PDH = DMAX×Io2×RDS(MAX)
PDH = 0.65×14.22×0.029 = 3.8W
Assuming that the programmed switching frequency is
set at 200KHz, an inductor is designed using the
Micrometals’ powder iron core material. The summary
of the design is outlined below:
RDS(MAX)=Maximum RDS(ON) of the MOSFET at 1258C
For synch MOSFET, maximum power dissipation hap-
The selected core material is Powder Iron, the selected pens at minimum Vo and minimum duty cycle.
core is T50-52D from Micro Metal wound with 8 turns of
DMIN » (2 + 0.27) / (5.25 - 0.27 + 0.27) = 0.43
PDS = (1 - DMIN)×Io2×RDS(MAX)
#16 AWG wire, resulting in 3µH inductance with » 3 mΩ
of DC resistance.
PDS = (1 - 0.43)×14.22 ×0.029 = 3.33W
Assuming L=3µH and Fsw=200KHz (switching fre-
quency), the inductor ripple current and the output ripple 3.3V Supply
voltage is calculated using the following set of equations: Again, for high side switch the maximum power dissipa-
tion happens at maximum Vo and maximum duty cycle.
T º Switching Period
D º Duty Cycle
Vsw º High-side MOSFET ON Voltage
RDS º MOSFET On-Resistance
The duty cycle equation for non synchronous replaces
the forward voltage of the diode with the Synch MOSFET
on voltage. In equations below:
Vsync º Synchronous MOSFET ON Voltage
Vf = 0.5V
∆Ir º Inductor Ripple Current
DMAX » (3.3 + 0.5) / (4.75 - 0.27 + 0.5) = 0.76
∆Vo º Output Ripple Voltage
Rev. 2.1
08/20/02
www.irf.com
12
IRU3007
PDH = DMAX×Io2×RDS(MAX)
PDH = 0.76×102×0.029 = 2.21W
To select the heat sink for the LDO MOSFET the first
step is to calculate the maximum power dissipation of
the device and then follow the same procedure as for the
switcher.
RDS(MAX) = Maximum RDS(ON) of the MOSFET at 1258C
For diode, the maximum power dissipation happens at
minimum Vo and minimum duty cycle.
Where:
PD = Power Dissipation of the Linear Regulator
IL = Linear Regulator Load Current
DMIN » (3.3 + 0.5) / (5.25 - 0.27 + 0.5) = 0.69
PDD = (1 - DMIN)×Io×Vf
For the 1.5V and 2A load:
PD = (VIN - Vo)×IL
PDD = (1 - 0.69)×10×0.5 = 1.55W
Switcher Current Limit Protection
The IRU3007 uses the MOSFET RDS(ON) as the sensing
PD = (3.3 - 1.5)×2 = 3.6W
resistor to sense the MOSFET current and compares to Assuming TJ(MAX) = 1258C:
a programmed voltage which is set externally via a re-
sistor (Rcs) placed between the drain of the MOSFET
and the “CS+” terminal of the IC as shown in the appli-
cation circuit.
Ts = TJ - PD×(θJC + θcs)
Ts = 125 - 3.6×(1.8 + 0.05) = 1188C
With the maximum heat sink temperature calculated in
the previous step, the heat-sink-to-air thermal resistance
For example, if the desired current limit point is set to (θSA) is calculated as follows:
be 22A for the synchronous and 16A for the non syn-
chronous, and from our previous selection, the maxi- Assuming TA = 358C:
mum MOSFET RDS(ON)=19mW, then the current sense
resistor Rcs is calculated as:
∆T = Ts - TA = 118 - 35 = 838C
Temperature Rise Above Ambient
θSA = ∆T / PD = 83 / 3.6 = 238C/W
Vcore
The same heat sink as the one selected for the switcher
MOSFETs is also suitable for the 1.5V regulator.
Vcs = ICL×RDS = 22×0.019 = 0.418V
Rcs = Vcs / IB = (0.418V) / (200µA) = 2.1KΩ
Where:
2.5V Clock Supply
IB=200µA is the internal current setting of the The IRU3007 provides a complete 2.5V regulator with a
IRU3007
minimum of 200mA current capability. The internal regu-
lator has short circuit protection with internal thermal
shutdown.
3.3V supply
Vcs = ICL×RDS = 16×0.019 = 0.3V
Rcs = Vcs / IB = (0.3V) / (200µA) = 1.50KΩ
1.5V and 2.5V Supply Resistor Divider Selection
Since the internal voltage reference for the linear regula-
1.5V, GTL+ Supply LDO Power MOSFET Selection tors is set at 1.26V for IRU3007, there is a need to use
The first step in selecting the power MOSFET for the external resistor dividers to step up the voltage. The re-
1.5V linear regulator is to select its maximum RDS(ON) of sistor dividers are selected using the following equations:
the pass transistor based on the input to output Dropout
Vo = (1 + Rt / RB)×VREF
voltage and the maximum load current.
Where:
Rt = Top resistor divider
RB = Bottom resistor divider
For Vo = 1.5V, VIN = 3.3V and IL = 2A:
RDS(MAX) = (VIN - Vo) / IL = (3.3 - 1.5) / 2 = 0.9Ω
Note: Since the MOSFETs RDS(ON) increases with tem-
perature, this number must be divided by » 1.5, in order
VREF = 1.26V typical
to find the RDS(ON) max at room temperature. The Motorola For 1.5V supply
MTP3055VL has a maximum of 0.18Ω RDS(ON) at room Assuming RB = 1KΩ:
temperature, which meets our requirement.
Rt = RB×[(Vo / VREF) - 1]
Rt = 1×[(1.5 / 1.26) - 1] = 191Ω
Rev. 2.1
08/20/02
www.irf.com
13
IRU3007
For 2.5V supply
Assuming RB = 1.02KΩ:
The bottom resistor, R3 is calculated as follows:
R3 = R2×[2 / (Vo - 2)] (Ω)
Rt = RB×[(Vo / VREF) - 1]
R3 = 75×[2 / (3.5 - 2)] = 100Ω, 1%
Rt = 1.02×[(2.5 / 1.26) - 1] = 1KΩ
Note: The value of the top resistor, R2 must not exceed
100Ω.
Switcher Output Voltage Adjust
Vcore
As it was discussed earlier, the trace resistance from Soft-Start Capacitor Selection
the output of the switching regulator to the Slot 1 can be The soft-start capacitor must be selected such that dur-
used to the circuit advantage and possibly reduce the ing the start up when the output capacitors are charging
number of output capacitors, by level shifting the DC up, the peak inductor current does not reach the current
regulation point when transitioning from light load to full limit threshold. A minimum of 1µF capacitor insures this
load and vice versa. To account for the DC drop, the for most applications. An internal 10µA current source
output of the regulator is typically set about half the DC charges the soft-start capacitor which slowly ramps up
drop that results from light load to full load. For example, the inverting input of the PWM comparator Vfb3. This
if the total resistance from the output capacitors to the insures the output voltage to ramp at the same rate as
Slot 1 and back to the Gnd pin of the IRU3007 is 5mΩ the soft-start cap thereby limiting the input current. For
and if the total ∆I, the change from light load to full load example, with 1µF and the 10µA internal current source
is 14A, then the output voltage measured at the top of the ramp up rate is (∆V/∆t)=I/C=1V/100ms. Assuming
the resistor divider which is also connected to the out- that the output capacitance is 9000µF, the maximum
put capacitors in this case, must be set at half of the start up current will be:
70mV or 35mV higher than the DAC voltage setting. To
do this, the top resistor of the resistor divider (R12 in the
I = 9000µF × (1V / 100ms) = 0.09A
application circuit) is set at 100Ω, and the R19 is calcu- Input Filter
lated. For example, if DAC voltage setting is for 2.8V It is highly recommended to place an inductor between
and the desired output under light load is 2.835V, then the system 5V supply and the input capacitors of the
R19 is calculated using the following formula:
switching regulator to isolate the 5V supply from the
switching noise that occurs during the turn on and off of
the switching components. Typically an inductor in the
range of 1 to 3µH will be sufficient in this type of appli-
cation.
R19 = 100×[VDAC / (Vo - 1.004×VDAC)] (Ω)
R19 = 100×[2.8 / (2.835 - 1.004×2.800)] = 11.76KΩ
Select 11.8KΩ, 1%
Note:The value of the top resistor must not exceed 100Ω. External Shutdown
The bottom resistor can then be adjusted to raise the The best way to shutdown the IRU3007 is to pull down
output voltage.
on the soft-start pin using an external small signal tran-
sistor such as 2N3904 or 2N7002 small signal MOSFET.
This allows slow ramp up of the output, the same as the
3.3V supply
The loop gain for the non-synchronous switching regula- power up.
tor is intentionally set low to take advantage of the level
shifting technique to reduce the number of output ca- Layout Considerations
pacitors. Typically there is a 1% drop in the output volt- Switching regulators require careful attention to the lay-
age from light load (discontinuous conduction mode) to out of the components, specifically power components
full load (continuous conduction mode) in the 3.3V sup- since they switch large currents. These switching com-
ply. To account for this, the output voltage is set at 3.5V ponents can create large amount of voltage spikes and
typically. The same procedure as for the synchronous is high frequency harmonics if some of the critical compo-
applied to the non-synch with the exception that the in- nents are far away from each other and are connected
ternal voltage reference of this regulator is internally set with inductive traces. The following is a guideline of how
at 2V. The following is the set of equations to use for the to place the critical components and the connections
output voltage setting for the non-synchronous assum- between them in order to minimize the above issues.
ing the Vo=3.5V and R2=75Ω (R2 is the top resistor in
the application circuit).
Rev. 2.1
08/20/02
www.irf.com
14
IRU3007
Start the layout by first placing the power components: 9) Place R12 and C10 close to pin 23 and R9 and C5
close to pin 9.
1) Place the input capacitors C3 and C14 and the high
side MOSFETs, Q1 and Q3 as close to their respec- 10) Place C9 close to pin 12
tive input caps as possible.
Component connections:
2) Place the synchronous MOSFET, Q2 and the Q3 as
close to each other as possible with the intention Note: It is extremely important that no data bus should
that the source of Q3 and drain of the Q4 has the be passing through the switching regulator section spe-
shortest length. Repeat this for the Q1 and D1 for the cifically close to the fast transition nodes such as PWM
non-synchronous.
drives or the inductor voltage.
3) Place the snubber R15 and C13 between Q4 and Q3. Using the 4 layer board, dedicate one layer to ground,
Repeat this for R1 and C4 with respect to the Q1 and another layer as the power layer for the 5V, 3.3V, Vcore,
D1 for the non-synchronous.
1.5V and if it is possible, for the 2.5V.
4) Place the output inductor , L3 and the output capaci- Connect all grounds to the ground plane using direct
tors, C16 between the MOSFET and the load with vias to the ground plane.
output capacitors distributed along the slot 1 and
close to it. Repeat this for L2 with respect to the C1 Use large low inductance/low impedance plane to con-
for the non-synchronous.
nect the following connections either using component
side or the solder side.
5) Place the bypass capacitors, C8 and C19 right next
to 12V and 5V pins. C8 next to the 12V, pin 28 and
C19 next to the 5V, pin 11.
a) C14 to Q3 Drain and C3 to Q1 drain
b) Q3 Source to Q4 Drain and Q1 Source to D1
cathode
6) Place the IRU3007 such that the pwm output drives,
pins 27 and 25 are relatively short distance from gates
of Q3 and Q4. The non-synch MOSFET must also
be situated such that the distance from its gate to
the pin 1 of the IRU3007 is also relatively short.
c) Q4 drain to L3 and D1 cathode to L2
d) L3 to the output capacitors, C16 and L2 to the
output capacitors, C1
e) C16 to the load, slot 1
f) Input filter L1 to the C16 and C3
g) C1 to Q2 drain
7) Place all resistor dividers close to their respective
feedback pins.
h) C17 to the Q2 source
I) A minimum of 0.2 inch width trace from the C18
capacitor to pin 16
8) Place the 2.5V output capacitor, C18 close to the pin
16 of the IC and the 1.5V output capacitor, C17 close Connect the rest of the components using the shortest
to the Q2 MOSFET.
connection possible.
Note: It is better to place the 1.5V linear regulator
components close to the IRU3007 and then run a
trace from the output of the regulator to the load.
However, if this is not possible then the trace from
the linear drive output pin, pin 18 must be run away
from any high frequency data signals.
It is critical, to place high frequency ceramic capaci-
tors close to the clock chip and termination resistors
to provide local bypassing.
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 2.1
08/20/02
www.irf.com
15
IRU3007
(W) SOIC Package
28-Pin Surface Mount, Wide Body
H
A
B
C
R
E
DETAIL-A
L
PIN NO. 1
D
0.51± 0.020 x 458
DETAIL-A
I
K
F
T
G
J
SYMBOL
28-PIN
MIN MAX
A
B
C
D
E
F
G
I
17.73 17.93
1.27 BSC
0.66 REF
0.36
7.40
2.44
0.10
0.23
0.46
7.60
2.64
0.30
0.32
J
10.11 10.51
K
L
08
88
0.51
0.63
2.44
1.01
0.89
2.64
R
T
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 2.1
08/20/02
www.irf.com
16
IRU3007
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
W
SOIC, Wide Body
28
27
1000
Fig A
1
1
1
Feed Direction
Figure A
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 2.1
08/20/02
www.irf.com
17
相关型号:
IRU3007CWPBF
Dual Switching Controller, 200kHz Switching Freq-Max, PDSO28, PLASTIC, SOIC-28
INFINEON
IRU3013
VRM 8.5 COMPATIBLE 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH TRIPLE LDO CONTROLLER
INFINEON
IRU3013CQ
VRM 8.5 COMPATIBLE 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH TRIPLE LDO CONTROLLER
INFINEON
IRU3013CW
VRM 8.5 COMPATIBLE 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC WITH TRIPLE LDO CONTROLLER
INFINEON
©2020 ICPDF网 联系我们和版权申明