IRU3011_技术文档

Data Sheet No. PD94143

IRU3011

5-BIT PROGRAMMABLE SYNCHRONOUS BUCK

CONTROLLER IC

FEATURES

DESCRIPTION

The IRU3011 controller IC is specifically designed to meet

Dual Layout compatible with HIP6004A

Designed to meet Intel specification of VRM8.4 for Intel specification for latest Pentium IIIä microproces-

Pentium IIIä sor applications as well as the next generation P6 fam-

On-Board DAC programs the output voltage from ily processors. These products feature a patented topol-

1.3V to 3.5V. The IRU3011 remains on for VID code ogy that in combination with a few external components

of (11111).

Loss-less Short Circuit Protection

as shown in the typical application circuit,will provide in

excess of 20A of output current for an on-board DC/DC

Synchronous operation allows maximum efficiency converter while automatically providing the right output

Patented architecture allows fixed frequency

operation as well as 100% duty cycle during

dynamic load

Over-Voltage Protection Output

Soft-Start

voltage via the 5-bit internal DAC. These devices also

features, loss less current sensing by using the RDS(ON)

of the high side Power MOSFET as the sensing resis-

tor, a Power Good window comparator that switches its

open collector output low when the output is outside of a

High current totem pole driver for direct driving of the ±10% window and an Over-Voltage Protection output.

external power MOSFET

Power Good Function

Other features of the device are: Under-voltage lockout

for both 5V and 12V supplies, an external programmable

soft-start function as well as programming the oscillator

frequency by using an external capacitor.

APPLICATIONS

Pentium III & Pentium IIä processor DC to DC

converter application

Low Cost Pentium with AGP

TYPICAL APPLICATION

Note:Pentium II and Pentium III are trade marks of Intel Corp.

5V

VOUT

L1

L2

Q1

Q2

(1.3V - 3.5V)

C5

R1

C8

R4

C1

C3

C10

R2

R3

C6

C11

R7

C4

D1

R9

12V

V12

CS+

HDrv

NC/

Boot

CS-

LDrv

Gnd

NC/Sen

VFB

C12

NC/Gnd

C13

R5

R8

IRU3011

SS

D4

V5/Comp

OVP PGd

C2

D3

D2

D1

D0

Ct/Rt

C9

VID4

C7

R6

VID3

VID2

VID1

VID0

Power Good

OVP

C14

Figure 1 - Typical application of the IRU3011.

PACKAGE ORDER INFORMATION

TA (8C)

DEVICE

PACKAGE

VID VOLTAGE RANGE

0 To 70

IRU3011CW

20-Pin Plastic SOIC WB (W)

1.3V to 3.5V

Rev. 1.6

08/20/02

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1

IRU3011

ABSOLUTE MAXIMUM RATINGS

V5 Supply Voltage .................................................... 7V

V12 Supply Voltage .................................................. 20V

Storage Temperature Range ...................................... -65°C To 150°C

Operating Junction Temperature Range ...................... 0°C To 125°C

PACKAGE INFORMATION

20-PIN WIDE BODY PLASTIC SOIC (W)

TOP VIEW

NC

CS+

SS

D0

1

2

20 Ct

19

18

17

16

15

14

13

12

11

OVP

V12

LDrv

Gnd

NC

3

4

5

D1

6

D2

7

D3

HDrv

CS-

PGd

NC

8

D4

9

V5

10

VFB

θJA =858C/W

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over V12=12V, V5=5V and TA=0 to 70°C. Typical values refer

to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient

temperature.

PARAMETER

SYM

TEST CONDITION

MIN

TYP

MAX

UNITS

VID Section

DAC Output Voltage (Note 1)

DAC Output Line Regulation

DAC Output Temp Variation

VID Input LO

0.99Vs

Vs

1.01Vs

0.1

V

%

V

0.5

0.4

VID Input HI

2

V

VID Input Internal Pull-Up

Resistor to V5

27

KΩ

Power Good Section

Under-Voltage lower trip point

Under-Voltage upper trip point

UV Hysterises

VOUT Ramping Down

VOUT Ramping Up

0.89Vs 0.90Vs 0.91Vs

0.92Vs

0.015Vs 0.02Vs 0.025Vs

V

Over-Voltage upper trip point

Over-Voltage lower trip point

OV Hysteresis

VOUT Ramping Up

VOUT Ramping Down

1.09Vs 1.10Vs

1.08Vs

1.11Vs

0.015Vs 0.02Vs 0.025Vs

Power Good Output LO

Power Good Output HI

Soft-Start Section

RL=3mA

RL=5K Pull-Up to 5V

0.4

4.8

Soft-Start Current

CS+=0V, CS-=5V

10

µA

Rev. 1.6

08/20/02

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IRU3011

PARAMETER

SYM

TEST CONDITION

Supply Ramping Up

MIN

TYP

MAX

UNITS

UVLO Section

UVLO Threshold-12V

UVLO Hysteresis-12V

UVLO Threshold-5V

UVLO Hysteresis-5V

Error Comparator Section

Input Bias Current

9.2

0.3

4.1

0.2

10

10.8

0.5

4.5

0.4

V

0.4

4.3

0.3

2

+2

100

µA

mV

ns

Input Offset Voltage

Delay to Output

-2

VDIFF=10mV

Current Limit Section

CS Threshold Set Current

CS Comp Offset Voltage

Hiccup Duty Cycle

Supply Current

160

-5

200

240

+5

2

µA

mV

%

Css=0.1µF

Operating Supply Current

CL=3000pF:

V5

20

14

mA

V12

Output Drivers Section

Rise Time

Fall Time

Dead Band Time

Oscillator Section

Osc Frequency

Osc Valley

CL=3000pF

70

200

100

130

300

ns

100

190

Ct=150pF

220

V5

250

0.2

KHz

V

Osc Peak

V

Over-Voltage Section

OVP Drive Current

mA

Note 1: Vs refers to the set point voltage given in Table 1.

D4

0

D3

1

0

D2

1

0

1

0

D1

1

0

1

0

1

0

1

0

D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Vs

D4

1

D3

1

0

D2

D1

1

0

1

0

1

0

1

0

D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Vs

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

1

0

1

0

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Table 1 - Set point voltage vs. VID codes.

Rev. 1.6

08/20/02

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IRU3011

PIN DESCRIPTIONS

PIN#

PIN SYMBOL

PIN DESCRIPTION

1

2

NC

CS+

No connection.

This pin is connected to the Drain of the power MOSFET of the Core supply and it

provides the positive sensing for the internal current sensing circuitry. An external resis-

tor programs the CS threshold depending on the RDS of the power MOSFET. An external

capacitor is placed in parallel with the programming resistor to provide high frequency

noise filtering.

3

SS

This pin provides the soft-start for the switching regulator. An internal current source

charges an external capacitor that is connected from this pin to the ground which ramps

up the outputs of the switching regulator, preventing the outputs from overshooting as

well as limiting the input current. The second function of the Soft-Start cap is to provide

long off time for the synchronous MOSFET or the Catch diode (HICCUP) during current

limiting.

4

5

6

7

D0

D1

D2

D3

LSB input to the DAC that programs the output voltage. This pin can be pulled up exter-

nally by a 10K resistor to either 3.3V or 5V supply.

Input to the DAC that programs the output voltage. This pin can be pulled-up externally

by a 10KΩ resistor to either 3.3V or 5V supply.

Input to the DAC that programs the output voltage. This pin can be pulled-up externally

by a 10K resistor to either 3.3V or 5V supply.

MSB input to the DAC that programs the output voltage. This pin can be pulled-up exter-

nally by a 10K resistor to either 3.3V or 5V supply.

8

9

10

D4

V5

VFB

This pin selects a range of output voltages for the DAC.

5V supply voltage.

This pin is connected directly to the output of the Core supply to provide feedback to the

Error comparator.

11

12

NC

PGd

No connection.

This pin is an open collector output that switches LO when the output of the converter is

not within ±10% (typ) of the nominal output voltage. When PGd pin switches LO the

saturation voltage is less than 0.4V at 3mA.

13

CS-

This pin is connected to the Source of the power MOSFET for the Core supply and it

provides the negative sensing for the internal current sensing circuitry.

Output driver for the high side power MOSFET.

14

15

16

HDrv

NC

Gnd

No connection.

This pin serves as the ground pin and must be connected directly to the ground plane. A

high frequency capacitor (0.1 to 1µF) must be connected from V5 and V12 pins to this

pin for noise free operation.

17

18

LDrv

V12

Output driver for the synchronous power MOSFET.

This pin is connected to the 12 V supply and serves as the power Vcc pin for the output

drivers. A high frequency capacitor (0.1 to 1µF) must be connected directly from this pin

to ground pin in order to supply the peak current to the power MOSFET during the

transitions.

19

20

OVP

Ct

Over-voltage comparator output.

This pin programs the oscillator frequency in the range of 50KHz to 500KHz with an

external capacitor connected from this pin to the ground.

Rev. 1.6

08/20/02

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IRU3011

BLOCK DIAGRAM

10

14

FB

V

Enable

V12

Vset

Enable

HDrv

18

V12

UVLO

9

PWM

Control

V5

+

Vset

Enable

17

Slope

Comp

LDrv

4

5

6

7

8

D0

D1

D2

D3

D4

Osc

5Bit

DAC,

Ctrl

13

2

CS-

Over

Current

Soft

Start &

Fault

CS+

Logic

200uA

Logic

Enable

20

3

Ct

SS

1.18Vset

1.1Vset

19

16

12

OVP

Gnd

PGd

0.9Vset

Figure 2 - Simplified block diagram of the IRU3011.

Rev. 1.6

08/20/02

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IRU3011

TYPICAL APPLICATION

Synchronous Operation

(Dual Layout with HIP6004B)

L1

L2

Q1

5V

Vcore

R11

C15

R10

R 1

C 5

C 1

C 8

Q2

C 3

C10

R 4

R 2

R 3

C 6

C11

R 9

D 1

C 4

R13

R 7

12V

C12

V12

CS+

HDrv

NC/

CS-

LDrv

Gnd NC/Sen

V FB

Boot

NC/Gnd

C13

R12

R 5

R 8

IRU3011

SS

D 4

V5/Comp

D 3

D 2

D 1

D 0

Ct/Rt

O V P

PGd

C 2

C 9

Vcc3

C 7

VID4

R 6

VID3

VID2

VID1

VID0

Power Good

C14

Figure 3 - Typical application of IRU3011 in an on board DC-DC converter

providing the Core supply for microprocessor.

Part #

R5

R7

V

R8

V

R9

V

C4

V

C7

O

C9

O

C11

V

C12

V

C13

V

D1

V

HIP6004B

IRU3011

O

S

O

V

O

V

O

S - Short

O - Open

V - See IR or Harris parts list for the value

Table 2 - Components that need to be modified to make

the dual layout work for IRU3011and HIP6004B.

Rev. 1.6

08/20/02

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IRU3011

IRU3011 and HIP6004B Dual Layout Parts List

Ref Desig Description

Qty

Part #

Manuf

Q1

Q2

L1

MOSFET

Inductor

1

IRL3103s, TO-263 package

IR

1

IRL3103D1S, TO-263 package

L=1µH, 5052 core with 4 turns of

1.0mm wire

IR

Micro Metal

L2

Inductor

1

L=2.7µH, 5052B core with 7 turns of

1.2mm wire

Micro Metal

Sanyo

C1

Capacitor, Electrolytic

Capacitor, Ceramic

Capacitor, Electrolytic

Capacitor, Ceramic

Capacitor, Electrolytic

Capacitor, Ceramic

Resistor

1

2

1

6

1

3

1

10MV470GX, 470µF, 10V

1µF, 0603

C2, 9

C3

10MV1200GX, 1200µF, 10V

220pF, 0603

Sanyo

C5

C6

1µF, 0805

C7

150pF, 0603

C8

1000pF, 0603

C10

C14

C15

R1

6MV1500GX, 1500µF, 6.3V

0.1µF, 0603

Sanyo

4.7µF, 1206

3.3KΩ, 5%, 0603

4.7Ω, 5%, 1206

R2, 3, 4

R5

Resistor

0Ω, 0603

R6

Resistor

10KΩ, 5%, 0603

100Ω, 1%, 0603

R9

Resistor

R10

R11

R12

R13

Resistor

220Ω, 1%, 0603

Resistor

330Ω, 1%, 0603

Resistor

22KΩ, 1%, 0603

10Ω, 5%, 0603

Resistor

Note 1: R10, R11, C15, R9, and R12 set the Vcore 2% higher for level shift to reduce CPU transient voltage.

Rev. 1.6

08/20/02

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IRU3011

APPLICATION INFORMATION

An example of how to calculate the components for the This intentional voltage level shifting during the load tran-

application circuit is given below.

sient eases the requirement for the output capacitor ESR

at the cost of load regulation. One can show that the

Assuming, two sets of output conditions that this regu- new ESR requirement eases up by half the total trace

lator must meet,

a) Vo=2.8V, Io=14.2A, ∆Vo=185mV, ∆Io=14.2A

b) Vo=2V, Io=14.2A, ∆Vo=140mV, ∆Io=14.2A

resistance. For example, if the ESR requirement of the

output capacitors without voltage level shifting must be

7mΩ then after level shifting the new ESR will only need

to be 8.5mΩ if the trace resistance is 5mΩ (7 + 5/2=9.5).

the regulator design will be done such that it meets the However, one must be careful that the combined “volt-

worst case requirement of each condition.

age level shifting” and the transient response is still within

the maximum tolerance of the Intel specification. To in-

sure this, the maximum trace resistance must be less

Output Capacitor Selection

The first step is to select the output capacitor. This is than:

done primarily by selecting the maximum ESR value

thatmeetsthetransientvoltagebudgetofthetotal∆Vo

specification. Assuming that the regulators DC initial

accuracy plus the output ripple is 2% of the output volt-

age, then the maximum ESR of the output capacitor is

calculated as:

Rs ≤ 2×(Vspec - 0.02×Vo - ∆Vo) / ∆I

Where :

Rs = Total maximum trace resistance allowed

Vspec = Intel total voltage spec

Vo = Output voltage

∆Vo = Output ripple voltage

∆I = load current step

100

14.2

ESR ≤

= 7mΩ

The Sanyo MVGX series is a good choice to achieve For example, assuming:

both the price and performance goals. The 6MV1500GX,

1500µF, 6.3V has an ESR of less than 36mΩ typical.

Selecting 6 of these capacitors in parallel has an ESR

of » 6mΩ which achieves our low ESR goal.

Vspec = ±140mV = ±0.1V for 2V output

Vo = 2V

∆Vo = assume 10mV = 0.01V

∆I = 14.2A

Other type of electrolytic capacitors from other manu- Then the Rs is calculated to be:

facturers to consider are the Panasonic FA series or the

Rs ≤ 2×(0.140 - 0.02×2 - 0.01) / 14.2 = 12.6mΩ

Nichicon PL series.

However, if a resistor of this value is used, the maximum

Reducing the Output Capacitors Using Voltage Level power dissipated in the trace (or if an external resistor is

Shifting Technique being used) must also be considered. For example if

The trace resistance or an external resistor from the output Rs=12.6mΩ, the power dissipated is:

of the switching regulator to the Slot 1 can be used to

the circuit advantage and possibly reduce the number of

Io²×Rs = 14.2²×12.6 = 2.54W

output capacitors, by level shifting the DC regulation point This is a lot of power to be dissipated in a system. So, if

when transitioning from light load to full load and vice the Rs=5mΩ, then the power dissipated is about 1W

versa. To accomplish this, the output of the regulator is which is much more acceptable. If level shifting is not

typically set about half the DC drop that results from implemented, then the maximum output capacitor ESR

light load to full load. For example, if the total resistance was shown previously to be 7mΩ which translated to » 6

from the output capacitors to the Slot 1 and back to the of the 1500µF, 6MV1500GX type Sanyo capacitors. With

Gnd pin of the device is 5mΩ and if the total ∆I, the Rs=5mΩ, the maximum ESR becomes 9.5mΩ which is

change from light load to full load is 14A, then the output equivalent to » 4 caps. Another important consideration

voltage measured at the top of the resistor divider which is that if a trace is being used to implement the resistor,

is also connected to the output capacitors in this case, the power dissipated by the trace increases the case

must be set at half of the 70mV or 35mV higher than the temperature of the output capacitors which could seri-

DAC voltage setting.

ously effect the life time of the output capacitors.

Rev. 1.6

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IRU3011

Output Inductor Selection

In our example for Vo=2.8V and 14.2A load, assuming

The output inductance must be selected such that un- IRL3103 MOSFET for both switches with maximum on

der low line and the maximum output voltage condition, resistance 0f 19mΩ, we have:

the inductor current slope times the output capacitor

T = 1 / 200000 = 5µs

Vsw = Vsync = 14.2×0.019 = 0.27V

D @ (2.8 + 0.27) / (5 - 0.27 + 0.27) = 0.61

ESR is ramping up faster than the capacitor voltage is

drooping during a load current step. However, if the in-

ductor is too small, the output ripple current and ripple

TON = 0.61×5 = 3.1µs

TOFF = 5 - 3.1 = 1.9µs

∆Ir = (2.8 + 0.27)×1.9 / 3 = 1.94A

∆Vo = 1.94×0.006 = 0.011V = 11mV

voltage become too large. One solution to bring the ripple

current down is to increase the switching frequency,

however, that will be at the cost of reduced efficiency

and higher system cost. The following set of formulas

are derived to achieve the optimum performance without

many design iterations.

Power Component Selection

Assuming IRL3103 MOSFETs as power components,

The maximum output inductance is calculated using the we will calculate the maximum power dissipation as fol-

following equation:

lows:

L = ESR×C×(VIN(MIN) - Vo(MAX)) / (2×∆I)

For high-side switch the maximum power dissipation

happens at maximum Vo and maximum duty cycle.

Where:

VIN(MIN) = Minimum input voltage

For Vo=2.8V and ∆I=14.2A

DMAX @ (2.8 + 0.27) / (4.75 - 0.27 + 0.27) = 0.65

PDH = DMAX×Io²×RDS(MAX)

PDH = 0.65×14.2²×0.029 = 3.8W

L = 0.006×9000×(4.75 - 2.8) / (2×14.2) = 3.7µH

Assuming that the programmed switching frequency is RDS(MAX) = Maximum RDS(ON) of the MOSFET at 1258C

set at 200KHz, an inductor is designed using the For synch MOSFET, maximum power dissipation hap-

Micrometals’ powder iron core material. The summary pens at minimum Vo and minimum duty cycle.

of the design is outlined below:

DMIN @ (2 + 0.27) / (5.25 - 0.27 + 0.27) = 0.43

PDS = (1 - DMIN)×Io²×RDS(MAX)

The selected core material is Powder Iron, the selected

core is T50-52D from Micro Metal wounded with 8 turns

PDS = (1 - 0.43)×14.2²×0.029 = 3.33W

of #16 AWG wire, resulting in 3µH inductance with » Heat Sink Selection

3mΩ of DC resistance.

Selection of the heat sink is based on the maximum

allowable junction temperature of the MOSFETS. Since

Assuming L=3µH and Fsw=200KHz(switching fre- we previously selected the maximum RDS(ON) at 1258C,

quency), the inductor ripple current and the output ripple then we must keep the junction below this temperature.

voltage is calculated using the following set of equations: Selecting TO-220 package gives θJC=1.88C/W (From the

venders’ data sheet) and assuming that the selected

T º Switching Period

D º Duty Cycle

Vsw º High-side MOSFET ON Voltage

RDS º MOSFET On-Resistance

Vsync º Synchronous MOSFET ON Voltage

∆Ir º Inductor Ripple Current

∆Vo º Output Ripple Voltage

heat sink is black anodized, the heat-sink-to-case ther-

mal resistance is θcs=0.058C/W, the maximum heat sink

temperature is then calculated as:

Ts = TJ - PD×(θJC + θcs)

Ts = 125 - 3.82×(1.8 + 0.05) = 1188C

With the maximum heat sink temperature calculated in

the previous step, the heat-sink-to-air thermal resistance

(θSA) is calculated as follows:

T = 1/Fsw

Vsw = Vsync = Io×RDS

D » (Vo + Vsync) / (VIN - Vsw + Vsync)

TON = D×T

Assuming TA = 358C:

∆T = Ts - TA = 118 - 35 = 838C

Temperature Rise Above Ambient

TOFF = T - TON

∆Ir = (Vo + Vsync)×TOFF / L

∆Vo = ∆Ir×ESR

θSA = ∆T / PD = 83 / 3.82 = 228C/W

Rev. 1.6

08/20/02

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IRU3011

Next, a heat sink with lower θSA than the one calculated Switcher Output Voltage Adjust

in the previous step must be selected. One way to do As it was discussed earlier, the trace resistance from

this is to simply look at the graphs of the “Heat Sink the output of the switching regulator to the Slot 1 can be

Temp Rise Above the Ambient” vs. the “Power Dissipa- used to the circuit advantage and possibly reduce the

tion” given in the heat sink manufacturers’ catalog and number of output capacitors, by level shifting the DC

select a heat sink that results in lower temperature rise regulation point when transitioning from light load to full

than the one calculated in previous step. The following

AAVID and Thermalloy heat sinks, meet this criteria.

load and vice versa. To account for the DC drop, the

output of the regulator is typically set about half the DC

drop that results from light load to full load. For example,

if the total resistance from the output capacitors to the

Slot 1 and back to the Gnd pin of the device is 5mΩ and

if the total ∆I, the change from light load to full load is

14A, then the output voltage measured at the top of the

Co.

Part #

Thermalloy............................6078B

AAVID...................................577002

Following the same procedure for the Schottky diode resistor divider which is also connected to the output

results in a heatsink with θSA=258C/W. Although it is capacitors in this case, must be set at half of the 70mV

possible to select a slightly smaller heatsink, for sim- or 35mV higher than the DAC voltage setting. To do this,

plicity the same heatsink as the one for the high side the top resistor of the resistor divider, RTOP is set at 100Ω,

MOSFET is also selected for the synchronous MOSFET. and the bottom resistor, RB is calculated. For example,

if DAC voltage setting is for 2.8V and the desired output

Switcher Current Limit Protection

under light load is 2.835V, then RB is calculated using

The PWM controller uses the MOSFET RDS(ON) as the the following formula:

sensing resistor to sense the MOSFET current and com-

RB = 100×[VDAC /(Vo - 1.004×VDAC)] [Ω]

RB = 100×[2.8 /(2.835 - 1.004×2.800)] = 11.76KΩ

pares to a programmed voltage which is set externally

via a resistor (Rcs) placed between the drain of the

MOSFET and the “CS+” terminal of the IC as shown in Select 11.8KΩ, 1%

the application circuit. For example, if the desired cur-

rent limit point is set to be 22A and from our previous Note:The value of the top resistor must not exceed 100Ω.

selection, the maximum MOSFET RDS(ON)=19mΩ, then The bottom resistor can then be adjusted to raise the

the current sense resistor, Rcs is calculated as:

output voltage.

Vcs = ICL×RDS = 22×0.019 = 0.418V

Soft-Start Capacitor Selection

The soft-start capacitor must be selected such that dur-

ing the start up when the output capacitors are charging

Rcs = Vcs / IB = (0.418V) / (200µA) = 2.1KΩ

Where:

IB = 200µA is the internal current setting of the up, the peak inductor current does not reach the current

IRU3011

limit threshhold. A minimum of 1µF capacitor insures

this for most applications. An internal 10µA current

source charges the soft-start capacitor which slowly

Switcher Timing Capacitor Selection

The switching frequency can be programmed using an ramps up the inverting input of the PWM comparator

external timing capacitor. The value of Ct can be ap- VFB3. This insures the output voltage to ramp at the same

proximated using the equation below:

rate as the soft-start cap thereby limiting the input cur-

rent. For example, with 1µF and the 10µA internal cur-

rent source the ramp up rate is (∆V/∆t)=I/C=1V/100ms.

Assuming that the output capacitance is 9000mF, the

maximum start up current will be:

3.5 × 10^-5

Fsw @

Ct

Where:

Ct = Timing Capacitor

FSW = Switching Frequency

I = 9000µF×(1V / 100ms) = 0.09A

Input Filter

If, FSW = 200KHz:

It is recommended to place an inductor between the

system 5V supply and the input capacitors of the switch-

ing regulator to isolate the 5V supply from the switching

noise that occurs during the turn on and off of the switch-

ing components. Typically an inductor in the range of 1

to 3µH will be sufficient in this type of application.

3.5 × 10^-5

Ct @

= 175pF

200 × 10³

Rev. 1.6

08/20/02

www.irf.com

10

IRU3011

Switcher External Shutdown

7) If the output voltage is to be adjusted, place resistor

dividers close to the feedback pin.

The best way to shutdown the part is to pull down on the

soft-start pin using an external small signal transistor

such as 2N3904 or 2N7002 small signal MOSFET. This

allows slow ramp up of the output, the same as the power

up.

Note: Although, the device does not require resistor

dividers and the feedback pin can be directly con-

nected to the output, they can be used to set the

outputs slightly higher to account for any output drop

at the load due to the trace resistance. See the ap-

plication note.

Layout Considerations

Switching regulators require careful attention to the lay-

out of the components, specifically power components

since they switch large currents. These switching com- 8) Place timing capacitor C7 close to pin 20 and soft-

ponents can create large amount of voltage spikes and

high frequency harmonics if some of the critical compo-

start capacitor C2 close to pin 3.

nents are far away from each other and are connected Component connections:

with inductive traces. The following is a guideline of how

to place the critical components and the connections Note: It is extremely important that no data bus should

between them in order to minimize the above issues.

be passing through the switching regulator section spe-

cifically close to the fast transition nodes such as PWM

Start the layout by first placing the power components: drives or the inductor voltage.

1) Place the input capacitors C3 and the high side Using 4 layer board, dedicate on layer to Gnd, another

MOSFET, Q1 as close to each other as possible

layer as the power layer for the 5V, 3.3V and Vcore.

2) Place the synchronous MOSFETs, Q2 and the Q1 Connect all grounds to the ground plane using direct

as close to each other as possible with the intention vias to the ground plane.

that the connection from the source of Q1 and the

drain of the Q2 has the shortest length.

Use large low inductance/low impedance plane to con-

nect the following connections either using component

side or the solder side.

3) Place the snubber R4 & C7 between Q1 & Q2.

4) Place the output inductor, L2 and the output capaci-

tors, C10 between the MOSFET and the load with

output capacitors distributed along the slot 1 and

close to it.

a) C3 to Q1 Drain

b) Q1 Source to Q2 Drain

c) Q2 drain to L2

d) L2 to the output capacitors, C10

e) C10 to the slot 1

5) Place the bypass capacitors, C6 and C9 right next to

12V and 5V pins. C6 next to the 12V, pin 18 and C9

next to the 5V, pin 9.

f) Input filter L1 to the C3

Connect the rest of the components using the shortest

connection possible.

6) Place the IC such that the PWM output drives, pins

14 and 17 are relatively short distance from gates of

Q1 and Q2.

IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 02/01

Rev. 1.6

08/20/02

www.irf.com

11

IRU3011

(W) SOIC Package

20-Pin Surface Mount, Wide Body

H

A

B

C

R

E

DETAIL-A

L

PIN NO. 1

D

0.51±0.020 x 458

DETAIL-A

I

K

F

T

G

J

SYMBOL

20-PIN

MIN MAX

A

B

C

D

E

F

G

I

12.598 12.979

1.018 1.524

0.66 REF

0.33

7.40

0.508

7.60

2.64

0.30

0.32

2.032

0.10

0.229

J

10.008 10.654

08 88

0.406 1.270

0.63 0.89

2.337 2.642

K

L

R

T

NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.

Rev. 1.6

08/20/02

www.irf.com

12

IRU3011

PACKAGE SHIPMENT METHOD

PKG

PACKAGE

PARTS

T & R

DESIG

DESCRIPTION

COUNT

PER TUBE

PER REEL

Orientation

W

SOIC, Wide Body

20

38

1000

Fig A

1

Feed Direction

Figure A

IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 02/01

Rev. 1.6

08/20/02

www.irf.com

13


型号：	IRU3011
厂家：	Infineon
描述：	5-BIT PROGRAMMABLE SYNCHRONOUS BUCK CONTROLLER IC 5位可编程同步降压控制器IC 控制器
文件：	总13页 (文件大小：79K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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