IRU3055CQPBF [INFINEON]
Switching Controller, 500kHz Switching Freq-Max, PDSO36, PLASTIC, QSOP-36;
| 型号： | IRU3055CQPBF |
| 厂家： | 
Infineon |
| 描述： | Switching Controller, 500kHz Switching Freq-Max, PDSO36, PLASTIC, QSOP-36 控制器 |
| 文件： | 总26页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94262
IRU3055
5-BIT PROGRAMMABLE 3-PHASE
SYNCHRONOUS BUCK CONTROLLER IC
PRELIMINARY DATA SHEET TEST SPEC
FEATURES
DESCRIPTION
The IRU3055 is a 3-phase synchronous Buck controller
Meets VRM 9.0 Specification
3-Phase Controller with On-Board MOSFET Driver
which provides high performance DC to DC converter for
On-Board DAC programs the output voltage from high current applications.
1.075V to 1.850V
Loss-less Short Circuit Protection
Programmable Frequency
The IRU3055 controller IC is specifically designed to meet
Intel and AMD specifications for the new microproces-
Synchronous operation allows maximum efficiency sor requiring low voltage and high current.
Minimum Part Count
Soft-Start
Power Good Function
Hiccup Mode Current Limit
The IRU3055 features under-voltage lockout for both 5V
and 12V supplies, an external and programmable soft-
start function as well as programming the oscillator fre-
quency by using an external resistor.
APPLICATIONS
Intel Pentium 4 and AMD K7
TYPICAL APPLICATION
12V
C3
1uF
D1
C4
1000uF
C1
1uF
L1
1uH
C2
0.1uF
VCL1
VCL23
HDrv1
5V
Vcc
C6
C5
1uF
Q1
6x 1500uF
IRF3704S
R1
OCSet
L2
2.2K
Ref
Rt
1uH
Q2
IRF3711S
LDrv1
R2
1.5K
PGnd1/
OCGnd
C8
CS1
1.5V / 60A
1uF
Q3
IRF3704S
HDrv2
SS
L3
1uH
IRU3055
R3
47K
C9
1uF
C10
0.1uF
Q4
IRF3711S
LDrv2
R4
1.5K
D4
D3
PGnd2
C11
1uF
CS2
D2
D1
Q5
IRF3704S
HDrv3
L4
1uH
Q6
IRF3711S
D0
LDrv3
R5
1.5K
R6
PGnd3
C12
Comp
22nF
C13
1uF
27K
CS3
Fb
C7
100pF
C14
(Optional)
8x 2700uF
Figure 1 - Typical application of IRU3055.
PACKAGE ORDER INFORMATION
TA (8C)
DEVICE
PACKAGE
0 To 70
IRU3055CQ
36-Pin Plastic QSOP WB (Q)
Rev. 1.4
08/13/02
www.irf.com
1
IRU3055
ABSOLUTE MAXIMUM RATINGS
VCH12 and VCH3 Supply Voltage ................................... 30V (not rated for inductor load)
VCL1 and VCL23 Supply Voltage ................................... 20V
VCC Supply Voltage .................................................. 7V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
PACKAGE INFORMATION
36-PIN WIDE BODY PLASTIC QSOP (Q)
VCL1
36
Rt
Comp
Fb
1
2
35 LDrv1
34 PGnd1
33 OCGnd
32 HDrv1
31 VCH12
30 HDrv2
29 NC
3
SS
4
CS1
CS2
CS3
Vcc
5
6
7
8
9
28
27
VSET
D0
Gnd
10
PGnd2
D1 11
D2 12
26 LDrv2
25 VCL23
24 LDrv3
23 PGnd3
22 HDrv3
D3 13
D4 14
Fault 15
OCSet 16
Gnd 17
SD 18
VCH3
21
20 Ref
19 PGood
θJA =608C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over VCL1=VCL23=VCH12=VCH3=12V, Vcc=5V and TA=0 to
70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case tem-
peratures equal to the ambient temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Supply Current Section
Operating Supply Current
CL High Side=3000pF
CL Low Side=6000pF
V5
ICC
17
30
19
50
21
70
ICLH
V12 (150KHz frequency)
mA
VID Section
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VDAC
LREG
TREG
-1.5
-0.7
Vs
-0.06
1.4
+1.5
+0.7
2
%
%
%
V
4.5 < Vcc < 5.5V
08C < temp < 708C
0.4
VID Input HI
2
V
VID Input Internal Pull-Up
Resistor to 3.3V
VIDR
12.4
16.4
20.4
KΩ
Rev. 1.4
08/13/02
www.irf.com
2
IRU3055
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Power Good Section
Under-Voltage Lower Trip Point
Under-Voltage Upper Trip Point
UV Hysteresis
PGUVL
PGUVH
PGHYST
OVL
OVH
OVHYST
PGL
VOUT Ramping Down
VOUT Ramping Up
0.88Vs 0.90Vs 0.92Vs
0.89Vs 0.91Vs 0.93Vs
0.001Vs 0.01Vs 0.02Vs
V
V
V
V
V
V
V
V
V
V
V
V
Over-Voltage Upper Trip Point
Over-Voltage Lower Trip Point
OV Hysteresis
VOUT Ramping Up
VOUT Ramping Down
1.10Vs
1.11Vs 1.12Vs
1.09Vs 1.10Vs 1.11Vs
0.001Vs 0.01Vs 0.02Vs
Power Good Output LO
Power Good Output HI
UVLO Threshold - 5V
UVLO Hysteresis - 5V
UVLO Threshold - 12V
UVLO Hysteresis - 12V
Over-Voltage Section
OVP Threshold
Error Amp Section
Transconductance
Input Bias Current
Input Offset Voltage
Current Sense Section
Input Bias Current
Input Offset Voltage
CS Matching
RL=3mA
RL=5K Pull-Up to 5V
0
0.04
4.9
4.34
0.32
10.5
0.7
0.4
5
4.5
0.42
10.8
0.9
PGH
4.8
4.2
0.22
10.2
0.5
UVLO5UP Supply Ramping Up
UVLO5HYST Supply Ramping Down
UVLO12UP Supply Ramping Up
UVLO12HYST Supply Ramping Down
OVPTH Fault Pin
1.1Vs
0.5
1.15Vs
1.2Vs
V
gm
IBERR
720
2.5
3
µmho
µA
mV
CS1, CS2, CS3
5
6
VOSERR Fb to VSET
IBCS
CS1, CS2, CS3
0.9
2
µA
mV
mV
VOSCS CS1 to CS2, CS1 to CS3
CSMATCH Difference between any CS
4
4
2
Current Limit Section
OC Threshold Set Current
OC Comp Offset Voltage
Hiccup Duty Cycle
Soft-Start Section
Charge Current
IBOC
OCSet @ 0V
120
-8
1
160
-3
2.4
200
+2
µA
mV
%
VOSOC OCSet @ OC Threshold
HIC
ISS
Css=0.1uF
Soft-Start @ 0V
7
10
50
13
75
75
µA
ns
ns
ns
Output Drivers Section
Rise Time
TRL
TRH
TFL
CL High Side=3000pF,
CL Low Side=6000pF
CL High Side=3000pF,
CL Low Side=6000pF
CL High Side=3000pF,
CL Low Side=6000pF,
(Both Measured @ 10%)
25
25
Fall Time
50
TFH
Dead Band
DBLH
DBHL
130
Oscillator Section
Osc Frequency per Phase
PWM Ramping Voltage
Duty cycle Matching
fOSC
Rt = 50KΩ
Peak to Peak
100
1.98
150
2.02
0.03
200
2.06
KHz
V
VOSC
OSCMATCH LDrv or HDrv
%
Note 1: Vs refers to the set point voltage given in Table 1
Rev. 1.4
08/13/02
www.irf.com
3
IRU3055
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.475
1.800
1.825
1.850
Table 1 - Set point voltage (Vs) vs. VID codes.
PIN DESCRIPTIONS
PIN#
PIN SYMBOL
PIN DESCRIPTION
1
Rt
This pin programs the oscillator frequency in the range of 50KHz to 500KHz with an
external resistor connected from this pin to the ground.
2
3
Comp
Fb
Compensation for error amplifier.
This pin is connected directly to the output of the Core supply to provide feedback to the
Error amplifier.
4
SS
This pin provides the soft-start for the switching regulator. An internal current source
charges an external capacitor that is connected from this pin to the ground which ramps
up the outputs of the switching regulator, preventing the outputs from overshooting as
well as limiting the input current. The second function of the Soft-Start cap is to provide
long off time (HICCUP) for the synchronous MOSFET during current limiting.
Current sense feedback for channel 1, 2, 3.
5
6
7
8
9
CS1
CS2
CS3
Vcc
VSET
D0
5V supply voltage.
Output of the DAC.
10
LSB input to the DAC that programs the output voltage. This pin is internally connected
to 3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply. This pin programs the output voltage in 25mV steps based on the VID table.
Input to the DAC that programs the output voltage. This pin is internally connected to
3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
Input to the DAC that programs the output voltage. This pin is internally connected to
3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
Input to the DAC that programs the output voltage. This pin is internally connected to
3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
MSB input to the DAC that programs the output voltage. This pin is internally connected
to 3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
11
12
13
14
D1
D2
D3
D4
Rev. 1.4
08/13/02
www.irf.com
4
IRU3055
PIN#
PIN SYMBOL
PIN DESCRIPTION
15
Fault
Fault detector. When the output exceeds the OVP trip point, the fault pin switches to
2.8V and pulls down the soft-start.
16
OCSet
Gnd
This pin is connected to the drain of the synchronous MOSFET in channel 1 of the Core
supply and it provides the positive sensing for the internal current sensing circuitry. An
external resistor programs the over current threshold depending on the RDS(ON) of the
power MOSFET.
Analog ground for internal reference and control circuitry. Connect to PGnd with a short
trace.
17
28
18
19
SD
PGood
Shut down pin. Pulling-up this pin disables the outputs.
Power good pin. This pin is a collector output that switches Low when the output of the
converter is not within ±10%(typ) of the nominal output voltage.
2V reference output.
These pins power the high side MOSFET driver. A minmum 1µF ceramic cap must be
connected from these pins to ground to provide peak drive current capability.
Output drivers for the high side power MOSFET.
20
21
31
22
30
32
23
27
34
24
26
35
25
36
Ref
VCH3
VCH12
HDrv3
HDrv2
HDrv1
PGnd3
PGnd2
PGnd1
LDrv3
LDrv2
LDrv1
VCL23
These pins serve as the ground pins and must be connected directly to the ground plane.
A high frequency capacitor (0.1 to 1µF) must be connected from pins VCL1, VCL23 and
VCH3, VCH12 to PGnd1, 2 and 3 for noise free operation.
Output driver for the synchronous power MOSFET.
These pins are connected to the 12V supply and serves as the power Vcc pin for the low
side output drivers. A high frequency capacitor (0.1 to 1µF) must be connected directly
from these pins to PGnd1, PGnd2 and PGnd3 pins in order to supply the peak current to
the power MOSFET during the transitions.
VCL1
29
33
NC
OCGnd
No connection.
This pin is connected from the source of the synchronous MOSFET in channal 1 of the
Core supply and it provides the reference point for the internal current sensing circuitry.
Rev. 1.4
08/13/02
www.irf.com
5
IRU3055
BLOCK DIAGRAM
160uA
16 OCSet
33 OCGnd
10uA
SS
4
2
VCH12
31
Comp
Master Error Amp
32 HDrv1
Fb
3
9
S
R
P1 PWM Comp
SET
VCL1
36
V
Q
SD
SD
SD
P1 Ramp
SD
10
D0
P1 PWM Latch
Reset Dom
35 LDrv1
VSET
D1 11
D2 12
P1 Set
5-Bit
DAC
P1 Ramp
34 PGnd1
P2 Set
3-Phase
Oscillator
P2 Ramp
P3 Set
13
D3
P3 Ramp
14
1
D4
Rt
HDrv2
30
S
Q
R
P2 PWM Comp
25 VCL23
26 LDrv2
P2 Ramp
P2 Duty Cycle Adj
5
6
7
8
CS1
CS2
CS3
Vcc
P2 PWM Latch
Reset Dom
27 PGnd2
21 VCH3
Chip Power
HDrv3
22
Fault 15
PGood / OVP
S
Q
R
PGood 19
P3 PWM Comp
P3 Ramp
P3 Duty Cycle Adj
Ref 20
Gnd 17
Gnd 28
2V Reference
P3 PWM Latch
Reset Dom
24 LDrv3
PGnd3
23
NC
SD
29
18
Shut Down
SD
Figure 2 - Simplified block diagram of the IRU3055.
Rev. 1.4
08/13/02
www.irf.com
6
IRU3055
TYPICAL APPLICATION (1)
12V
C3
D 1
C4
C1
1uF
1uF
L1
1000uF
1uH
C2
0.1uF
VCL1
5V
Vcc
VCL23
HDrv1
C6
C5
Q1
6x 1500uF
1uF
IRF3704S
R1
OCSet
L2
2.2K
Ref
Rt
1uH
Q2
LDrv1
IRF3711S
R2
PGnd1/
OCGnd
1.5K
C8
CS1
1.5V / 60A
1uF
Q3
IRF3704S
HDrv2
SS
L3
IRU3055
C9
R3
C10
0.1uF
1uH
1uF
47K
Q4
LDrv2
PGnd2
IRF3711S
R4
1.5K
D4
D3
C11
1uF
CS2
D2
D1
Q5
HDrv3
L4
IRF3704S
1uH
Q6
D0
LDrv3
PGnd3
IRF3711S
R5
1.5K
R6
C12
Comp
22nF
C13
1uF
27K
CS3
Fb
C7
100pF
C14
(Optional)
8x 2700uF
Figure 3 - Typical application of IRU3055.
Parts List
Ref Desig Description
Q1,Q3,Q5 MOSFET
Q2,Q4,Q6 MOSFET
Value
20V, 9mΩ
Qty
3
Part#
IRF3704S
Manuf
Web site (www.)
IR
IR
IR
IR
irf.com
20V, 6mΩ
Synchronous PWM
3
1
1
IRF3711S
IRU3055
BAT54S
U1
Controller
D1
Schottky Diode In Series
L1
L2,L3,L4
Inductor
Inductor
1µH
1µH
1
3
Z9479-A
Coilcraft
coilcraft.com
T60-18 Core, 6-turns
#14 AWG wire
ECJ-3YB1E105K
ECJ-2VF1E104Z
ECJ-3VF1C105Z
C1
C2,C10
C3,C5,C9, Cap, Ceramic
C8,C11,C13
Cap, Ceramic
Cap, Ceramic
1µF, X7R, 25V
0.1µF, Y5V, 25V
1µF, Y5V, 16V
1
2
6
Panosonic maco.panasonic.co.jp
Panosonic
Panosonic
C4
C6
Cap,Electrolytic 1000µF, 16V
Cap,Electrolytic 1500µF, 16V
Cap (Optional) 100pF, X7R, 50V
1
6
1
1
8
1
3
1
1
Any
EEU-FJ1C152U
Panosonic maco.panasonic.co.jp
C7
ECU-V1H101KBN Panosonic
ECU-V1H223KBG Panosonic
C12
C14
R1
Cap, Ceramic
22nF, X7R, 50V
Cap,Electrolytic 2700µF,6.3V,13mΩ
EEU-FJ0J272U
Panosonic
Any
Any
Resistor
2.2K, 1%
1.5K, 1%
47K, 1%
27K, 1%
R2,R4,R5 Resistor
R3
R6
Resistor
Resistor
Any
Any
Rev. 1.4
08/13/02
www.irf.com
7
IRU3055
APPLICATION INFORMATION
Constant Switching Frequency 3-Phase
Output Current Ripple Reduction
Controller
IRU3055 is a 3-phase buck converter controller. For high
current applications, multiple converters are usually con-
nected in parallel to reduce the power capability for each
individual converter as well as alleviate the thermal stress
on each of the power devices. These individual convert-
ers share a common output, but may have different input
sources. Each individual converter operates at the same
switching frequency but at a different phase. As a result,
the effective input current and output current ripple are
much smaller compared with a single-phase converter.
Another benefit will be faster dynamic load responses.
The block diagram of IRU3055 is shown in Figure 2. The
3-phase oscillator provides a constant frequency and the
three PWMs ramp signals with 120 degree phase shift.
The three comparators and three PWM latches will gen-
erate three PWM outputs to the drivers which are built
inside the IC. A typical 3-phase PWM signal is shown in
Figure 4.
Figure 5 - Output inductor currents and
output capacitor ripple current.
1
0.9
Single
phase
0.8
0.7
0.6
0.5
Two
phase
0.4
0.3
0.2
0.1
0
Three
phase
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
D
1
Figure 6 - Normalized output current across
output capacitor.
(Peak to peak current normalized to the Vo/(L×Fs)).
One of advantages of the multi-phase converter is that
the output current ripple is significantly reduced. The
current from multiple converters tend to cancel each
other so that the total output current flowing into the
Figure 4 - The 3-phase PWM signal.
Voltage and Current Loop
IRU3055 has three transconductance error amplifiers. output capacitor is reduced. In this case, the output in-
The master Error amplifier is used to regulate the output ductor in each individual buck converter can be selected
voltage. The output voltage can connect directly, or smaller to improve the load transient response without
through a resistor divider, to the Fb pin of the error ampli- sacrificing the output current ripple. Figure 5 shows a 3-
fier. The compensation network at the output of the am- phase inductor current and current ripple in the capaci-
plifier (Comp Pin) helps to stabilize the voltage loop. The tor for 12V input 1.5V, 50A, 3-phase buck converter. The
non-inverting pin of the master amplifier is connected to effective output ripple has three times frequency and a
the output of the DAC which interfaces with the micro smaller amplitude compared with each individual con-
processor core and determines the desired output volt- verter. Figure 6 indicates the total ripple current, as a
age. Two additional transconductance amplifiers are used function of duty cycle, normalized to the parameter Vo/
to balance the output inductor current among 3-phases. (L×Fs) at zero duty cycle.
Rev. 1.4
08/13/02
www.irf.com
8
IRU3055
It is shown that the output current ripple is greatly re- Through an internal resistor, there will be an additional
duced by multi-phase operation. At the certain duty cycle voltage drop above the node Comp and then the voltage
D=1/m, where m is the phase number, the output ripple sent to the PWM comparator will be higher and the gen-
will be near zero due to complete cancelation of inductor erated duty cycle for phase-2 will be larger. As a result,
current ripple. The optimum number of phases exists for the inductor (L2) current will go up until the current bal-
different applications.
ance is achieved. For accurate current sharing, the cur-
rent sense from each inductor should be as symmetri-
cal as possible. The layout is critical and the layout of
the RC network should be as follows:
Output Inductor Current Sensing
IRU3055
Connect the node from Resistor R1 (or R2) directly to
the pad of inductor. Connect the other node of capacitor
C1 and C2 together and connect to the output voltage
terminal. In this case, the voltage at node C1 and C2
will have a common reference voltage that is output volt-
age. If the inductor inherent resistance as well as PCB
trace are almost identical or symmetrical, almost per-
fect current sharing can be obtained. The PCB connec-
tion from three inductors to the output capacitor should
have the same length and width. The feedback point from
the output should be located such that the effect imped-
ances from the three inductors to the output feedback
sensing point are almost symmetrical or identical so
that the noise will cancel each other. The current shar-
ing accuracy is dependent upon the mismatch among
Comp
P1 Ramp
P2 Ramp
Master
Error Amp
V
SET
L1
R
L1
VOUT
Fb
R1
C1
CS1
CS2
L2
RL2
P2 Duty Cycle
Adj
R2
C2
Figure 7 - Loss-less inductive current sensing
and current sharing.
The loss-less sensing current is achieved by sensing the values of current sensing components and the cur-
the voltage across the inductor. In Figure 7, L1 and L2 rent amplifier offset. It is recommended that all the in-
are inductors. RL1 and RL2 are inherent inductor resis- ductors be from the same manufacturer and also be the
tance. The resistor R1 and capacitor C1 are used to same model so that mismatch will be minimized and
sense the average inductor current. The voltage across the cost reduced. In most cases, with a good layout, the
the capacitors C1 and C2 represent the average current difference between 3-channel currents can be limited to
flowing into resistance RL1 and RL2. The time constant of be below 2A.
the RC network should be equal or at most three times
larger than the time constant L/RL.
Operation of IRU3055
Over Current Protection
The IRU3055 senses the MOSFET switching current to
achieve the over current protection. The diagram is shown
L
RL
R1×C1=(1~3)×
---(1)
In order to minimize the effect of the bias current in in Figure 8. A resistor (RSET) is connected between pin
IRU3055, the sensing resistor should be as small as OCSet and the drain of the low side MOSFET for phase1.
possible. However, a small resistor will result in high Inside the IC, there is an internal 160µA current source
power dissipation and a high value capacitor, a trade off connected to OCSet pin. When the upper switch is turned
has to be chosen. Typically, a 1µF ceramic capacitor is off, the inductor current flows through the low side switch.
a good start. In the Application Circuit (1), L=1µH and The voltage at OCSet pin is given as:
RL=1.6mΩ. The sensing resistor and capacitor is cho-
VOCSet = 160µA×RSET - RDS(ON)×iL1
---(2)
sen as:
160uA
10uA
R1= 1.5K and C1= 1µF
IRU3055
The voltage across the sensing capacitors are sent to
the pins CS1 and CS2. Suppose the inductor current in
the inductor L2 is smaller than in inductor L1 and the
voltage across capacitor C1 will be greater than that
across C2. The transconductance amplifier in IRU3055
will generate a positive current flowing into node Comp.
SS
L1
VOUT
RSET
OCSet
OCGnd
Hiccup
Logic
Phase 1
Figure 8 - Diagram of the over current sensing.
Rev. 1.4
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9
IRU3055
When the inductor current is large enough, the voltage Over Voltage Protection
across the low side switch is low enough so that the The Fb pin is connected to the output voltage. An over-
voltage at OCSet node is below zero and the compara- voltage condition is detected when the voltage at Fb pin
tor will flip and trigger a switch to discharge the soft-start is 15% higher than the programmed voltage by DAC.
capacitor at a certain slope rate. The system enters into When the overvoltage occurs, the soft-start capacitor is
a hiccup mode. The over current threshold can be set by discharged. The high side MOSFETs are turned off and
resistor RSET. Suppose the current sharing is perfect, the low side MOSFETs are turned on. As a result, the
then the current flowing into phase 1 will be one third of low side MOSFET of synchronous rectifier conduct and
the total output current. The maximum allowed output shunt the output voltage to ground and protect the load.
current can be represented as:
IMAX = 160µA × RSET / (RDS(ON)/3)
RSET = IMAX×RDS(ON)/3/160µA
In the meantime, the PGood pin is held to low.
Soft-Start
---(3)
The IRU3055 has a soft-start function to limit the current
Where RDS(ON) is the ON resistance of low side MOSFET. surge at the start-up. An external capacitor which is
In practice, the RDS(ON) of MOSFET is temperature de- charged by a 10µA internal current source is used to
pendent. The overhead has to be considered. For prac- program the soft-start timing. The voltage of the external
tice, over current threshold has to be at least 50% higher capacitor linearly increases, which forces the output volt-
than the nominal current plus ripple. In the demo-board, age to go up linearly until the voltage at soft-start reaches
the maximum output current is set to be:
the desired voltage. The following equation can be used
to calculate the start up time.
IMAX = (1+50%)×IOUT = 1.5×60A = 90A
10µA×tSTART/Css = VSET+0.7V
Consider ripple current, select IMAX=100A
tSTART = (VSET+0.7V)×Css/10µA
---(4)
For each phase, the maximum current is one third (33A),
assuming good current sharing. The low side of MOSFET
is IRF3711S. The On resistor at 150 degrees is given
from the data sheet:
Where:
Css is the soft-start capacitor (µF).
VSET is the voltage from DAC and equal to the de-
sired output voltage.
RDS(ON) = 1.5×6mΩ = 9mΩ
For a 7.5ms start-up time and 1.5V output, the required
capacitor will be 33nF.
The over current setting resistor can be set as
RSET = 33A × 0.009/160µA = 1.86K
Operation Frequency Selection
Select RSET = 2.2K
The operation switching frequency is determined by an
external resistor (Rt). The switching frequency is approxi-
mately inversely proportioned to resistance (see Fig.10).
The switching frequency can also be estimated by:
Fs @ 7500/Rt
---(5)
Where Rt is in KΩ and Fs is in KHz.
For example, if the 150KHz switching frequency is se-
lected, the required Rt is calculated as:
Rt @ 7500/150 = 50KΩ
Frequency versus Rt
500
400
300
200
100
Figure 9 - Operation waveforms at short circuit.
(Hiccup mode)
0
0
10
20
30
40
50
60
70
Ch1: Input current, 5A/div.
Rt(K
)
Ω
frequency
Ch2: Phase 1 inductor current, 10A/div.
Ch3: Soft-start capacitor voltage, 5V/div.
Ch4: Output voltage, 2V/div.
Figure 10 - The operation frequency vs. Rt.
Rev. 1.4
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10
IRU3055
Synchronous-Rectifier Driver
Component Selection Guide
Output Inductor Selection
VC1
The inductor is selected based on the inductor current
ripple, operation frequency and efficiency consideration.
In general, a large inductor results in small output ripple
and higher efficiency but big size. A small value inductor
causes large current ripple and poor efficiency but small
size. Generally, the inductor is selected based on the
output current ripple. The optimum point is usually found
between 20% and 50% ripple of output inductor current.
For each phase synchronous buck converter, the output
peak-to-peak current ripple is given by:
C1
C2
C3
V
IN
V
CH12
VCH3
L1
IRU3055
Phase 1
∆i(PEAK - PEAK) = (VIN-VOUT)×VOUT/(L×Fs×VIN) ---(6)
Figure 11 - Supply VCH12, VCH3 with
charge bump configuration.
Assuming the output current is evenly distributed in each
phase, we can define the ratio of the ripple current and
Synchronous rectification reduces conduction losses in nominal output current as:
the rectifier by shunting the normal Schottky diode or
MOSFET body diode with a low on-resistance MOSFET
LIR = ∆i(PEAK - PEAK)/ IOUT / m
switch. The synchronous rectification also ensures good Where LIR is typically between 20% to 50% and m is
transient dynamic. For IRU3055, the 3-phase synchro- the phase number. In this case m=3. Then the inductor
nous rectifier MOSFET drivers are built inside. To drive can be selected by:
the high-side MOSFET, it is necessary to supply a gate
voltage at least 4V greater than the bus voltage. In
L>VOUT×(VIN-VOUT)/(Fs×VIN×LIR×IOUT/m)
---(7)
IRU3055, the driver supply voltage for high side MOSFET For example, in the application circuit, the ripple is se-
driver is supplied through the VCH12 and VCH3 pins. If the lected as LIR=40%, the inductor is selected as:
input voltage for DC-DC converter is 5V, the VCH12 and
L>1.5×(12-1.5)/(150K×12×40%×60A/3)=1.1µH
VCH3 pins can be connected to 12V or supplied by using
charge pump configuration as shown in Figure 11.
Select L=1µH
If the voltage Vc1 and VIN in Figure 11 is connected to The RMS current of the inductor will be approximately
input voltage 12V, the voltage at VCH12 and VCH3 pins are equal to average current:
charged up to almost twice the input voltage. The high
side driver can be enabled. A capacitor in the range of
IOUT/m = 60/3 = 20A.
0.1µF to 1µF is generally adequate for capacitor C2. The peak inductor current is about:
For high current applications, a large ceramic capacitor
such as 2.2µF is recommended. The diode can be a
IL(PEAK) = (1+LIR/2)×IOUT/m = 1.2×20 = 24A
Schottky diode such as BAT54S.
Output capacitor selection
The voltage rating of the output capacitor is the same as
With the charge bump configuration, shown in Figure output voltage. Typical available capacitors on the mar-
11, the voltage at pins VCH12 and VCH3 can be boosted ket are electrolytic, tantalum and ceramic. If electrolytic
up. When the low side MOSFET is on, the capacitor C2 or tantalum capacitors are employed, the criteria is nor-
is charged to voltage Vc1. When the high side MOSFET mally based on the value of Effective Series Resistance
is ON, the energy in the capacitor C2 is discharged to (ESR) of total output capacitor. In most cases, the ESR
the bypass capacitor C1 next to pins VCH12 and VCH3. of the output capacitor is calculated based on the follow-
The voltage at VCH12 and VCH3 pins is approximately the ing relationship:
sum of the voltage Vc1 and VIN. The high side driver
signal should be at least 4V higher than the input volt-
ESR < ∆V/∆i
---(8)
age (VIN). The voltage Vc1 has to be 5V or higher. For Where ∆V is the maximum allowed output voltage drop
the demo-board, Vc1 is equal to input voltage (VIN=12V). during the transient and ∆i is the maximum output cur-
If the low power dissipation of IC is preferred, especially rent variation. In the worst case, ∆i is the maximum out-
at higher frequency, Vc1 can be connected to 5V in- put current minus zero.
stead.
Rev. 1.4
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11
IRU3055
Power MOSFET Selection
Where q is the temperature coefficient of ON resistor of
The IRU3055 is a controller for 3-phase synchronous MOSFET RDS(ON) and can be found in MOSFET data
buck converter. For each phase, the average inductor sheet (typically between 1 and 2).
current will be one third of the total output current in an
ideal case, which will greatly alleviate the thermal man- In this example, the MOSFET IRF3704S is chosen to
agement for power switch. In general, the MOSFET se- be the high side switch with:
lection criteria depends on the maximum drain-source
voltage, RMS current and ON resistance (RDS(ON)). For
both high side and low side MOSFET, a drain-source
RDS(ON) = 9mΩ
q = 1.5 @ 1508C
voltage rating higher than maximum input voltage is nec- The conduction loss for high side MOSFET is given as:
essary. In the demo-board, 20V rating should be satis-
fied. The gate drive requirement for each MOSFET is
PCON(HI)=9mΩ×1.5×(60/3)×(60/3)×1.5/12=0.68W
almost the same. If logic-level MOSFET is used, some Low side switch is configured with one IRF3711 with 6mΩ
caution should be taken with devices at very low VGS RDS(ON). The conduction loss is calculated as:
to prevent undesired turn-on of the complementary
MOSFET, which results a shoot-through circuit.
PCON(LO) = 6mΩ×1.5×(60/3)×(60/3)×(1-1.5/12)
PCON(LO) = 3.15W
If output inductor current ripple is neglected, the RMS The switching loss for MOSFET is more difficult to cal-
current of high side switch is given by:
culate due to effect of the parasitic components, etc.
The switching loss can be estimated by the following
equation:
IRMS(HI) =
IRMS(HI) =
D×IOUT/m
(VOUT/VIN)×IOUT/m
---(9)
PSW = VDS(OFF)×(tr+tf)×FS×ISW/2
The RMS current of low side switch is given as:
Where:
IRMS(LO) =
IRMS(LO) =
(1 - D)×IOUT/m
VDS(OFF) is the Drain to Source voltage when switch
is turned off.
tr is the rising time.
(1 - VOUT/VIN)×IOUT/m
In the demo board, RMS current of high side switch is:
tf is the fall time.
IRMS(HI) = (1.5/12)×60/3 = 7.1A
RMS current of low side switch is:
IRMS(LO) = (1 - 1.5/12)×60/3 = 18.7A
FS is the switching frequency.
ISW is the current in MOSFET when MOSFET is
turned off. It can be estimated by:
For RDS(ON) of MOSFET, it should be as small as pos-
sible in order to get highest efficiency. The MOSFET
ISW = ILOAD/m + half of the ripple current
from International rectifier IRF3704S with a RDS(ON)=9mΩ, In this example, for low side MOSFET, the body diode is
20V drain source voltage rating and 77A ID is selected turned on before MOSFET is on. Therefore, the switch-
for high side MOSFET.
ing losses for low side MOSFET is almost zero due to
zero voltage switching. For high side MOSFET, from data
For a high input and low output case, the low side switch sheet, we have:
conducts most of output current and handles most of
tr = 50ns
the thermal management. Two MOSFETs can be put in
tf = 50ns
parallel to further reduce the effect RDS(ON) and conduc-
Select FS = 150KHz
VDS(OFF) = 12V
ISW = Peak Inductor Current = 24A
PSW(HI) = 12V×(50ns+50ns)×150KHz×24A/2
PSW(HI) = 2.1W
tion losses. In the demo-board, MOSFET from Interna-
tional Rectifier IRF3711S with RDS(ON)=6mΩ, 20V VDS and
110A ID is selected as synchronous MOSFET. The power
dissipation includes conduction loss and switching loss.
The conduction loss for high side switch in each phase The total power dissipation is:
can be estimated by the following equation:
PD(HI) = PCON(HI)+PSW(HI)
PD(HI) = 0.68W+2.16W = 2.84W
PCON(HI) = RDS(ON)×q×(IOUT/m)×(IOUT/m)×(VOUT/VIN)
PD(LO) @ PCON(LO) = 3.15W
The low side switch power dissipation is:
PCON(LO)=RDS(ON)×q×(IOUT/m)×(IOUT/m)×(1-VOUT/VIN)
Rev. 1.4
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12
IRU3055
Heat Sink Selection
Input Filter Selection
The criteria of selecting heat sink is based on the maxi-
mum allowable junction temperature of the MOSFETs.
That is:
0.5
Single-
Phase
0.4
TA + PD×(RθJC+RθCS+RθSA) < TJ(MAX)
Where:
IRMS(IN)
IOUT
Two-
Phase
0.3
TA = The Ambient Temperature
PD = Power Dissipation of each MOSFET
RθJC = The Thermal Resistance from junction to case
RθCS = the thermal resistance from case to heat sink
RθSA = the heat-sink-to-air thermal resistance
TJ(MAX) = maximum allowable junction temperature
of MOSFET, for example 1508C.
0.2
0.1
0
Three-
Phase
0
0.1
0.2
0.3
0.4
0.5
The maximum heat-sink-to-air thermal resistance is cal-
culated as:
D
Figure 12 - Normalized input RMS current vs.
duty cycle.
RθSA < (TJ(MAX)-TA)/PD-RθJC+RθCS
In this example, the MOSFET is mounted in the PCB The selection criteria of input capacitor are voltage rat-
board with more than 1" square PCB board. Therefore, ing and the RMS current rating. For conservative consid-
the junction temperature for MOSFET can be calculated eration, the capacitor voltage rating should be 1.5 times
as:
higher than the maximum input voltage. The RMS cur-
rent rating of the input capacitor for multi-phase con-
verter can be estimated from the above Figure 12.
TJ = TA + PD×RθJA
Where RθJA is the junction-to-ambient thermal resistance
with MOSFET on 1" square PCB board and it is avail- First, determine the duty cycle of the converter (VO/VIN).
able from MOSFET data sheet.
The ratio of input RMS current over output current can
be obtained. Then the total input RMS current can be
For MOSFET IRF3704S with D2 package, RθJA = 408C/ calculated. From this figure, it is obvious that a multi-
W. Assume ambient temperature is TA=358C. For high phase converter can have a much smaller input RMS
side MOSFET, the junction temperature is given as:
current, which results in a lower amount of input capaci-
tors that are required.
358C + 2.84W×408C/W = 1498C
For low side MOSFET, IRF3711s, the maximum junc- For high current applications, multiple bulk input capaci-
tion temperature can be calculated as:
tors in parallel may be necessary. Some electrolytic
capacitors, such as Panasonic HFQ series, Sanyo MV-
WX or equivalent may be put in parallel to provide a large
358C + 3.15W×408C/W = 1618C
This is the worst case. For conservative consideration, current. In addition, ceramic bypass capacitors for high
two IRF3711 can be put in parallel.
frequency de-coupling are recommended. Furthermore,
some small ceramic capacitors should be put very close
to the drain of the high side MOSFET and source of the
low side switch to suppress the voltage spike caused by
parasitic circuit parameters.
For high current applications, a 1µH input inductor is
recommended to slow down the input current transient.
Rev. 1.4
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IRU3055
Design Example
(5) MOSFET Selection
In the demo-board, the condition is as follows:
By equation (9), the RMS current of high side
MOSFET is given as:
VIN=12V, VOUT=1.5V and IOUT=60A
IRMS(HI) =
IRMS(HI) =
D = 1.5/12 = 0.125
D×IOUT/m
(VOUT/VIN)×IOUT/m
Output voltage regulation is within 100mV during tran-
sient.
IRMS = 0.125×60A/3 = 7.1A
(1) Select Switching Frequency
Fs = 150KHz for each phase
Select MOSFET from International Rectifier
IRF3704S with D-2 pak, which will result to:
According to Figure 10 and equation (5), the oscilla-
tor selection resistor is given by:
RRDS(ON) = 9mΩ and 110A IDS current
For low side MOSFET:
Rt @ 7500/150 = 50K
From Figure 10, select Rt=47K
IRMS(LO) =
(1-D)×IOUT/m
D = VOUT/VIN = 1.5/12 = 0.125
IRMS(LO) = (1-0.125)×60/3 = 19A
(2) Soft-Start Capacitor
For 1.5V output, VSET=1.5V. The soft-start time of
the converter can be estimated from equation (4):
Select MOSFET from International Rectifier
IRF3711S with D-2 package, which will result to:
tSTART = (VSET+0.7V)×Css/10µA
RDS(ON)(LO) = 6mΩ and 110A current
If tSTART=20ms, then:
(6) Over Current Setting
Css = 20ms×10µA/(1.5V+0.7V) = 95nF
Choose Css=0.1µF
By equation (3), over current limit is set by RSET. The
current limit should be at least 150% of the nominal
output current. Set IMAX=90A and 30A for each phase.
For low side MOSFET, RDS(ON)=6mΩ and 9mΩ at
1508C. The over current setting resistor is given by:
(3) Output Inductor and Capacitor
Select the current ripple LIR=40%, by equation (7):
L>VOUT×(VIN-VOUT)/(Fs×VIN×LIR×IOUT/m)
L>1.5×(12-1.5)/(150K×12×40%×60A/3)=1.1µH
RSET = IMAX×RDS(ON)/3/160µA
RSET = 90A×9mΩ/3/160µA = 1.7KΩ
Select RSET = 2.2KΩ
Select core from Micrometal, T60-18 with 6 turns
#14 AWG wire, which gives 1µH inductor, 15A RMS
and 25A saturation current. The DC resistor of in- (7) Compensation Design
ductor is 1.6mΩ.
For detailed explanation, please see IRU3037 data
sheet. Select bandwidth of the system to be 1/10 of
switching frequency that is 15KHz:
L = 1µH and RL = 1.6mΩ
The output capacitor is based on ESR. Suppose
the maximum allowed voltage droop for 60A load is:
Fo = 2×3.14×15KHz = 94KHz
The compensation resistor can be calculated as:
Rc = Vosc×Fo×L/(VIN×ESR×gm)
∆V = 100mV
ESR < ∆V/∆i = 100mV/60A = 1.66mΩ
Select 8 Panasonic capacitors. EEUFJ0J272U with
2700µF and 13mΩ ESR each. The total:
Where Vosc is the ramp peak voltage and gm is the
transconductance of the error amplifier. From the
data sheet:
COUT = 8×2700µF = 21600µF
ESR = 13mΩ/8 = 1.6mΩ
Vosc = 2V
gm = 720µmho
(4) Senseless Inductor Current Sensing
With equation (1), we select the inductor sensing
network which has a time constant:
Rc = 2×94KHz×1µH/(12×1.6mΩ×720µmho)
Rc = 12KΩ. Select R6=Rc=12.7KΩ
The compensator capacitor is given as:
R2×C8 = 2×L/RL
Select: C8 = 1µF
R2 = 2×1µH/(1.6mΩ×1uF) = 1.25K
Cc = (L×COUT) /0.75/Rc
Cc = (1µH×21600µF) /0.75/12KΩ = 16.3nF
Select C12=Cc=22nF
Select R2, R4 and R5 = 1.5K
Rev. 1.4
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IRU3055
In practice, the resistor Rc (R6 in Fig.3) can be tuned for (4). Place the other 2-phase Q3, Q4 and Q5, Q6 follow-
a better dynamic load response. Higher Rc will result in ing the same rule.
a fast transient response. Cc (C12 in Fig.3) can be kept
unchanged. In Fig.3. R6=27KW.
(5) Place output inductor Lo1, Lo2, Lo3 and output ca-
pacitor COUT. Make sure the output capacitors are evenly
distributed among 3-phases and close to the output slot.
(8) Input Capacitor Selection
From the Figure 12, according to the duty ratio, pick
up the normalized input RMS current. For this ex- (6) Place IC IRU3055 such that the driver pins, HDrv1,
ample:
HDrv2, Hdrv3 and LDrv1, LDrv2, LDrv3, have a relatively
short distance from the corresponding MOSFET gate. In
addition, make the 3-phase driving signal path as sym-
metrical as possible. If the length of the gate signal path
IRMS(IN)/IOUT = 0.15
IRMS(IN) = 0.15×60A = 9A
Select Panosonic capacitor. Four EEUFJ1C152U is more than 1cm long, a 2 to 10Ω gate resistor is rec-
with1500µF give results to:
ommended to be in series in the gate signal path.
4×2.5 = 10A RMS current.
(7) Place bypass capacitor close to Vcc pin, VREF pin
and VCH12,VCH3 pins and also soft-start capacitor to SS
Layout Considerations
For any switching converter, the current transition from pin.
one power device to another usually causes voltage
spikes across the power component due to parasitic (8) Place a frequency selection resistor (Rt) close to Rt
inductance and capacitance. These voltage spikes will pin.
result in reduction of efficiency, increased voltage stress
of power components and radiated noise to circuit. A (9) Connect output inductor current sensing network such
good layout can minimize these effects.
as R2, C8 close to IRU3055. One example of the layout
is shown as follows:
There are several critical loops for IRU3055 controlled
multi-phase converter. The loop by synchronous
MOSFETs and input capacitor is the most critical loop
and it should be minimized as small as possible. Put a
small ceramic capacitor next to the drain of high side
switch and source of low side switch. Put the input ca-
pacitors to the high and low side switch as close as
possible. The second loop is the gate of MOSFETs and
the drivers from IRU3055. Because the IRU3055 includes
the MOSFETs drivers inside, the signal path between
driver to the gate of MOSFETs should be minimized.
The trace should handle 1A transient current ability.
Output copper plane
CS1
Output Cap
VOUT
IRU3055
CS2
CS3
Fb
Close to IRU3055
The following is a guideline of how to place the critical
components and the connections between components
in order to minimize the switching noises.
Figure 13 - An example of layout connection for
inductor current sensing.
Connect current sensing resistors Rs1,Rs2,Rs3 right
Start the layout by first placing the power components: to the pads of output inductor Lo1,Lo2,Lo3. Connect the
other node of current sensing capacitors Cs1,Cs2,Cs3
(1) Place the high side MOSFET Q1 and low side together and directly connect to the output voltage ter-
MOSFET Q2 as close to each other as possible so that minal, which is also the sensing point for output voltage
the source of Q1 and drain of Q2 has the most possible feedback sensing.
shortest length.
(10) Place feedback resistors (RFB1 and RFB2) close to IC
(2) Place a capacitor (Electrolytic or ceramic or both) and place compensator network close to Comp pin. Note
close to the drain of Q1 and source of Q2.
that the resistor RFB1 and RFB2, can be used to set the
outputs slightly higher to account for the output drop at
the load due to the trace resistance.
(3). If needed, place a snubber RC circuit next to Q2.
Rev. 1.4
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15
IRU3055
Component Connection
• No data bus should be passing through the switching
regulator especially close to the fast transition nodes
such as PWM drivers or the inductor voltage.
•
If possible, using four layer board, dedicate one layer
to ground, another layer as power layer for the constant
power input and output such as 5V, 12V, and 1.5V out-
put. Connect all grounds to the ground plane using di-
rect vias to the ground plane.
•
Use large and low impedance/low inductance PCB
plane to connect the high current path connections ei-
ther using component side or the solder side. These
connections include:
(a) Input capacitor to the drain of high side MOSFET
Q1, Q3 and Q5.
(b) The interconnection between source of high side
MOSFET such as Q1 and low side MOSFET such
as Q2.
(c) From drain of low side MOSFET to output Induc-
tor .
(d) From output inductor to output capacitor. Make
sure the impedance from output inductor to output
voltage slot (also the voltage feedback sensing point)
are as identical or symmetrical as possible.
(e) From each output capacitor to output slot.
(f) From input inductor to input capacitor.
Connect the rest of the components using the shortest
trace possible.
Rev. 1.4
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16
IRU3055
TEST WAVEFORMS FOR TYPICAL APPLICATION (1)
Figure 14 - 3-Phase inductor current at 60A load,
Ch1, Ch2 and Ch3: 10A/div. Ch4: gate signal.
Figure 17 - Zoomed 60A Load dynamic (rising).
Ch3: Output voltage, 100mV/div, AC.
Ch4: Load current, 20A/us, sensed by 2mΩ resistor, 25A/div.
Vss
VCORE
PGood
Figure 15 - Soft-start, Vcore and PGood.
Figure 18 - 60A load dynamic waveforms with three-phase
inductor current.
Ch1, Ch2 and Ch3: Inductor current, 10A/div.
Ch4: Load current, 20A/us, sensed by 2mΩ resistor, 25A/div.
Figure 16 - 60A Dynamic load response with 20A/µs slew rate.
Ch3: Output voltage, 100mV/div, AC.
Figure 19 - 60A load dynamic waveforms with three-phase
inductor current. (Zoomed)
Ch1, Ch2 and Ch3: Inductor current, 10A/div.
Ch4: Load current, 20A/us, sensed by 2mΩ resistor, 25A/div.
Ch4: Load current, 20A/us, sensed by 2mΩ resistor, 25A/div.
Rev. 1.4
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17
IRU3055
TYPICAL APPLICATION (2)
For Intel Pentium 4 processor with Vcc VID generation and active voltage droop
12V
C3
1uF
C4
1000uF
D1
C1
1uF
L1
1uH
C2
0.1uF
V
CL1
5V
Vcc
V
CL23
C6
6x 1500uF
C5
1uF
Q1
IRF3704S
HDrv1
R1
OCSet1
L2
1uH
2.2K
Ref
Rt
Q2
IRF3711S R2
1.5K
LDrv1
PGnd1/
OCGnd
C8
1uF
CS1
1.5V / 60A
Q3
IRF3704S
HDrv2
SS
L3
1uH
IRU3055
C9
1uF
C10
0.1uF
R3
47K
Q4
IRF3711S
LDrv2
R4
1.5K
D4
D3
D2
D1
D0
PGnd2
C11
1uF
CS2
Q5
IRF3704S
HDrv3
L4
1uH
Q6
IRF3711S
LDrv3
R5
1.5K
PGnd3
R6
27K
C12
Comp
C13
1uF
22nF
C7
CS3
Fb
100pF
(Optional)
C14
8x 2700uF
R22
R7
2.2K
80K
R10
R9
2.2K
R8
2.2K
1K
C15
R11
1.07K
5V
1uF
R12
40K
R13
U2D
1/4 LM324
R16
3.24K
U2C
1/4 LM324
Q9
2N3904
R15
40K
U2B
1/4 LM324
4.7K
R14
10K
R17
C16
0.47uF
5V
R18
4.7K
5V
Ref 2V
C17
0.1u
1MΩ
R19
40K
VID Good
3.3V
Q8
2N3904
U2A
1/4 LM324
Q7
2N3904
R20
60K
C18
47nF
VID 1.2V
R21
1K
C19
15uF
Figure 20 - Application circuit of IRU3055 to implement active voltage droop
as well as the 1.2V VID voltage with VccVID Power Good.
Rev. 1.4
08/13/02
www.irf.com
18
IRU3055
PARTS LIST FOR TYPICAL APPLICATION (2)
Ref Desig Description
Q1,Q3,Q5 MOSFET
Q2,Q4,Q6 MOSFET
Value
20V, 9mΩ
Qty
3
Part#
IRF3704S
Manuf
Web site (www.)
IR
IR
IR
IR
irf.com
20V, 6mΩ
Synchronous PWM
3
1
1
IRF3711S
IRU3055
BAT54S
U1
Controller
D1
Schottky Diode In Series
L1
L2,L3,L4
Inductor
Inductor
1µH
1µH
1
3
Z9479-A
Coilcraft
coilcraft.com
T60-18 Core, 6-turns
#14 AWG wire
ECJ-3YB1E105K
ECJ-2VF1E104Z
ECJ-3VF1C105Z
C1
C2,C10
Cap, Ceramic 1µF, X7R, 25V
Cap, Ceramic 0.1µF, Y5V, 25V
1
2
6
Panosonic maco.panasonic.co.jp
Panosonic
Panosonic
C3,C5,C9, Cap, Ceramic 1µF, Y5V, 16V
C8,C11,C13
C4
C6
Cap,Electrolytic 1000µF, 16V
Cap,Electrolytic 1500µF, 16V
Cap (Optional) 100pF, X7R, 50V
Cap, Ceramic 22nF, 50V
1
6
1
1
8
1
3
1
1
Any
EEU-FJ1C152U
Panosonic maco.panasonic.co.jp
C7
ECU-V1H101KBN Panosonic
Panosonic
C12
C14
R1
Cap,Electrolytic 2700µF,6.3V,13mW
EEU-FJ0J272U
Panosonic
Any
Any
Resistor
2.2K, 1%
1.5K, 1%
47K, 1%
27K, 5%
R2,R4,R5 Resistor
R3
R6
Resistor
Resistor
Any
Any
Q7,Q8,Q9 NPN Transistor
U2A,B,C,D OPAMP
3
1
1
1
1
1
1
3
2
2
1
3
2N3904
LM324
ECJ-2YB1C105K
ECJ-2YB1C474K
ECJ-2VF1E104Z
ECJ-2VF1E473K
Any
Any
C15
C16
C17
C18
C19
Cap, Ceramic 1µF, X7R, 16V
Cap, Ceramic 0.47µF, X7R, 16V
Cap, Ceramic 0.1µF, Y5V, 25V
Cap, Ceramic 47nF, X7R, 16V
Cap, POSCAP 15µF, 6.3V
Panosonic maco.panasonic.co.jp
Panosonic
Panosonic
Panosonic sanyo.com
Sanyo
Any
Any
R7,R8,R9 Resistor
2.2K, 1%
4.7K, 5%
R13,R18
R10,R21
R11
R12,R15,
R19
Resistor
Resistor
Resistor
Resistor
1K, 1%
1.07K, (tuned), 1%
40K, 1%
Any
Any
Any
R14
R16
Resistor
Resistor
Resistor
Resistor
Resistor
10K, 1%
3.24K, (tuned), 1%
1MΩ, 1%
60K, 1%
80K, 1%
1
1
1
1
1
Any
Any
Any
Any
Any
R17
R20
R22
Rev. 1.4
08/13/02
www.irf.com
19
IRU3055
Introduction to Intel Specification
With this simple circuit, the output voltage will linearly
decrease as load current increases. The output voltage
will fall in Intel spec. The resistor ratio “c” will determine
the slope of the voltage-current load line. The resistor
ratios “d” and “e” determine the offset voltage.
Vo
VSET
V
O(MAX)
In an ideal case, these parameters can be calculated
VOFFSET
by:
Rs
KLOAD - Rs
c =
V
O(TYP)
V
O(MIN)
KLOAD
Rs
Vc
VOFFSET
d =
e =
×
Vc
VOFFSET
Io
Figure 21 - The Intel specification for the load line.
Where Rs is equivalent current sensing resistors.
According to the Intel spec, the output voltage is depen-
dent on the load current. When the current goes up, the For a 3-phase converter with inductor current sensing:
voltage goes down. The characteristic can be modeled
by the following:
RL
3
Rs =
Where RL is the DC resistance of the inductor.
Vo = VSET - VOFFSET - KLOAD×Io
---(10)
Where VOFFSET is the offset voltage and KLOAD is the In practice, the resistor ratios “c” and “d” have to be tuned
slope of load line.
in order to take some parasitic parameters such as PCB
layout trace into account.
Rearrangement results in:
Component selection guide
VSET = Vo + VOFFSET + KLOAD×Io
---(11)
The implementation circuit is shown in Fig.20, Resistor
R7, R8, R9 and capacitor C15 configures a inductor cur-
rent losses sensing network to sense the load current.
(Attn: The C15 and R11 must connect directly to the
output terminal.) The RC networks that sense the induc-
tor current have to satisfy the following:
For Intel spec:
VOFFSET = 25mV
KLOAD = 98mV/45A = 2.18mΩ
Implementation of Voltage Droop with IRU3055
With a single single-ended OPAMP, the IRU3055 can
achieve voltage droop function as shown in Figure 22.
(R/3)×C = L/RL
The voltage Vc is a constant voltage such as 2V or 5V. For example, in the application circuit in Figure 20, the
The signal Vo+Rs×Io can be from inductor current sens- inductor is 1µH and the DC resistance is 1.6mΩ. If the
ing. The real application circuit is shown in Figure 20.
filter capacitor C15 is chosen to be 1µF, then the cur-
rent sensing resistors R7, R8 and R9 are:
e x R1
R = 3×L/RL/C
IRU3055
R = 3×1µH/1.6mΩ/1µF = 1.87K
R1
Because the given inductor is larger at zero current (it is
1.3µH at 0 current). A large resistor has to be taken.
c x R1
Vo
VFB
R2/d
R2
In the application circuit in Figure 20, R7,R8 and R9=2.2K.
Select R17 (referring to R2 in Figure 22) to be 1MΩ if we
consider the input bias of OPAMP LM324. Select R10
(referring to R1 in Figure 22) to be 1KΩ.
Vo+(Rs x Io)
Vc
(constant voltage)
VSET
R10=1K and R17=1MΩ
Figure 22 - Implement voltage droop
with a single OPAMP.
Connect the voltage Vc to 2V reference voltage shown in
Figure 20.
Vc=2V
Rev. 1.4
08/13/02
www.irf.com
20
IRU3055
Calculating R22 (referring to e×R1 in Figure 22) by the The test data is displayed in Figure 23. The DAC input is
provided equation, we get
01110, which refers to output voltage 1.5V. The mea-
sured DAC output VSET is 1.490V. The measured output
voltage versus load current falls into the Intel specifica-
R22 = R17×Vc/VOFFSET = 1K×2V/25mV = 80K
The resistor R11 and R16 (referring to c×R1 and d×R2 tion as shown in Figure 23.
in Figure 22) have to be tuned. From the suggested equa-
tion, they are in a few KΩ range. Because resistor R11 In this figure, at light load, the output voltage almost
and R16 function independent, they can be tuned sepa- follows the Intel typical specification. At 40A, 50A and
rately. First, connect the board and make the board work 60A loads, the output voltage is a slight deviation from
first. Put no load in the output. Then replace R16 with a the typical Intel spec. The reason is because the induc-
5K~20K potentiometer and adjust the potentiometer so tors get hot at high current loads. The resistance in-
as the output voltage is about 25mV lower than the DAC creases comparing with low load condition. As a result,
output setting. Because the output current is zero, the there is more voltage droop than the theoretical predic-
resistor R11 will not affect the output voltage. The DC tion, because the specification at high current has larger
offset is only dependent on R16. Select R16 with the tolerance. The Intel specification can be satisfied easily
tuned potentiometer value.
with the proposed circuit.
After R16 is tuned, replace R11 with a potentiometer. Implement the 1.2V VID Regulator
Connect the output voltage to certain current load (for If a Quadra-OPAMP such as LM324 is used, the addi-
example, half of the nominal load, 30A). Adjust the po- tional 1.2V VID regulator as well as the power sequence
tentiometer so that the output voltage has the same volt- can be implemented. In application circuit Figure 20,
age drops as Intel spec requests (for example, 95mV one OPAMP and a NPN transistor 2N3904 implement a
drop comparing with zero current condition). Then se- 1.2V, 30mA VID voltage regulator. The VID voltage is
lect R11 with tuned potentiometer value.
also sent to the minus input of one OPAMP. When the
VID voltage reaches 1V, the OPAMP changes to high
state and starts to charge up the RC network. The Re-
sistor R15 and the capacitor C16 function as a delay
network. 40K and 0.1µF will give about 1ms delay. In
the application circuit, C16=0.47µF, which gives about
5ms delay for a better illustration. When the voltage
across capacitor C16 reaches 1V, the OPAMP will turn
off the two NPN transistors. The soft-start capacitor of
IRU3055, C10, starts to be charged up and output volt-
age, Vo, will smoothly go into steady state.
Comparison of Test Data with Intel Spec
1.55
1.5
1.45
1.4
1.35
1.3
1.25
0
10
20
30
40
50
60
O U T
I
(A)
Vomax(Intel spec)
Vo(typical Intel spec)
Vomin (Intel spec)
Experiment Vo (steady state)
Vset (experiment)
Figure 23 - Test steady state output voltage for the
circuit of IRU3055 with active droop.
Rev. 1.4
08/13/02
www.irf.com
21
IRU3055
EXPERIMENT WAVEFORMS FOR TYPICAL APPLICATION (2)
Figure 24 - Soft-start.
Ch1: 1.2V VID. Ch2: VID Good.
Ch3: 1.5V Output. Ch4: PGood.
Figure 25 - 60A Load dynamic with 20A/µs slew rate.
Ch4: Output current, sensed through 2mΩ resistor, 25A/div.
Ch3: Ouput voltage, DC offset 1.3V, 100mV/div.
Figure 26 - 3-Phase inductor current at 60A load,
Ch1, Ch2 and Ch3: 10A/div and gate signal.
Rev. 1.4
08/13/02
www.irf.com
22
IRU3055
TYPICAL APPLICATION (3)
Q7
R7
R8
1K
D1
10Ω
C15
1uF
C 1
D3
12V
1uF
C 2
1uF
Battery
19V
C3
L1
1uF
VCL1
CL23
HDrv1
5V
Vcc
1uH
V
C 6
C 5
Q1
C 4
6x 1500uF
1uF
IRF3704S
1000uF
D2
1N4148
L2
R 1
2.2K
Ref
Rt
OCSet
LDrv1
2uH
Q2
IRF3711S
R 2
PGnd1/
OCGnd
3.3K
C 8
CS1
1.5V / 60A
1uF
Q3
HDrv2
SS
L3
IRF3704S
IRU3055
C 9
R 3
C10
2uH
1uF
47K
0.1uF
Q4
LDrv2
IRF3711S
R 4
D 4
D 3
D 2
D 1
3.3K
PGnd2
C11
CS2
1uF
Q5
HDrv3
L4
2uH
IRF3704S
Q6
D 0
LDrv3
IRF3711S
R 5
3.3K
PGnd3
R 6
C12
22nF
C13
1uF
Comp
CS3
Fb
20K
C14
8x 2700uF
Figure 26 - Typical application of IRU3055 in notebook application.
Rev. 1.4
08/13/02
www.irf.com
23
IRU3055
PARTS LIST FOR TYPICAL APPLICATION (3)
Ref Desig Description
Q1, Q3, Q5 MOSFET
Q2, Q4, Q6 MOSFET
Value
20V, 9mΩ
Qty
3
Part#
IRF3704S
Manuf
Web site (www.)
irf.com
IR
IR
20V, 6mΩ
3
IRF3711S
Q7
U1
NPN Transistor
Controller
1
1
2N3904
IRU3055
Any
IR
Synchronous PWM
irf.com
D1
D2
D3
Schottky Diode In Series
Diode
Zener Diode
1
1
1
BAT54S
1N4148
1N5242A
IR
Any
Any
Coilcraft
L1
L2,L3,L4
Inductor
Inductor
1.3µH
2µH, 15A
1
3
Z9479-A
coilcraft.com
T60-18 Core, 6-turns
#14 AWG wire
ECJ-3YB1E105K
ECJ-2VF1E104Z
ECJ-3VF1C105Z
C1
Cap, Ceramic 1µF, X7R, 25V
Cap, Ceramic 0.1µF, Y5V, 25V
Cap, Ceramic 1µF, Y5V, 16V
1
2
7
Panosonic maco.panasonic.co.jp
Panosonic
Panosonic
C2, C10
C3,5,8,9,
11,13,15
C4
Cap,Electrolytic 1000µF, 16V
Cap,Electrolytic 1500µF, 16V
Cap, Ceramic 22nF, X7R, 50V
Cap,Electrolytic 2700µF,6.3V,13mΩ
1
6
1
8
1
3
1
1
1
Any
C6
EEU-FJ1C152U
Panosonic maco.panasonic.co.jp
C12
C14
R1
ECU-V1H223KBG Panosonic
EEU-FJ0J272U
Panosonic
Any
Resistor
2.2K, 1%
3.3K, 1%
47K, 1%
20K, 1%
10Ω, 5%
R2,R4,R5 Resistor
Any
Any
Any
R3
R6
R7
Resistor
Resistor
Resistor
Any
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.4
08/13/02
www.irf.com
24
IRU3055
(Q) QSOP Package, Wide Body
36-Pin
H
A
P
B
B1
R1
D E
R
DETAIL-A
L
C
PIN NO. 1
DETAIL-A
J
0.50±0.05
K
F
G
36-PIN
MIN
SYMBOL
MAX
A
B
15.20 15.40
0.85
0.80 REF
B1
C
D
E
0.28
7.40
10.11
2.44
0.10
0.51
7.60
10.51
2.64
0.30
F
G
H
J
78 TYP
0.23
08
0.32
88
K
L
0.40
0.63
1.27
0.89
R
R1
P
0.20±0.05
78±38
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 1.4
08/13/02
www.irf.com
25
IRU3055
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
Q
QSOP Plastic, Wide Body
36
---
1500
Fig A
1
1
1
Feed Direction
Figure A
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.4
08/13/02
www.irf.com
26
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