IRU3072C_技术文档

Data Sheet No. PD94698

IRU3072

20-PIN SYNCHRONOUS PWM CONTROLLER/

3 LDO CONTROLLER

FEATURES

DESCRIPTION

Synchronous Controller plus 3-LDO controllers

Current Limit using MOSFET Sensing

The IRU3072 controller IC is designed to provide a low

cost synchronous Buck regulator for on-board DC to DC

converter for multi-output applications. The outputs can

be programmed as low as 0.8V for low voltage applica-

Dual Soft-Start Function allows power sequencing

Single 5V/12V Supply Operation

Programmable Switching Frequency up to 400KHz tions.

Fixed Frequency Voltage Mode

1A Peak Output Drive Capability

The IRU3072 features dual soft-starts which allows power

sequencing between outputs.

Over current limit is provided by using external MOSFET's

on-resistance for optimum cost and performance.

This device features a programmable frequency set from

200KHz to 400KHz, under-voltage lockout for all input

supplies, dual external programmable soft-start functions

as well as output under-voltage detection that latches

off the device when an output short is detected.

APPLICATIONS

Graphic Card

DDR memory source sink VTT application

Applications with Multiple Outputs

Low cost on-board DC to DC such as

5V to 3.3V, 2.5V or 1.8V

Hard Disk Drive

TYPICAL APPLICATION

3.3V

Vcc

V

SEN33 / SDB

+5V

C1

1uF

Q1

Drv2

Fb2

R1

V

OUT2

2.5V

2.15K

C2

R2

1K

10uF

Q2

VccLDO

Vc

C3

1uF

Drv3

Fb3

D1

R3

VOUT3

1.8V

L1

1.25K

C4

10uF

R4

1K

VIN=12V

1uH

C7

2x 47uF,16V

U1

IRU3072

C6

0.1uF

C5

1uF

C8

10uF

Q3

Drv4

Fb4

R5

V

OUT4

1.5V

Q4

IRF7460

866Ω

HDrv

C9

10uF

R6

1K

L2

1uH

R7

OCSet

LDrv

V

OUT1

1.2V @ 8A

C10 220pF

6.81K

Q5

IRF7460

R8

C12

3x 330uF, 40m

6TPB330M, Poscap

C11

15nF

Comp

Ω

3.3K

R9

46.4K

R10

499Ω

Rt

SS1

Fb1

C13

0.1uF C14

33nF

R11

1K

SSLDO

Gnd

PGnd

Figure 1 - Typical application of IRU3072.

PACKAGE ORDER INFORMATION

TA (°C)

DEVICE

PACKAGE

0 To 70

IRU3072CH

20-Pin MLPQ 4x4 (H)

Rev. 1.0

3/25/04

www.irf.com

1

IRU3072

ABSOLUTE MAXIMUM RATINGS

Vcc and VccLDO Supply Voltage .............................. 25V

Vc Supply Voltage .................................................... 25V

Storage Temperature Range ...................................... -65°C To 150°C

Operating Junction Temperature Range ..................... 0°C To 125°C

CAUTION: For all pins, voltage should not be below -0.5V.

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.

PACKAGE INFORMATION

20-PIN MLPQ 4x4 (H)

θJA=468C/W

20

19

18

17

16

1

2

3

4

5

15

14

13

12

11

Drv4

Drv3

Comp

Fb1

Rt

Drv2

VSEN33/SDB

VccLDO

Vcc

OCSet

6

7

8

9

10

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, the typical specification value applies over Vcc=5V, Vc=12V, VccLDO=5V and

TA=25°C. the Min and Max limits apply to the temperature range from 0 to 70°C. Low duty cycle pulse testing is

used which keeps junction and case temperatures equal to the ambient temperature.

PARAMETER

SYM

TEST CONDITION

MIN

TYP MAX UNITS

Feedback Voltage

Fb Voltage Line Regulation

UVLO

VFB

LREG

0.784

0.8

0.2

0.816

0.625

V

%

5<Vcc<12

UVLO Threshold - Vcc

UVLO Hysteresis - Vcc

UVLO Threshold - Vc

UVLO Hysteresis - Vc

UVLO Threshold - VccLDO

UVLO Hysteresis - VccLDO

UVLO Threshold - VSEN33

UVLO Hysteresis - VSEN33

UVLO VCC Supply Ramping Up

UVLO VC Supply Ramping Up

UVLO VCCLDO Supply Ramping Up

UVLO VSEN33 Supply Ramping Up

3.8

3.2

4.2

0.25

3.5

0.2

2.5

0.15

1.27

0.07

0.4

4.6

3.8

V

2.25

1.17

0.3

2.75

1.37

0.5

UVLO Threshold - Fb1, 2, 3, 4 UVLO Fb1 Fb Ramping Down

UVLO Hysteresis - Fb1, 2, 3, 4

0.02

Supply Current

Vcc Dynamic Supply Current

Vc Dynamic Supply Current

Vcc Static Supply Current

Vc Static Supply Current

Dyn ICC

Dyn IC

ICCQ

Freq=200KHz, CL=3000pF

SS=0V

11

5

14

8

mA

ICQ

SS=0V

3

5

Rev. 1.0

3/25/04

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2

IRU3072

PARAMETER

SYM

TEST CONDITION

MIN

TYP MAX UNITS

Soft-Start Section

Charge Current

Error Amp

Fb Voltage Input Bias Current

Transconductance

Oscillator

SS IB1,IB2 SS1=SS2=0V

15

25

0.1

900

35

µA

IFB1

IFB2

SS1=3V

SS1=0V

1

75

µA

35

500

1300 µmho

Frequency

Freq

VRAMP

Tr

Rt=100K

Rt=39K

Note 1

170

340

200

400

1.27

230

460

KHz

VPP

ns

Ramp Amplitude

Output Drivers

Rise Time

CLOAD=3000pF (10% to 90%)

Vcc=12V

CLOAD=3000pF (90% to 10%),

Vcc=12V

Vcc=12V, CLOAD=3000pF

HDrv falls,LDrv rises

Vcc=12V, CLOAD=3000pF

LDrv falls, HDrv rises

Fb=0.7V, Freq=200KHz

Fb=0.9V

50

100

150

100

99

Fall Time

Tf

ns

Dead Band Time 1

Dead Band Time 2

TDB

50

20

85

115

50

ns

Max Duty Cycle

Min Duty Cycle

DMAX

DMIN

92

0

%

LDO Controller Section

Drive Current

Fb Voltage

Input Bias Current

Thermal Shutdown

Current Limit

Drv2, 3 and 4

Note 1

40

0.784

60

0.8

0.5

150

mA

V

µA

8C

0.816

2

OC Threshold Set Current

OC Comp Off-Set Voltage

IOCSET

23

-7

30

0

37

+7

µA

mV

VOC(OFFSET)

Note 1: Guaranteed by design but not tested in production.

PIN DESCRIPTIONS

PIN# PIN SYMBOL

PIN DESCRIPTION

1

2

3

4

5

Drv4

Drv3

Drv2

VccLDO

Vcc

Outputs of the linear regulator controllers.

This pin provides power for the LDO controllers.

This pin provides biasing for the internal blocks of the IC as well as power for the low side

driver. A minimum of 1µF, high frequency capacitor must be connected from this pin to

ground to provide peak drive current capability.

6

7

LDrv

Gnd

Output driver for the synchronous power MOSFET.

This pin serves as the ground pin and must be connected directly to the ground plane. A

high frequency capacitor (0.1 to 1µF) must be connected from Vcc, Vc and VccLDO pins

to this pin for noise free operation.

8

9

PGnd

HDrv

This pin serves as the separate ground for MOSFET's driver and should be connected to

system's ground plane.

Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148,

from this pin to ground for the application when the inductor current goes negative (Source/

Sink), soft-start at no load and for the fast load transient from full load to no load.

Rev. 1.0

3/25/04

www.irf.com

3

IRU3072

PIN# PIN SYMBOL

PIN DESCRIPTION

10

Vc

This pin is connected to a voltage that must be at least 4V higher than the bus voltage of

the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A

minimum of 1µF, high frequency capacitor must be connected from this pin to ground to

provide peak drive current capability.

11

OCSet

This pin is connected to the Drain of the synchronous MOSFET and it provides the posi-

tive sensing for the internal current sensing circuitry. An external resistor programs the

current sense (CS) threshold depending on the RDS of the power MOSFET.

This pin is used to monitor the 3.3V rail. This pin can be pulled-low to shutdown the

outputs.

12

VSEN33/SDB

13

14

Rt

Fb1

This pin sets the switching frequency with a resistor to Gnd.

This pin is connected directly to the output of the switching regulator via resistor divider to

provide feedback to the Error amplifier.

15

16

Comp

SS1

Compensation pin of the error amplifier. An external resistor and capacitor network is

typically connected from this pin to ground to provide loop compensation.

This pin provides soft-start for the switching regulator. An internal current source charges

an external capacitor that is connected from this pin to ground which ramps up the output

of the switching regulator, preventing it from overshooting as well as limiting the input

current.

17

SSLDO

This pin provides soft-start for the LDO controllers. An internal current source charges an

external capacitor that is connected from this pin to ground which ramps up the output of

the LDO controller, preventing it from overshooting as well as limiting the input current.

These pins provide feedback for the linear regulator controllers.

18

19

20

Fb2

Fb3

Fb4

Rev. 1.0

3/25/04

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4

IRU3072

BLOCK DIAGRAM

3V

12

VSEN33 / SDB

Bias

Generator

1.27V

0.8V

20uA

1.27V / 1.2V

4.2V / 4.0V

POR

64uA

Max

64uA

Max

64uA

Max

UVLO

Vcc

Vc

17

16

SSLDO

3V

3.5V / 3.3V

2.5V / 2.35V

VccLDO

20uA

64uA

Max

13 Rt

SS1

10 Vc

Rt

Ct

Oscillator

Enbl

9

HDrv

POR

S

R

ErrorComp

Q

Comp 15

0.8V

ErrorAmp

25K

5

6

Vcc

Reset Dom

LDrv

PGnd

Fb1 14

3V

0.4V

20uA

8

7

CSComp

POR

64uA×

25K=1.6V

When SS=0

11

OCSet

FbLo Comp

Gnd

4

VccLDO

0.8V

3

2

1

Drv2

Drv3

Drv4

25K

18

Fb2

25K

19

Fb3

Fb4 20

Figure 2 - Simplified block diagram of the IRU3072.

Rev. 1.0

3/25/04

www.irf.com

5

IRU3072

TYPICAL APPLICATION

3.3V

Vcc

VSEN33 / SDB

+5V

C1

1uF

Q1

Drv2

Fb2

R1

VOUT2

2.5V

2.15K

C2

10uF

R2

1K

VccLDO

Vc

C3

1uF

Q2

Drv3

Fb3

D1

R3

VOUT3

1.8V

L1

1.25K

C4

10uF

R4

1K

VIN=12V

1uH

C7

2x 47uF,16V

U1

IRU3072

C5

1uF

C6

0.1uF

C8

10uF

Q3

Drv4

Fb4

R5

VOUT4

1.5V

Q4

IRF7460

866Ω

HDrv

C9

10uF

R6

1K

L2

R7

OCSet

LDrv

VOUT1

1.2V @ 8A

1uH

C10 220pF

6.81K

Q5

IRF7460

R8

C12

3x 330uF, 40m

6TPB330M, Poscap

C11

15nF

Comp

Ω

3.3K

R9

46.4K

Rt

R10

499

Ω

SS1

Fb1

C13

0.1uF C14

33nF

R11

1K

SSLDO

Gnd

PGnd

Figure 3 - Typical application of IRU3072.

PARTS LIST

Ref Desig Description

Q1,Q2,Q3 MOSFET

Value

Qty

3

2

1

2

3

1

2

1

3

1

3

1

Part#

IRLR2703

IRF7460

IRU3072

BAT54S

DS1608C-102

DO3316P-102HC

ECJ-2VF1C105Z

Manuf

Web site (www.)

irf.com

30V, 65mΩ, 22A

20V, 10mΩ, 12A

Synchronous PWM

IR

Q4,Q5

U1

MOSFET

Controller

D1

Schottky Diode 0.2A, 30V

L1

L2

C1,C3

Inductor

Capacitor

1µH, 2A

Coilcraft

coilcraft.com

1µH

1µF, Y5V, 16V

10µF

1µF, X7R, 25V

0.1µF, Y5V, 25V

47µF, 16V

10µF

220pF, X7R

15nF

330µF, 6.3V, 40mΩ

33nF, X7R

2.15K, 1%

1K, 1%

1.25K, 1%

866Ω, 1%

6.81K, 1%

3.3K, 1%

46.4K, 1%

499Ω, 1%

1K, 1%

Panasonic maco.panasonic.co.jp

C2,C4,C9 Capacitor

C5

C6,C13

C7

Capacitor

Resistor

ECJ-3YB1E105K

ECJ-2VF1E104Z

16TPB47M

Panasonic

Sanyo

Any

sanyo.com

C8

C10

C11

C12

C14

R1

ECU-V1H221KB

ECJ-2VB1H153K Panasonic

6TPB330M Sanyo

Panasonic maco.panasonic.co.jp

sanyo.com

ECJ-2VB1H333K Panasonic maco.panasonic.co.jp

Any

R2,R4,R6 Resistor

R3

R5

R7

R8

R9

R10

R11

Resistor

Rev. 1.0

3/25/04

www.irf.com

6

IRU3072

APPLICATION INFORMATION

The IRU3072 controller IC is designed to provide a low The IRU3072 senses four voltages with under-voltage

cost synchronous Buck regulator for on-board DC to DC lockout (UVLO) block. The voltages Vcc, Vc and VccLDO

converter as well as three linear regulator controllers. It are sensed through the UVLO block. The LDO input volt-

is specially designed for multiple output applications. age can be sensed through pin VSEN33. Although syn-

The outputs can be programmed as low as 0.8V.

chronous bus voltage (VBUS) is not sensed, in practical,

it can be sensed indirectly. Typically, only two or three

The IRU3072 provides two separate soft-starts. It not input voltages are available. Some of the five input volt-

only allows different output power sequences, but also ages have to either share or be generated by another

allows shutdown of LDO and PWM output regulators method such as charge pump. One example of IRU3072

individually.

application with only two input voltages, 5V and 3.3V, is

shown in figure 5. In this example:

The IRU3072 provides cycle-by-cycle current limit and

output feedback under-voltage lockout.

VBUS = Vcc = 5V

Vc = VccLDO created by charge pump

VSEN33 = 3.3V

Power Sequence and Under-Voltage Lockout

For correct operation, proper power sequence should be The IRU3072 will sense all four voltages to ensure all

ensured. Typically, there are four or five input voltages these voltages enter into steady state before the soft-

involved.

start capacitor is charged up. The operation waveforms

are shown in Figure 6.

Vcc: IC biasing voltage.

VSEN33: LDO Input voltage, for example 3.3V

VccLDO: Input biasing voltage for IRU3072 internal

LDO controller.

VBUS: Input voltage for synchronous buck converter.

Vc: Input biasing voltage for IRU3072 internal high

side MOSFET drivers.

3.3V

V

SEN33 / SDB

Drv2

Fb2

U1

IRU3072

The power sequence should be proper such that soft-

start capacitors (for both LDO and PWM) start to be

linearly charged up right after the above five voltages enter

into steady state, as shown in the following figure.

Vcc

VccLDO

UVLO

L1

VBUS=5V

Vc

C6

UVLO Threshold Voltage

Input Voltage

V

CC,VCCLDO,

BUS,Vc, etc

Soft-Start

SS1

HDrv

Q4

Q5

L2

VOUT1

R7

OCSet

LDrv

C10

Soft-Start Voltage

for PWM VSS

SSLDO

Soft-Start Voltage

for LDO VSSLDO

Figure 5 - IRU3072 application with only two

power inputs: 5V and 3.3V.

Figure 4 - Desired power sequence.

Rev. 1.0

3/25/04

www.irf.com

7

IRU3072

The soft-start operation can ensure the output voltage

ramps up to the regulated voltage without surge of the

current. The IRU3072 also has an output feedback UVLO

block, which will turn off both high side and low side

MOSFET driver when the voltage at pin Fb1,Fb2,Fb3 or

Fb4 is below 0.4V. The feedback UVLO is used to pro-

tect the system when the output is in short circuit. How-

ever, during the power on of the buck converter, the out-

put of buck converter starts from zero and the voltage at

pin Fb1 will be below 0.4V. The feedback UVLO should

be disabled when soft-start capacitor voltage ramps up

and down. This is achieved by injecting a current into

the Fb1 pin (also Fb2, Fb3 and Fb4) during the soft-start

and the magnitude of this current is inversely propor-

tional to the voltage at soft-start pin (SS or SSLDO). The

diagram is shown in Figure 7 and operation waveforms

are shown in Figure 8. The operation principle is as

Figure 6 - Power sequence.

If there are three input voltage sources available, such follows:

as 3.3V, 5V and 12V, the possible connections to en-

sure proper operation are shown in the following table.

Initially, the buck converter’s output voltage and the volt-

age at pin Fb1 are both zero. The voltage at soft-start pin

“SS” is almost zero and about 64µA current will inject to

the pin of Fb1 through a 25KΩ internal resistor. The

voltage at the negative input of Error Amplifier and the

positive input of the feedback UVLO comparator is ap-

proximately:

Option Vcc VBUS

Vc

12V

CP

12V

VccLDO LDO Input

1

2

5V

12V

3.3V

3

4

12V 12V

12V 5V

more

64µA×25KΩ = 1.6V

3V

Table: Possible combination of input voltage source

connections to ensure proper start-up operation.

(CP refers to Charge Pump)

20uA

HDrv

SS1

64uA

Max

There are many possible combinations of input voltage

source connections and the table above lists only a few

of them. Most importantly for a proper power sequence,

the soft-start capacitor has to be charged up after all the

input voltage sources are established.

POR

Comp

0.8V

Error Amp

LDrv

25K

Soft-Start

One of the useful features of IRU3072 is that it allows

different start-up times for PWM output and LDO output

by programming two separate soft-start capacitors. Fig-

ure 7 just shows the soft-start for PWM section.

Fb1

0.4V

64uA

×

25K=1.6V

When SS=0

POR

Feeback

UVLO Comp

Figure 7 - IRU3072 soft-start diagram.

Rev. 1.0

3/25/04

www.irf.com

8

IRU3072

From the above analysis, the output start up time is the

period when soft-start capacitor voltage increases from

1V to 2V. The start up time will be dependent on the size

of the external soft-start capacitor. The start up time can

be estimated by:

Output of UVLO

POR

3V

@2V

@1V

Soft-Start

Voltage

0V

20µA×tSTART/CSS @ 2V-1V

64uA

For a given start up time, the soft-start capacitor can be

estimated as:

Current flowing

into Fb1 pin

0uA

CSS @ 20µA×tSTART/1V ---(1)

@

1.6V

Voltage at negative input

of Error Amp and Feedback

UVLO comparator

0.8V

For 5ms start up time, a 0.1µF soft-start capacitor is

required. In practice, the 20µA current will slightly de-

crease as the soft-start voltage goes up. Therefore, for a

0.1µF soft-start capacitor, start up time may be slightly

longer, e.g. 6ms.

0V

Voltage at Fb1 pin

Figure 8 - Theoretical operation waveforms

during soft-start.

The soft-start waveforms are shown in Figure 9. In this

figure, the start up time for the buck converter VOUT1 and

LDOs is different by selecting separate soft-start capaci-

When the power voltage such as Vcc go into steady tors.

state and the output of voltage UVLO “POR” goes high,

a 20uA current source charges the external soft-start

capacitors. The soft-start voltage ramps up. In the mean

time, the current flowing into pin Fb1 starts to decrease

linearly and so does the voltage at the positive pin of

feedback UVLO comparator and the voltage at the nega-

tive input of Error amplifier. When the soft-start capacitor

voltage is around 1V, the current flowing into the Fb1 pin

is approximately 32µA. The voltage at the positive input

of the Error amplifier is approximately:

For PWM: CSS = 0.1µF, tSTART @ 5ms

For LDOs: CSSLDO = 33nF, tSTART @ 2ms

32µA×25KΩ = 0.8V

The Error Amplifier will start to operate and the output

voltage starts to increase. As the soft-start capacitor

voltage continues to go up, the current flowing into the

Fb1 pin will keep decreasing. Because the voltage at pin

of Error Amplier is regulated to reference voltage 0.8V,

the voltage at the Fb1 pin is:

VFB1 = 0.8V-25KΩ×(Injecting Current)

The feedback voltage increases linearly as the injecting

current goes down. The injecting current drops to zero

when soft-start voltage is around 2V and the output volt-

age goes into steady state.

Figure 9 - Soft-start of buck converter

(PWM) and LDO.

Shutdown

The PWM output and LDO output can be turned on and

off individually by pulling up and down the correspond-

ing soft start capacitors.

Figure 8 shows that the voltage at the positive pin of

feedback UVLO comparator is always higher than 0.4V,

therefore, feedback UVLO is not functional during soft-

start.

Rev. 1.0

3/25/04

www.irf.com

9

IRU3072

(a). Shutdown and start up PWM output by controlling

soft start SS1. LDO output such as Vout2 will not be

affected.

Figure 11 - Operation waveforms when PWM

converter is shutdown by pulling

down the soft-start capacitor.

Both PWM output and LDO output can be shutdown by

pulling the pin VSEN33/SDB down. One example is shown

as follows.

External

Shutdown

3.3V

4.7K

VSEN33 / SDB

Drv2

Fb2

U1

IRU3072

Vcc

VccLDO

UVLO

L1

(b). Shutdown and start up LDO output by controlling

soft-start SSLDO. PWM output VOUT1 will not be affected.

VBUS=5V

Vc

C6

Figure 10 - Shutdown PWM or LDO by

controlling soft-start.

Soft-Start

SS1

HDrv

Q4

Q5

L2

V

OUT1

R7

OCSet

One issue related to shutdown of PWM output by pull-

ing down the soft-start, there is a small negative voltage

shown in the output during the shutdown. It is because

the low side MOSFET driver is on when the soft-start

capacitor voltage is pulling down. The output inductor

resonates with output capacitor and load. This occurs

especially often when output current is small (light load

or no load condition). The operation waveforms are shown

as follows.

LDrv

C10

SSLDO

Figure 12 - External shutdown by

using pin VSEN33/SDB.

Rev. 1.0

3/25/04

www.irf.com

10

IRU3072

The LDO and PWM output can be shutdown by using a

transistor to pull down the pin VSEN33/SDB as shown in

Figure 12. Because the VSEN33/SDB pin also senses the

LDO input voltage for the power UVLO block, a high im-

pedance resistor such as 4.7K has to be inserted be-

tween VSEN33/SDB pin and the input of LDO such as 3.3V.

The input voltage UVLO operation will not be affected

due to the high input impedance nature of VSEN33/SDB

pin. The operation waveforms is shown as follows:

3V

VBUS

IRU3072

20uA

Q1

VOUT

R

SET

L

CS Comp

OCSet

Enb

Oscillator

Q2

S

R

HDrv

Q

LDrv

Fb1

Rf1

Rf2

0.4V

Err Comp

Figure 14 - IRU3072 current limit diagram.

The operation is illustrated in Figure 15.

VREF

Feedback

voltage

0.4V

Figure 13 - Shutdown by pulling down pin VSEN33/SDB.

IOUT

FS(NOM)

Switching

frequency

One feature of shutdown by pulling down VSEN33/SDB is

that there is no negative voltage shown in the buck con-

verter output because both high side and low side

MOSFET drivers are off after shutdown.

DMAX

FS(NOM)

VOUT

FS(NOM)×VIN

High Side MOSFET

turn on time (tON)

IOUT

Over Current Protection

The IRU3072 over current protection is achieved with a

cycle-by-cycle current limit and an output voltage under-

voltage lockout scheme. The diagram is shown in Figure

14. It includes an over current comparator and an output

voltage UVLO comparator. The current is sensed through

the RDS(ON) of the low side MOSFET. A resistor, RSET, is

connected from OCSet pin to the drain of the low side

MOSFET in order to set the over-current limit. When the

low side MOSFET Q2 is ON, the inductor current flows

through MOSFET Q2. The voltage at OCSet pin is given

<IL>=IOUT

Average Inductor

Current

IO(NOM)

IO(LIM)

IOUT

Normal

operation

Over Current

Limit Mode

Shutdown

by UVLO

Figure 15 - Operation of IRU3072 current limit

and UVLO.

as:

During the normal operation mode, the synchronous buck

converter operates in fixed frequency FS(NOM), which is

VOCSet =20µA×RSET -iL×RDS(ON)

When voltage VOCSet is below zero, the current sensing the normal operation switching frequency and it is deter-

comparator flips and disables the oscillator. The high mined by the external resistor Rt. The output voltage is

side MOSFET is turned off and the low side MOSFET is regulated to the desired voltage and the feedback volt-

on until the inductor currents reduces to below current age is equal to the reference voltage VREF. The turn on

setting value. The critical inductor current can be calcu- time of the high side MOSFET is given as:

lated by setting:

tON(normal) @ D×TS(NOM) =VOUT/(FS(NOM)×VIN)

VOCSet = 20µA×RSET-iL×RDS(ON) = 0

ISET = iL(critical) = 20µA×RSET/RDS(ON) ---(2)

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IRU3072

As the load current goes up, the inductor current in- From Figure 16, first, the high side MOSFET is on for tON

creases and the high side MOSFET’s turn on time in- period and the inductor current increases during this time.

creases a little due to the voltage drop across the high Then, the high side MOSFET is off and low side MOSFET

side MOSFET RDS(ON).

is on. Because the inductor current is higher than the

critical inductor current ISET, the current sensing com-

As the output current increases to limit current, IL=IO(LIM), parator goes high and the low side MOSFET keeps on.

which is set by the resistor RSET. The buck converter will The inductor current is discharged by the output voltage.

go into cycle-by-cycle current limit mode. The operation When the inductor current is below setting current or

waveforms of IRU3072 during cycle-by-cycle current critical current ISET, the current sensing comparator goes

mode is shown in Figure 16.

low and enables the oscillator. The high side MOSFET

is turned on again and next cycle starts. The operation

frequency is only dependent on the current sensing com-

parator and the internal clock frequency is modified by

current limit.

iL(VALLEY)

L(PEAK)

i

iL(AVG)

Inductor

Current

ISET

In conclusion, from Figures 15 and 16, two big differ-

ences exist between normal operation and current limit

mode. First, during current limit mode, the valley induc-

tor current is determined by ISET .

Current Limit

Comparator Output

Internal Clock

ISET = iL(VALLEY)

MOSFET

Driver HDrv

Second, in Figures 15 and 16, the frequency in current

limit mode, is lower than normal operation frequency.

D×TS(NOM)

TS(NOM)

In general, the output current is represented by:

(a) Normal operation.

IOUT = iL(AVG)=iL(VALLEY)+∆IPK_PK/2

Where ∆IPK_PK is the peak to peak inductor current

ripple which is given by:

Internal Clock

∆IPK_PK = iL(PK)-iL(VALLEY) = (VIN-VOUT )×tON/L

at normal operation

Figure 15 shows that the operation frequency of the buck

converter decreases as output current goes up during

current limit mode. The on time of high side MOSFET is

controlled by the output voltage loop so that the voltage

at Fb pin, still equals the reference voltage, VFB=VREF.

The output voltage is regulated to the desired voltage.

Internal Clock

at current limit

i

L(PEAK)

Inductor

Current

i

L(AVG)

ISET=iL(VALLEY)

Current Limit

Comparator Output

As a result:

tON = VO(NOM)/VIN/FS

High Side MOSFET

Driver HDrv

(VIN-VO(NOM))×VO(NOM)

IOUT(Current Limit Mode) = ISET +

t

OFF

t

ON

(2×L×VIN×Fs)

(b). Operation at current limit mode.

Where VO(NOM) is the nominal output voltage and it is

determined by the feedback resistor and reference volt-

age as shown in Figure 14. The above equation indi-

cates that the operation frequency is inversely propor-

tional to the output current during the current limit mode.

For practical application, the most important is setting

up the over current limit threshold. From Figure 15, at

the current limit threshold IO(LIM), the frequency is still

equal to nominal operation frequency.

Figure 16 - Cycle-by-Cycle operation when IRU3072

is in over-current limit mode.

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IRU3072

FS = FS(NOM)

Therefore, the output current limit threshhold is set by:

∆IPK_PK(LIM)

IOUT(LIM) =I SET +

2

Where:

(VIN-VO(NOM))×VO(NOM)

(VIN×FS(NOM)×L)

∆IPK_PK(LIM) =

From equation (2), the over current limit set resistor can

be calculated by:

ISET ×RDS(ON)

RSET =

20µA

RSET = (IOUT(LIM)-∆IPK_PK(LIM)/2)×RDS(ON)/20µA ---(3)

(a). Normal operation.

Where RDS(ON) has to choose the maximum over the tem-

perature for the selected MOSFET. Overall, the profile of

current limit operation is shown in Figure 17.

Over

Current

Limit

Normal

Operation

Shutdown

by UVLO

Mode

FS(NOM)

Switching

Frequency

IO(LIM)

ISET

IO(MAX)

IOUT

Select inductor L, frequency FS(NOM), IO(LIM)

(VIN-VO(NOM))×VO(NOM)

Calculate:

DI

PK_PK(LIM)

=

V

IN× L×FS(NOM)

(b). Current limit mode.

Set: ISET = IO(LIM)

-

DIPK_PK/2

Figure 18 - Operation waveforms during normal

and current limit mode.

Select: RSET = ISET× RDS(ON)/20µA

Figure 17 - Profile of operation switching frequency

versus output current.

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IRU3072

450

400

350

300

250

200

150

100

50

Fs(measured)

Fs(predicted)

0

2

4

6

8

10

Iout (A)

Figure 19 - Profile of switching frequency versus

output current -predicted and measured.

Figure 18 (a) shows normal operation waveforms for a

12V input 1.6V output 400KHz buck regulator. During

normal operation, the switching frequency is 400KHz.

Figure 18 (b) shows the operation waveforms during cur-

Figure 20 - Operation waveforms when output

of buck converter is short to ground.

rent limit mode. The switching frequency is reduced and The output UVLO senses the four feedback pin voltages

output ripple increases. Figure 19 shows the profile of Fb1,Fb2,Fb3,Fb4. If any of the feedback voltages are

switching frequency versus output current. When the below 0.4V, all four outputs will be shutdown.

output current goes up and hit the over current limit, the

switching frequency starts to decreases. Due to the out-

put voltage loop, the output voltage will keep the regula-

tion except the ripple increases. As the output current

keeps going up. The output voltage will start to decrease

until the feedback voltage Fb is under 0.4V. The output

voltage under lockout takes over and turns off both high

side and low side MOSFET. The output voltage reduces

to zero.

Output Feedback UVLO

Besides the cycle-by-cycle current limit, an output feed-

back UVLO is included in the IRU3072 for the output

short protection. The diagram is shown in Figure 14. If

the output is short or overload, once the voltage at the

Fb1 pin is below 0.4V, the output feedback UVLO com-

parator will flip and turn off both high side and low side

MOSFETs. The output of converter will decrease to zero.

The operation when PWM output is in short circuit con-

dition is shown in Figure 20. If either PWM or LDO out-

put is in short condition, it will turn off all outputs. The

operation waveforms are shown in Figures 21 and 22.

Figure 23 shows a soft-start operation when the output

is short. Because of current limit and output feedback

UVLO, the output will be turned off and the system pro-

tected.

Figure 21 - Operation of PWM output and LDO

when PWM output is short to ground.

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IRU3072

Design Example

Input voltage for buck converter: VIN=12V

Output voltage for buck converter: VOUT=1.2V

Nominal output current from switching regulator: IOUT=8A

Output current limit is 10A.

Switching frequency: FS=400KHz

The maximum dynamic output voltage droop at 8A step

load is 150mV.

LDO specification

LDO input voltage: VIN(LDO)=3.3V

LDO output1: VOUT2=2.5V @ 2A

LDO output2: VOUT3=1.8V @ 2A

LDO output3: VOUT4=1.5V @ 2A

Figure 22 - Operation of PWM output and LDO

when LDO VOUT2 is short.

Output inductor selection

The inductor is selected based on the inductor current

ripple, operation frequency and efficiency consideration.

In general, a large inductor results in a small output ripple

and higher efficiency but large size. A small value induc-

tor causes large current ripple and poor efficiency but

small size. Generally, the inductor is selected based on

the output current ripple. The optimum point is usually

found between 20% and 50% ripple of output inductor

current.

Suppose the ripple is selected as 40% of the total out-

put current.

∆IPK_PK/IOUT = 40%

The current ripple is calculated as:

∆IPK_PK = (VIN-VOUT )×VOUT /(L×FS×VIN)

Figure 23 - Soft-start with output is short to ground.

Combining of above two equations, the inductance can

be selected by:

Switching frequency

The switching frequency of IRU3072 can be selected by

the following figure.

L > VOUT ×(VIN-VOUT)/(FS×VIN×40%×IOUT )

In this example,

500

450

400

350

300

250

200

150

100

50

L > 1.2V×(12 - 1.2)/(400KHz×12V×0.4×8A)

L > 0.8µH

Select inductor from Panasonic so that L=1µH. The ripple

current is calculated as:

∆IPK_PK =(12-1.2)×1.2/(1µH×400KHz×12)

∆IPK_PK @2.7A

0

50

100

150

200

Rt (K

)

ΩΩ

Figure 24 - Switching frequency versus resistor Rt.

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IRU3072

Output capacitor selection

ment for each MOSFET is almost the same. If logic-

The voltage rating of the output capacitor is the same as level or 3V driver MOSFET is used, some caution should

the output voltage. Typical available capacitors on the be taken with devices at very low VGS to prevent undes-

market are electrolytic, tantalum and ceramic. If electro- ired turn-on of the complementary MOSFET, which re-

lytic or tantalum capacitors are employed, the criteria is sults a shoot-through circuit.

normally based on the value of Effective Series Resis-

tance (ESR) of total output capacitor. In most cases, If output inductor current ripple is neglected, the RMS

the ESR of the output capacitor is calculated based on current of high side switch is given by:

the following relationship:

D = VOUT/VIN = 0.1

ESR < ∆VRIPPLE(SPEC)/∆IPK_PK

or

ESR < ∆VSTEPLOAD(SPEC)/∆ISTEPLOAD(MAX)

IRMS(HI) =

D×IOUT = 0.1×8A = 2.53A

The RMS current of low side switch is given as:

IRMS(HI) =

1-D×IOUT = 1-0.1×8A = 7.6A

Depending on which one is the requirement.

Where:

For low side MOSFET, if it is driven by 5V, a logic gate

driver MOSFET is preferred. For RDS(ON) of the MOSFET,

it should be as small as possible in order to get highest

efficiency. A logic driver MOSFET such as IRF7460 from

International Rectifier in a SOIC 8-pin package,

RDS(ON)=10mΩ, 20V drain source voltage rating and 12A

IDS is selected for high side and low side MOSFET.

∆VRIPPLE(SPEC) is the maximum allowed voltage ripple.

∆IPK_PK is the current ripple.

∆VSTEPLOAD(SPEC) is the maximum allowed voltage

droop during the transient or step load.

∆ISTEPLOAD(MAX) is the maximum step load current.

In this example:

∆VSTEPLOAD(SPEC) =150mV

∆ISTEPLOAD(MAX) =8A

Power Dissipation for MOSFETs

The power dissipation for MOSFETS typically includes

conduction loss and switching losses. For high side

switch, the conduction loss is estimated as:

The required ESR is calculated as:

ESR < 150mV/8A = 18.75mΩ

PCOND(HI) =D×IOUT×IOUT ×RDS(ON)MAX

Select three Sanyo POSCAP 6TPB330M with 6.3V

330µF and 40mΩ ESR will give about 13mΩ, which will

meet the specification.

The RDS(ON) has to consider the worst case. In the

datasheet of IRF7460:

RDS(ON)MAX = 14mΩ @ Vgs = 4.5V

PCOND(HI) = 0.1×8A×8A×14mΩ @ 0.09W

Input capacitor Selection

Input capacitor is dertermined by the voltage rating and

input RMS current. For this application, the input RMS

current is given as:

The switching loss is more difficult to calculate because

of the parasitic parameters. In general, the switching

loss can be estimated by the following:

IIN(RMS) = IOUT× D×(1-D)

D = VOUT/VIN = 1.2V/12V @ 0.1

PSW = 0.5×VDS×IOUT×(tr+tf)×FS

tr is the rising time and tf is the falling time. From IRU3072

datasheet: tr=50ns and tf=50ns

The input RMS current is estimated as:

IIN(RMS) = 8A× 0.1×(1-0.1) @ 2.4A

PSW(HI) = 0.5×12V×8A×(50ns+50ns)×400KHz

PSW(HI) @ 1.92W

Select two Sanyo POSCAP -16TPB47M with 16V, 47µF

and 1.4A ripple current. A 1µH, 1A small input inductor

is enough for the input filer.

The total disspation for the high side switch is:

PD(HI) = PSW(HI)+PCOND(HI) @ 2W

Power MOSFET Selection

For low side switch, most of the loss are conduction

loss. The low side switch power dissipation is:

In general, the MOSFET selection criteria depends on

the maximum drain-source voltage, RMS current and

ON resistance (RDS(ON)). For both high side and low side

MOSFETs, a drain-source voltage rating higher than

maximum input voltage is necessary. In the demo-board,

20V rating should be satisfied. The gate drive require-

PD(LO) @ PCOND(LO) =(1-D)×IOUT×IOUT×RDS(ON)MAX

PD(LO) @ PCOND(LO) = (1-0.1)×8A×8A×14mΩ

PD(LO) @ PCOND(LO) = 0.81W

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IRU3072

Estimated Temperature Rise for MOSFET

The estimated junction temperature of the MOSFET is

given by:

For low side MOSFET IRF7460, with 4.5V gate volt-

age and maximum RDS(ON) of 14mΩ, then:

RSET = 8.7A×14mΩ/20µA = 6.09KΩ

Select R7=RSET=6.8KΩ

TJ = TA+PD×RθJA

Where:

TJ is the junction temperature.

TA is the ambient temperature.

PD is the power dissipation.

(4) Compensation Design

VOUT

RθJA is the junction-to-ambient thermal resistance

with MOSFET on 1" square PCB board and is from

the data sheet.

IRU3072

Rf1

Error Amp

VFB

For MOSFET IRF7460 with SOIC 8-pin package,

RθJA=508C/W. Assume ambient temperature is TA=358C.

For high side MOSFET, the junction temperature is given

as:

g_m

Rf2

1V

TJ = TA+PD×RθJA = 35+2×50 = 1358C < 1508C

Rc1

Cc1

Comp

For low side MOSFET IRF7460, the maximum junction

temperature can be calculated as:

Cc2

(Optional)

TJ = TA+PD×RθJA = 35+0.81×50 = 768C < 1508C

The maximum junction temperature of both MOSFETs

is below the maximum rating of 1508C.

Figure 25 - Type II compensator.

Controller Parameter Calculation

(1) Frequency Selection

For electrolytic capacitor, the frequency caused by

ESR is typically at a few KHz range. A type II com-

pensator is a good option. The detailed description

is shown in application note AN-1043 from:

From Figure 23, the frequency setting resistor can

be chosen to be Rt=47KΩ, which gives us approxi-

mately 400KHz frequency.

http://www.irf.com/technical-info/appnotes.htm

(2) Soft-Start Capacitor

Select the zero crossover frequency to be 1/10 of

switching frequency that is 40KHz:

Soft-start capacitor for PWM secton is selected from

equation (1). Select start up time tSTART=5ms:

FO = 40KHz

CSS = 20µA×tSTART = 20µA×5ms = 0.1µF

Select C11=CSS=0.1µF

The compensation resistor can be calculated as:

2π×FO×L×VOSC×VOUT

Rc1=

(ESR×VIN×gm×VREF)

(3) Over Current Limit Setting

The over current limit resistor can be calculated based

on Figure 17. The output current limit is set by:

Where VOSC is the oscillator peak to peak voltage

and gm is the transconductance of the error ampli-

fier. From the datasheet we get VOSC=1.25V and

gm=1000µmho. The calculated compensation resis-

tor is:

IO(LIM) = 10A

The current ripple during nomral operation (400KHz)

is given by:

Rc1=2π×40×1×1.25×1.2/(13×12×1000×0.8)

Rc1=2.98K

∆IPK_PK =(12-1.2)×1.2/(1µH×400KHz×12)

∆IPK_PK @ 2.7A

Select R8=Rc1=3.3K

The over current setting ISET is:

The compensator capacitor is given as:

ISET =I O(LIM)-∆IPK_PK/2 = 10A-2.7A/2 @ 8.7A

Cc1 = (L×COUT)/0.75/Rc1

The over current setting resistor:

Cc1 = (1µH×450µF)/0.75/3.3K = 10nF

Select C9=Cc1=15nF

RSET =I SET×RDS(ON)/20µA

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IRU3072

(Optional) an additional capacitor Cc2 can be The required thermal resistance of heat sink should be

adopted, where:

RθSA<(TJ-TA)/PD-RθJC-RθCS

Cc2 @ 1/(π×Rc1×FS) @ 220pF

In this example, the MOSFET is mounted in the copper

area more than 1 square inch. The estimated junction

temperaure is:

(5) Feedback resistor

The output of PWM is determined by:

VOUT =VREF×(RT+RB)/RB

or

RT =(VOUT/VREF-1)×RB

TJ=TA+PD×RθJA

Where RθJA is the thermal resistance from junction to

ambient with PCB mounted.

Where VREF=0.8V

RT is the top feedback resistor and RB is bottom

feedback resistor.For 1.2V output, RT=499Ω,RB=1K.

For IRLR2703s, RθJA=508C/W, Assume:

TA = 358C

TJ = 35+1.5W×508C/W = 1108C < 1508C

LDO Regulator Component Selection

and LDO Power MOSFET Selection

The first step in selecting the power MOSFET for the

linear regulator is to select its maximum RDS(ON) based

on the input to output dropout voltage and maximum

load current.

The thermal managment can meet the requirement.

VccLDO Selection

For LDO, the LDO controller supply voltage has to sat-

isfy the following:

For VOUT2=2.5V, VIN(LDO)=3.3V and IOUT2=2A:

VCC(LDO) > VLDO(OUT)MAX+VGS(TH)MIN+2VBE

RDS(ON)MAX =(VIN(LDO)-VOUT2)/IOUT2

RDS(ON)MAX = (3.3V-2.5V)/2.0A = 0.4Ω

Where:

VLDO(OUT)MAX is the maximum output voltage

VGS(TH)MIN is the minimum LDO MOSFET gate thresh-

old voltage

Note that the MOSFET’s RDS(ON) increases with tem-

perature, the calculated RDS(ON) has to be divided by the

RDS(ON) temperature coefficienct (about 1.5) in order to

get typical RDS(ON).

VBE is the diode drop, approximately 0.6V

For this example, VGS(TH)MIN of MOSFET IRLR2703s, is

1V. Then:

IRLR2703s from Internation Rectifier with D2 package,

30V, VDS logic drive and 65mΩ is good enough to meet

the requirement.

VCC(LDO) > 2.5V+1V+2×0.6V = 4.7V

Select VCCLDO=12V for proper power sequence

LDO Feedback Resistor Selection

The output of LDO is determined by:

To select the heat sink for the LDO MOSFET, the first

step is to calculate the maximum power dissipation of

the device:

VOUT =VREF×(RT+RB)/RB

Where:

VREF=0.8V

PD =(VIN(LDO)-VOUT)×IOUT

PD = (3.3V-2.5V)×2A = 1.4W

RT is the top feedback resistor and RB is bottom

feedback resistor.

The junction temperature of MOSFET can be estimated

by the following formula:

For 2.5V output, if RB=1K then:

RT = (VOUT /VREF-1)×RB = (2.5/0.8-1)×1K = 2.12K

Select Rt=2.15K

TJ = TA+PD×(RθJC+RθCS+RθSA)

TJ should be < TJ(MAX) @ 1508C

Where:

TJ = the estimated junction temperature.

TA = the ambient temperature.

PD = the power disspation.

RθJC = the thermal resistance from junction to case.

RθCS = the thermal resistance from case to heat sink.

RθSA = the thermal resistance from heat sink to am-

bient.

LDO Soft-Start Capacitor

The soft-start capacitor can be estimated from equation

(1). Select start up time as 2ms:

CSS(LDO) = 20µA×tSTART = 20µA×2ms = 0.04µF

Select C12=CSS(LDO)=33nF

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IRU3072

Layout Consideration

directly to the drain of the high-side MOSFET, to reduce

The layout is very important when designing high fre- the ESR replace the single input capacitor with two par-

quency switching converters. Layout will affect noise allel units. The feedback part of the system should be

pickup and can cause a good design to perform with kept away from the inductor and other noise sources,

less than expected results.

and be placed close to the IC. In multilayer PCB use

one layer as power ground plane and have a control cir-

Start to place the power components, make all the con- cuit ground (analog ground), to which all signals are ref-

nection in the top layer with wide, copper filled areas. erenced. The goal is to localize the high current path to

The inductor, output capacitor and the MOSFET should a separate loop that does not interfere with the more

be close to each other as possible. This helps to reduce sensitive analog control function. These two grounds

the EMI radiated by the power traces due to the high must be connected together on the PC board layout at a

switching currents through them. Place input capacitor single point.

APPLICATION EXPERIMENTAL WAVEFORMS

for Application Circuit in Figures 1 and 3

Figure 26 - Transient response with 8A load.

Figure 27 - Transient response (zoomed).

Figure 28 - Transient response (zoomed).

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IRU3072

TYPICAL APPLICATIONS

3.3V

VSEN33 / SDB Vcc

C1

1uF

Q1

IRLR2703

Drv2

Fb2

R1

VOUT2

2.5V

2.15K

C2

R2

1K

VccLDO

Vc

Q2

C4

Drv3

Fb3

R3

VOUT3

1.8V

L1

1.24K

R4

1K

C5

1uF

C6

0.1uF

VIN=5V

1uH

U1

IRU3072

C7

16TPB47M

47uF, 16V

C8

10uF

Q3

C9

Drv4

Fb4

R5

V

1.5V

OUT4

Q4

IRF7460

866

HDrv

R6

1K

L2 1uH

R7

6.8K

OCSet

LDrv

VOUT1

1.2V @ 8A

C10 100pF

Q5

IRF7460

R8

C12

3x 6TPB330M

6.3V, 330uF, 40m

C11

10nF

Comp

6.8K

Ω

R9

Rt

46.4K

R10

1K

SS1

Fb1

C13

0.1uF C14

33nF

R11

1K

SSLDO

Gnd

PGnd

Figure 29 - IRU3072 typical application with one bus input voltage VCC=VBUS=5V and 3.3V for LDO.

3.3V

Vcc

V

SEN33 / SDB

C1

1uF

Q1

IRLR2703

Drv2

Fb2

R1

V

OUT2

2.15K

2.5V

R2

1K

C2

VccLDO

Vc

12V

Q2

C4

Drv3

Fb3

R3

C3

1uF

VOUT3

1.8V

L1

1.24K

R4

1K

VIN=5V

U1

IRU3072

1uH

C7

16TPB47M

47uF, 16V

C8

10uF

Q3

C9

Drv4

Fb4

R5

V

1.5V

OUT4

Q4

IRF7460

866

HDrv

R6

1K

L2

1uH

R7

6.8K

OCSet

LDrv

VOUT1

0.8V

C10 100pF

Q5

IRF7460

R8

C11

C12

3x6TPB330M

6.3V, 330uF, 40m

Comp

10nF

6.8K

Ω

R9

Rt

46.4K

SS1

Fb1

C13

0.1uF C14

33nF

SSLDO

Gnd

PGnd

Figure 30 - IRU3072 Typical application with 5VBUS input and 12V for the driver (charge pump is saved).

Rev. 1.0

3/25/04

www.irf.com

20

IRU3072

TYPICAL APPLICATIONS

3.3V

VSEN33 / SDB Vcc

+5V

C1

1uF

Q1

IRLR2703

Drv2

Fb2

R1

VOUT2

2.5V

2.15K

C2

R2

1K

VccLDO

Vc

C3

1uF

Q2

C4

D1

D2

Drv3

Fb3

R3

VOUT3

1.8V

L1

1.24K

R4

1K

VIN=12V

1uH

U1

IRU3072

C5

1uF

C6

0.1uF

C8

10uF

C7

47uF,16V

Q3

C9

Drv4

Fb4

R5

V

1.5V

OUT4

Q4

IRF7460

866

HDrv

R6

1K

L2

R7

4.7K

OCSet

LDrv

VOUT1

1.2V @ 5A

1uH

C10 82pF

C12

2x 47uF

Ceramic

Q5

IRF7460

R8

C11

3.3nF

Comp

10K

R9

47K

Rt

R11

4.64K

R10

62K

SS1

C13

0.1uF C14

33nF

C15

220pF

SSLDO

Fb1

Gnd PGnd

R12

124K

Figure 31 - IRU3072 typical application with ceramic capacitor output.

R12

3.3V

VSEN33 / SDB Vcc

C1

1uF

200Ω

Q1

IRLR2703

Drv2

Fb2

R1

V

OUT2

2.15K

2.5V

C2

R2

1K

VccLDO

Vc

Q2

C4

Drv3

Fb3

R3

VOUT3

1.8V

L1

1.24K

R4

1K

C5

1uF

C6

0.1uF

VIN=12V

1uH

16TPB47M

47uF, 16V

U1

IRU3072

C7

C8

10uF

Q3

C9

Drv4

Fb4

R5

V

1.5V

OUT4

Q4

IRF7460

HDrv

866

R6

1K

L2 1uH

R7

6.8K

OCSet

LDrv

VOUT1

1.2V

C10 220pF

Q5

IRF7460

R8

C12

3x 6TPB330M

6.3V, 330uF, 40m

C11

15nF

Comp

3.3K

Ω

R9

47K

Rt

R10

1K

SS1

Fb1

C13

0.1uF C14

33nF

R11

1K

SSLDO

Gnd

PGnd

Figure 32 - IRU3072 typical application with one bus input voltage VCC=VBUS=12V and 3.3V for LDO.

Rev. 1.0

3/25/04

www.irf.com

21

IRU3072

TYPICAL APPLICATION

R13

1K

R12

200

3.3V

VSEN33 / SDB Vcc

C1

1uF

Ω

Q1

IRLR2703

Drv2

Fb2

R1

V

OUT2

2.15K

2.5V

R2

1K

C2

VccLDO

Vc

Q2

C4

Drv3

Fb3

R3

VOUT3

1.8V

L1

1.24K

R4

1K

C5

1uF

C6

0.1uF

VIN=12V

1uH

U1

IRU3072

C7

16TPB47M

47uF, 16V

C8

10uF

Q3

C9

Drv4

Fb4

R5

V

1.5V

OUT4

Q4

IRF7460

866

HDrv

R6

1K

L2

1uH

R7

6.8K

OCSet

LDrv

VOUT1

3.3V

C10 220pF

Q5

IRF7460

R8

C12

3x 6TPB330M

6.3V, 330uF, 40m

C11

15nF

Comp

3.3K

Ω

R9

Rt

47K

R10

3.125K

SS1

Fb1

C13

0.1uF C14

33nF

R11

1K

SSLDO

Gnd

PGnd

Figure 33 - IRU3072 typical application with one bus input voltage

VCC=VBUS=12V to generate all LDO output.

Rev. 1.0

3/25/04

www.irf.com

22

IRU3072

(H) MLPQ Package

20-Pin

D

D/2

D2

EXPOSED PAD

PIN NUMBER 1

PIN 1 MARK AREA

(See Note1)

E/2

E2

E

R

L

TOP VIEW

e

B

BOTTOM VIEW

Note 1: Details of pin #1 are optional, but

must be located within the zone indicated.

The identifier may be molded, or marked

features.

A

A3

A1

SIDE VIEW

20-PIN 4x4

SYMBOL

DESIG

A

MIN

NOM

0.90

MAX

1.00

0.05

0.80

0.00

A1

A3

B

0.02

0.20 REF

0.23

0.18

2.00

0.30

2.25

D

4.00 BSC

2.15

D2

E

4.00 BSC

2.15

E2

e

0.50 BSC

0.55

L

0.45

0.09

0.65

---

R

---

NOTE: ALL MEASUREMENTS

ARE IN MILLIMETERS.

Rev. 1.0

3/25/04

www.irf.com

23

IRU3072

PACKAGE SHIPMENT METHOD

PKG

PACKAGE

COUNT

20

PARTS

PER TUBE

TBD

PARTS

PER REEL

TBD

T & R

Orientation

Fig A

DESIG

DESCRIPTION

H

MLPQ 4x4

Feed Direction

Figure A

This product has been designed and qualified for the industrial market.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 02/01

Rev. 1.0

3/25/04

www.irf.com

24


型号：	IRU3072C
厂家：	Infineon
描述：	20-PIN SYNCHRONOUS PWM CONTROLLER/ 3 LDO CONTROLLER 20 -PIN同步PWM控制器/ 3 LDO控制器控制器
文件：	总24页 (文件大小：329K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRU3072C [INFINEON]

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