Q62702-C1659 [INFINEON]
NPN Silicon AF and Switching Transistor (High breakdown voltage Low collector-emitter saturation voltage); NPN硅AF和开关晶体管(高击穿电压低集电极 - 发射极饱和电压)型号: | Q62702-C1659 |
厂家: | Infineon |
描述: | NPN Silicon AF and Switching Transistor (High breakdown voltage Low collector-emitter saturation voltage) |
文件: | 总4页 (文件大小:36K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BF 1012
Silicon N-Channel MOSFET Tetrode
3
• For low noise, high gain controlled
input stages up to 1GHz
4
• Operating voltage 12V
• Integrated stabilized bias network
2
VPS05178
1
ESD: Electrostatic discharge sensitive device, observe handling precaution!
Type
Marking Ordering Code Pin Configuration
Package
BF 1012
MYs
Q62702-F1487 1 = S
2 = D
3 = G2 4 = G1 SOT-143
Maximum Ratings
Parameter
Symbol
Value
Unit
V
Drain-source voltage
Continuos drain current
16
V
DS
25
mA
I
D
Gate 1/gate 2 peak source current
10
3
±I
G1/2SM
Gate 1 (external biasing)
V
+V
G1SE
200
mW
°C
Total power dissipation, T ≤ 76 °C
P
tot
S
Storage temperature
Channel temperature
-55 ...+150
150
T
T
stg
ch
Thermal Resistance
Channel - soldering point
K/W
R
≤370
thchs
Note:
It is not recommended to apply external DC-voltage on Gate 1 in active mode.
Semiconductor Group
1
Sep-09-1998
1998-11-01
Semiconductor Group
1
BF 1012
Electrical Characteristics at T = 25°C, unless otherwise specified.
A
Parameter
Symbol
Values
typ. max.
Unit
min.
DC characteristics
Drain-source breakdown voltage
16
8
10
-
-
-
-
V
V
(BR)DS
I = 300 µA, -V
= 4 V, - V
= 4 V
G2S
D
G1S
Gate 1 source breakdown voltage
±I = 10 mA, V = V = 0
12
16
60
50
±V
±V
(BR)G1SS
(BR)G2SS
G1SS
G1S
G2S
DS
Gate 2 source breakdown voltage
±I = 10 mA, V = 0 V, V = 0 V
-
G2S
G1S
DS
Gate 1 source current
= 6 V, V = 0 V
-
µA
+I
V
G1S
G2S
Gate 2 source leakage current
±V = 8 V, V = 0 V, V = 0 V
-
-
nA
±I
G2SS
G2S
G1S
DS
Drain current
= 12 V, V
-
-
500 µA
I
I
DSS
V
= 0 , V
= 6 V
G2S
DS
G1S
Operating current (selfbiased)
= 12 V, V = 6 V
8
-
10
0.9
-
-
mA
V
DSO
V
DS
G2S
Gate 2-source pinch-off voltage
= 12 V, I = 100 µA
V
G2S(p)
V
DS
D
AC characteristics
Forward transconductance (self biased)
-
-
24
2.1
0.9
22
-
mS
g
fs
V
= 12 V, V
= 6 V, f = 1 kHz
G2S
DS
Gate 1-input capacitance (self biased)
= 12 V, V = 6 V, f = 1 MHz
2.5 pF
C
C
G
g1ss
dss
ps
V
DS
G2S
Output capacitance (self biased)
= 12 V, V = 6 , f = 1 MHz
-
-
V
DS
G2S
Power gain (self biased)
= 12 V, V = 6 , f = 800 MHz
-
-
-
-
dB
V
DS
G2S
Noise figure (self biased)
= 12 V, V = 6 V, f = 800 MHz
-
1.4
50
F
800
V
DS
G2S
Gain control range (self biased)
= 12 V, V = 6 V, f = 800 MHz
40
∆G
ps
V
DS
G2S
Semiconductor Group
Semiconductor Group
2
Sep-09-1998
1998-11-01
2
BF 1012
Total power dissipation P = f (T )
Drain current I = f (V
)
G2S
tot
S
D
300
11
mA
mW
9
8
200
150
100
50
7
P
I
6
5
4
3
2
1
0
0
°C
V
0
20
40
60
80
100 120
150
0.0
1.0
2.0
3.0
4.0
6.0
G2S
T
V
S
Insertion power gain
Forward transfer admittance
2
| S | = f (V
)
| Y | = f (V
)
G2S
21
G2S
21
24
10
dB
mS
0
-5
20
18
16
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
Y
14
12
10
8
6
4
2
0
V
V
0.0
1.0
2.0
3.0
4.0
6.0
G2S
0.0
1.0
2.0
3.0
4.0
6.0
G2S
V
V
Semiconductor Group
Semiconductor Group
3
Sep-09-1998
1998-11-01
3
BF 1012
Gate 1 input capacitance C
= f (V
)
Output capacitance C
= f (V )
dss G2
g1ss
g2s
f = 200MHz
f = 200MHz
3.2
pF
3.2
pF
2.4
2.4
2.0
2.0
C
C
1.6
1.2
0.8
0.4
0.0
1.6
1.2
0.8
0.4
0.0
V
V
0.0
1.0
2.0
3.0
4.0
6.0
G2S
0.0
1.0
2.0
3.0
4.0
6.0
G2S
V
V
Semiconductor Group
Semiconductor Group
4
Sep-09-1998
1998-11-01
4
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