Q67007-A9399 [INFINEON]
TrilithIC; TrilithIC
| 型号： | Q67007-A9399 |
| 厂家： | 
Infineon |
| 描述： | TrilithIC |
| 文件： | 总16页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TrilithIC
BTS 7710 G
Data Sheet
1
Overview
1.1
Features
• Quad D-MOS switch driver
• Free configurable as bridge or quad-switch
• Optimized for DC motor management applications
• Low RDS ON: 70 mτ high-side switch, 40 mτ low-side
switch (typical values @ 25 C)
P-DSO-28-14
• Maximum peak current: typ. 15 A @ 25 C=
• Very low quiescent current: typ. 5 ←A @ 25 C=
• Small outline, enhanced power P-DSO-package
• Load and GND-short-circuit-protection
• Operates up to 40 V
• Status flag diagnosis
• Overtemperature shut down with hysteresis
• Internal clamp diodes
• Isolated sources for external current sensing
• Under-voltage detection with hysteresis
• PWM frequencies up to 50 kHz
Type
Ordering Code
Package
BTS 7710 G
Q67007-A9399
P-DSO-28-14
1.2
Description
The BTS 7710 G is part of the TrilithIC family containing three dies in one package:
One double high-side switch and two low-side switches. The drains of these three
vertical DMOS chips are mounted on separated leadframes. The sources are connected
to individual pins, so the BTS 7710 G can be used in H-bridge- as well as in any other
configuration. The double high-side is manufactured in SMART SIPMOS® technology
which combines low RDS ON vertical DMOS power stages with CMOS control circuitry.
The high-side switch is fully protected and contains the control and diagnosis circuitry.
To achieve low RDS ON and fast switching performance, the low-side switches are
manufactured in S-FET logic level technology. The equivalent standard product is the
BUZ 103 SL.
In contrast to the BTS 7710 GP, which consists of the same chips in an P-TO263-15
package, the P-DSO-28-14 package offers a smaller outline and a lower price for
applications, which do not need the thermal properties of the P-TO263-15.
Data Sheet
1
2001-02-01
BTS 7710 G
1.3
Pin Configuration
(top view)
DL1 1
28 DL1
27 SL1
26 SL1
25 DL1
24 DHVS
23 SH1
22 SH1
21 SH2
20 SH2
19 DHVS
18 DL2
17 SL2
16 SL2
15 DL2
IL1 2
DL1 3
N.C. 4
DHVS 5
GND 6
IH1 7
LS-Leadframe
HS-Leadframe
LS-Leadframe
ST 8
IH2 9
DHVS 10
N.C. 11
DL2 12
IL2 13
DL2 14
Figure 1
Data Sheet
2
2001-02-01
BTS 7710 G
1.4
Pin No.
Pin Definitions and Functions
Symbol Function
1, 3, 25, 28
2
4
DL1
IL1
N.C.
DHVS
Drain of low-side switch1, leadframe 1 1)
Analog input of low-side switch1
not connected
5, 10, 19, 24
Drain of high-side switches and power supply voltage,
leadframe 2 1)
6
7
GND
IH1
Ground
Digital input of high-side switch1
Status of high-side switches; open Drain output
Digital input of high-side switch2
not connected
8
9
11
ST
IH2
N.C.
12, 14, 15, 18 DL2
Drain of low-side switch2, leadframe 3 1)
Analog input of low-side switch2
Source of low-side switch2
Source of high-side switch2
Source of high-side switch1
Source of low-side switch1
13
IL2
16,17
20,21
22,23
26,27
SL2
SH2
SH1
SL1
1)
To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe.
Pins written in bold type need power wiring.
Data Sheet
3
2001-02-01
BTS 7710 G
1.5
Functional Block Diagram
DHVS
5,10,19,24
8
ST
Diagnosis
Biasing and Protection
7
IH1
Driver
IN OUT
0 0 L L
0 1 L H
1 0 H L
1 1 H H
RO1
RO2
20,21
SH2
DL2
9
6
IH2
12,14,15,18
GND
22, 23
SH1
DL1
1,3,25,28
2
IL1
IL2
13
26, 27
16, 17
SL1
SL2
Figure 2
Block Diagram
Data Sheet
4
2001-02-01
BTS 7710 G
1.6
Circuit Description
Input Circuit
The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with
hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into
the necessary form for driving the power output stages. The inputs are protected by ESD
clamp-diodes.
The inputs IL1 and IL2 are connected to the gates of the standard N-channel vertical
power-MOS-FETs.
Output Stages
The output stages consist of an low RDS ON Power-MOS H-bridge. In H-bridge
configuration, the D-MOS body diodes can be used for freewheeling when commutating
inductive loads. If the high-side switches are used as single switches, positive and
negative voltage spikes which occur when driving inductive loads are limited by
integrated power clamp diodes.
Short Circuit Protection
The outputs are protected against
– output short circuit to ground
– overload (load short circuit).
An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-Voltage-
Drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the
output current depending on the junction temperature and the drop voltage.
In the case of overloaded high-side switches the status output is set to low.
Overtemperature Protection
The high-side switches incorporate an overtemperature protection circuit with hysteresis
which switches off the output transistors and sets the status output to low.
Undervoltage-Lockout (UVLO)
When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis.
The High-Side output transistors are switched off if the supply voltage VS drops below
the switch off value VUVOFF.
Data Sheet
5
2001-02-01
BTS 7710 G
Status Flag
The status flag output is an open drain output with Zener-diode which requires a pull-up
resistor, c.f. the application circuit on page 14. Various errors as listed in the table
“Diagnosis” are detected by switching the open drain output ST to low. A open load
detection is not available. Freewheeling condition does not cause an error.
2
Truthtable and Diagnosis (valid only for the High-Side-Switches)
Flag
IH1
IH2
SH1 SH2 ST Remarks
Outputs
Inputs
0
0
1
1
0
1
0
1
L
L
1
1
1
1
stand-by mode
switch2 active
switch1 active
both switches
active
Normal operation;
identical with functional truth table
L
H
L
H
H
H
Overtemperature high-side switch1
Overtemperature high-side switch2
Overtemperature both high-side switches
0
1
X
X
0
X
1
X
X
0
1
0
1
X
L
L
X
X
L
L
L
X
X
L
L
L
L
L
1
0
1
0
1
0
0
detected
detected
detected
detected
Undervoltage
X
X
L
L
1
not detected
Inputs:
Outputs:
Status:
0 = Logic LOW
1 = Logic HIGH
X = don’t care
Z = Output in tristate condition
L = Output in sink condition
H = Output in source condition
X = Voltage level undefined
1 = No error
0 = Error
Data Sheet
6
2001-02-01
BTS 7710 G
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
– 40 C < Tj < 150 C
Parameter
Symbol Limit Values Unit Remarks
min. max.
High-Side-Switches (Pins DHVS, IH1,2 and SH1,2)
Supply voltage
VS
– 0.3 42
28
V
V
–
–
Supply voltage for full short VS(SCP)
circuit protection
HS-drain current*
HS-input current
HS-input voltage
Note: * single pulse
IS
IIH
VIH
– 8
– 5
– 10
**
5
16
A
TA = 25°C; t < 100 ms
mA Pin IH1 and IH2
V
Pin IH1 and IH2
** internally limited
Status Output ST
Status pull up voltage
Status Output current
VST
IST
– 0.3 5.4
– 5
V
–
5
mA Pin ST
Low-Side-Switches (Pins DL1,2, IL1,2 and SL1,2)
Drain- source break down
voltage
VDSL
55
–
V
VIL = 0 V; ID 1 mA
LS-drain current*
IDL
–8
–
–
8
A
A
A
V
t < 100 ms
t < 10 ms
t < 1 ms
TA = 25°C
11
24
20
LS-input voltage
VIL
– 20
Pin IL1 and IL2
Note: * single pulse
Temperatures
Junction temperature
Storage temperature
Tj
Tstg
– 40
– 55
150
150
C
C
–
–
Data Sheet
7
2001-02-01
BTS 7710 G
3.1
Absolute Maximum Ratings (cont’d)
– 40 C < Tj < 150 C
Parameter
Symbol Limit Values Unit Remarks
min. max.
Thermal Resistances (one HS-LS-Path active)
LS-junction case
HS-junction case
RthjC L
RthjC H
Rthja
–
–
–
20
20
60
K/W measured to pin 3 or 12
K/W measured to pin 19
K/W device soldered to
reference PCB with
6 cm2 cooling area
Junction ambient
Rthja = Tj(HS)/(P(HS)+P(LS)
)
ESD Protection (Human Body Model acc. MIL STD 883D, method 3015.7 and EOS/
ESD assn. standard S5.1 - 1993)
Input LS-Switch
Input HS-Switch
Status HS-Switch
Output LS and HS-Switch
VESD
VESD
VESD
VESD
–
–
–
–
0.5
1
2
kV
kV
kV
kV
8
all other pins connected
to Ground
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
3.2
Operating Range
– 40 C < Tj < 150 C
Parameter
Symbol Limit Values Unit
min. max.
Remarks
Supply voltage
VS
VUVOFF 42
V
After VS rising
above VUVON
Input voltages HS
Input voltages LS
Output current
VIH
VIL
IST
Tj
– 0.3 15
– 0.3 20
V
V
mA
C
–
–
–
–
0
2
Junction temperature
– 40
150
Note: In the operating range the functions given in the circuit description are fulfilled.
Data Sheet
8
2001-02-01
BTS 7710 G
3.3
Electrical Characteristics
I
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Current Consumption HS-switch
Quiescent current
IS
–
5
8
←A
←A
IH1 = IH2 = 0 V
Tj = 25 C
–
–
–
1.5
12
2.6
IH1 = IH2 = 0 V
Supply current
IS
mA IH1 or IH2 = 5 V
VS = 12 V
–
–
–
3
–
–
5.2
6
mA IH1 and IH2 = 5 V
VS = 12 V
Leakage current of
highside switch
ISH LK
ILKCL
←A
VIH = VSH = 0 V
Leakage current through
=
10
mA IFH = 3 A
logic GND in free wheeling IFH + ISH
condition
Current Consumption LS-switch
Input current
IIL
–
–
10
–
100
10
nA
VIL = 20 V;
V
DSL = 0 V
Tj = 25 C
VIL = 0 V
Leakage current of lowside IDL LK
←A
switch
VDSL = 40 V
Under Voltage Lockout (UVLO) HS-switch
Switch-ON voltage
Switch-OFF voltage
Switch ON/OFF hysteresis VUVHY
VUVON
VUVOFF
–
1.8
–
–
–
1
4.5
3.2
–
V
V
V
VS increasing
VS decreasing
VUVON – VUVOFF
Data Sheet
9
2001-02-01
BTS 7710 G
3.3
Electrical Characteristics (cont’d)
I
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Output stages
Inverse diode of high-side VFH
–
–
–
0.8
0.8
70
1.2
1.2
90
V
V
IFH = 3A
IFL = 3 A
switch; Forward-voltage
Inverse diode of lowside
VFL
switch; Forward-voltage
Static drain-source
on-resistance of highside
switch
RDS ON H
mτ ISH = 1 A
Tj = 25 C
Static drain-source
on-resistance of lowside
switch
RDS ON L
–
–
40
–
50
mτ ISL = 1 A;
VIL = 5 V
Tj = 25 C
Static path on-resistance
RDS ON
260
mτ
RDS ON H + RDS ON L
ISH = 1 A;
Short Circuit of highside switch to GND
Initial peak SC current
Initial peak SC current
Initial peak SC current
ISCP H
ISCP H
ISCP H
15
13
9
18
15
11
20
17
13
A
A
A
Tj = – 40 °C
Tj = + 25 °C
Tj = + 150 °C
Short Circuit of highside switch to VS
Output pull-down-resistor
RO
8
15
35
kτ
V
DSL = 3 V
Thermal Shutdown
Thermal shutdown junction Tj SD
155
150
–
180
170
10
190
180
–
C
C
C
–
–
temperature
Thermal switch-on junction Tj SO
temperature
Temperature hysteresis
αT
αT = TjSD – TjSO
Data Sheet
10
2001-02-01
BTS 7710 G
3.3
Electrical Characteristics (cont’d)
I
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Status Flag Output ST of highside switch
Low output voltage
Leakage current
Zener-limit-voltage
VST L
IST LK
VST Z
–
–
5.4
0.2
–
0.6
10
–
V
←A
V
IST = 1.6 mA
VST = 5 V
IST = 1.6 mA
Switching times of highside switch
Turn-ON-time;
tON
–
–
–
–
75
60
–
160
160
1.5
2.0
←s
←s
RLoad = 12 τ
VS = 12 V
to 90% VSH
Turn-OFF-time;
tOFF
RLoad = 12 τ
to 10% VSH
VS = 12 V
Slew rate on 10 to 30% VSH dV/dtON
V/←s RLoad = 12 τ
VS = 12 V
V/←s RLoad = 12 τ
Slew rate off 70 to 40% VSH -dV/
–
dtOFF
VS = 12 V
Note: switching times are guaranteed by design
Switching times of low-side switch
Turn-ON delay time;
td_ON_L
tON_L
td_OFF_L
tOFF_L
–
–
–
–
9
14
40
55
33
ns
ns
ns
ns
resistive load
VIL = 5V; RG = 7τ
ISL = 3 A; VS = 30 V
Switch-ON time;
25
36
22
resistive load
VIL= 5V; RG = 7τ
ISL = 3 A; VS = 30 V
Switch-OFF delay time;
resistive load
VIL= 5V; RG = 7τ
ISL = 3 A; VS = 30 V
Switch-OFF time;
resistive load
VIL= 5V; RG = 7τ
ISL = 3 A; VS = 30 V
Data Sheet
11
2001-02-01
BTS 7710 G
3.3
Electrical Characteristics (cont’d)
I
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Gate charge of lowside switch
Input to source charge;
Input to drain charge;
Input charge total;
QIS
QID
QI
–
–
–
4
10
28
6
16
43
nC
nC
nC
ISL = 3 A; VS = 14 V
ISL = 3 A; VS = 14 V
ISL = 3 A; VS = 14 V
VIL = 0 to 10 V
Input plateau voltage;
V(plateau)
–
2.75 -
V
ISL = 3 A; VS = 14 V
Note: switching times and input charges are guaranteed by design
Control Inputs of highside switches IH 1, 2
H-input voltage
L-input voltage
Input voltage hysterese
H-input current
L-input current
VIH High
VIH Low
VIH HY
IIH High
IIH Low
RI
–
1
–
15
5
–
–
0.3
30
–
2.5
–
–
60
20
5.5
–
V
V
V
←A
←A
kτ
V
–
–
–
VGH = 5 V
VGH = 0.4 V
–
Input series resistance
Zener limit voltage
2.7
5.4
4
–
VIH Z
IGH = 1.6 mA
Control Inputs IL1, 2
Gate-threshold-voltage
VIL th
0.9
1.7
2.2
V
IDL = 1 mA
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 C and
the given supply voltage.
Data Sheet
12
2001-02-01
BTS 7710 G
VS=12V
IS
CS
CL
470nF
100µF
IFH1,2
DHVS
5,10,19,24
IST LK
IST
VDSH2
VDSH1
8
7
ST
-VFH2
-VFH1
Diagnosis
Biasing and Protection
VST
VSTL
VSTZ
IIH1
IH1
Gate
Driver
ISH2
IDL2
IDL LK 2
ISH1
IDL1
IDL LK 1
RO1
RO2
SH2
DL2
20,21
IIH1
IH2
9
6
Gate
VIH1
Driver
12,14,15,18
GND
VUVON
VIH2
VUVOFF
SH1
DL1
IGND
ILKCL
22,23
1,3,25,28
IIL1
2
IL1
IL2
IIL2
13
VIL1
VIL th 1
26,27
VIL2
VIL th 2
16,17
VDSL1
-VFL1
VDSL2
SL2
SL1
-VFL2
ISCP L 1
ISCP L 2
ISL1
ISL2
Figure 3
Test Circuit
HS-Source-Current
Named during Short
Circuit
Named during Leakage-
Cond.
ISH1,2
ISCP H
IDL LK
Data Sheet
13
2001-02-01
BTS 7710 G
Watchdog
Reset
Q
I
TLE
VS=12V
4278G
D
RQ
100 k
CQ
22µF
CS
D01
Z39
CD
τ
10µF
47nF
WD R
VCC
DHVS
5,10,19,24
8
7
RS
10 k
ST
τ
Diagnosis
Biasing and Protection
IH1
Gate
Driver
RO1
RO2
SH2
DL2
20,21
IH2
9
6
Gate
Driver
12,14,15,18
GND
µP
M
SH1
22,23
DL1
1,3,25,28
2
IL1
IL2
13
26,27
16,17
SL2
GND
SL1
Figure 4
Application Circuit
Data Sheet
14
2001-02-01
BTS 7710 G
4
Package Outlines
P-DSO-28-14
(Plastic Transistor Single Outline Package)
0.35 x 45˚
1)
7.6 -0.2
+0.09
0.23
8˚ max
0.4 +0.8
1.27
0.3
0.35 +0.152)
10.3
0.1
0.2 28x
28
15
14
1
1)
18.1-0.4
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max rer side
2) Does not include dambar protrusion of 0.05 max per side
GPS05123
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Dimensions in mm
2001-02-01
Data Sheet
15
BTS 7710 G
Published by
Infineon Technologies AG i Gr.,
Bereichs Kommunikation
St.-Martin-Strasse 53,
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body, or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
Data Sheet
16
2001-02-01
相关型号：
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INFINEON
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