Q67100-Q1147 [INFINEON]
2M x 8-Bit Dynamic RAM; 2M ×8位动态随机存储器
| 型号： | Q67100-Q1147 |
| 厂家： | 
Infineon |
| 描述： | 2M x 8-Bit Dynamic RAM |
| 文件： | 总26页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2M x 8-Bit Dynamic RAM
HYB3117800BSJ-50/-60/-70
Advanced Information
• 2 097 152 words by 8-bit organization
• 0 to 70 °C operating temperature
• Performance:
-50
50
13
25
90
35
-60
60
15
30
-70
t
t
t
t
t
RAS access time
70
20
35
ns
ns
ns
RAC
CAC
AA
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
110 130 ns
40 45 ns
RC
PC
• Single + 3.3 V (± 0.3V) supply
• Low power dissipation
max. 432 active mW (-50 version)
max. 396 active mW (-60 version)
max. 360 active mW (-70 version)
7.2 mW standby (LV-TTL)
3.6 mW standby (CMOS)
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh and test mode
• Fast page mode capability
• All inputs, outputs and clocks fully LVTTL-compatible
• 2048 refresh cycles / 32 ms
• Plastic Package:
P-SOJ-28-3 400 mil
Semiconductor Group
1
1.96
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
The HYB 3117800BSJ is a 16 MBit dynamic RAM organized as 2097152 words by 8-bits. The HYB
3117800BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 3117800BSJ to be packaged in a standard SOJ 28
400 mil plastic package. These packages provide high system bit densities and are compatible with
commonly used automatic testing and insertion equipment. System-oriented features include single
+ 3.3 V (± 0.3V) power supply, direct interfacing with high-performance logic device families.
Ordering Information
Type
Ordering Code Package
Descriptions
3.3V DRAM (access time 50 ns)
3.3V DRAM (access time 60 ns)
3.3V DRAM (access time 70 ns)
HYB 3117800BSJ-50 Q67100-Q1147 P-SOJ-28-3 400 mil
HYB 3117800BSJ-60 Q67100-Q1148 P-SOJ-28-3 400 mil
HYB 3117800BSJ-70
P-SOJ-28-3 400 mil
Pin Names
A0 to A10 Row Address Inputs
A0 to A9
RAS
OE
Column Address Inputs
Row Address Strobe
Output Enable
I/O1-I/O8
CAS
WE
Data Input/Output
Column Address Strobe
Read/Write Input
VCC
Power Supply (+ 3.3 V)
Ground (0 V)
VSS
N.C.
not connected
Semiconductor Group
2
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
P-SOJ-28-3 (400mil)
O
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
VCC
I/O1
28
1
2
3
4
27
26
25
24
23
22
I/O2
I/O3
I/O4
5
6
WE
RAS
N.C.
A10
A0
7
A9
A8
A7
8
21
20
9
19
18
17
16
15
10
11
12
13
14
A1
A6
A5
A2
A3
VCC
A4
VSS
Pin Configuration
Semiconductor Group
3
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
I/O8
I/O1 I/O2
WE
&
.
CAS
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
8
8
Column
Address
Buffer(10)
10
Column
Decoder
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
8
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (11)
1024
x8
11
A10
Row
Address
Buffers(11)
Row
Decoder
Memory Array
2048x1024x8
11
11
2048
No. 1 Clock
Generator
RAS
Block Diagram
Semiconductor Group
4
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70°C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage ...............................................................................-0.5 to min (Vcc+0.5, 4.6) V
Power supply voltage...................................................................................................-1.0V to 4.6 V
Power dissipation..................................................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3V, tT = 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Vcc+0.5
0.8
1)
1)
1)
1)
Input high voltage
VIH
VIL
2.0
V
Input low voltage
– 0.5
2.4
V
LVTTL Output high voltage (IOUT = –2 mA)
LVTTL Output low voltage (IOUT = 2 mA)
CMOS Output high voltage (IOUT = –100 µA)
CMOS Output low voltage (IOUT = 100 µA)
VOH
VOL
VOH
VOL
II(L)
–
V
–
0.4
V
Vcc-0.2
–
–
V
)
0.2
V
1)
Input leakage current,any input
– 10
10
µA
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)
1)
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)
IO(L)
ICC1
– 10
10
µA
Average VCC supply current:
-50 ns version
2) 3) 4)
2) 3) 4)
2) 3) 4)
–
–
–
120
110
100
mA
mA
mA
-60 ns version
-70 ns version
(RAS, CAS, address cycling, tRC = tRC min.)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only ICC3
–
2
mA
–
2) 4)
2) 4)
2) 4)
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
–
–
–
120
110
100
mA
mA
mA
(RAS cycling: CAS = VIH, tRC = tRC min.)
Semiconductor Group
5
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3V, tT = 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Average VCC supply current,
during fast page mode:
ICC4
2) 3) 4)
2) 3) 4)
2) 3) 4)
-50 ns version
-60 ns version
-70 ns version
–
–
–
40
35
30
mA
mA
mA
(RAS = VIL, CAS, address cycling,tPC = tPC min.)
1)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
ICC6
–
1
mA
Average VCC supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
2) 4)
2) 4)
2) 4)
–
–
–
120
110
100
mA
mA
mA
-70 ns version
(RAS, CAS cycling, tRC = tRC min.)
ICC7
_
1
mA
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1-I/O8)
CI1
CI2
CIO
–
–
–
5
7
7
pF
pF
pF
Semiconductor Group
6
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
5)6)
16F
AC Characteristics
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
common parameters
Random read or write cycle time tRC
90
30
50
13
0
–
110
40
60
15
0
–
130
50
70
20
0
–
ns
ns
ns
ns
ns
ns
ns
ns
RAS precharge time
RAS pulse width
tRP
–
–
–
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
10k
10k
–
10k
10k
–
10k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
8
–
10
0
–
10
0
–
0
–
–
–
10
18
13
–
15
20
15
–
15
20
15
–
37
25
45
30
50
35
RAS to column address delay
time
ns
RAS hold time
tRSH
tCSH
tCRP
tT
13
50
5
15
60
5
–
20
70
5
–
ns
ns
ns
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
–
3
50
32
3
50
32
3
50
32
ns
7
tREF
–
–
–
ms
Read Cycle
Access time from RAS
Access time from CAS
tRAC
tCAC
–
50
13
25
13
–
–
60
15
30
15
–
–
70
20
35
20
–
ns 8, 9
ns 8, 9
ns 8,10
ns
–
–
–
Access time from column address tAA
–
–
–
OE access time
tOEA
–
–
–
Column address to RAS lead time tRAL
25
0
30
0
35
0
ns
Read command setup time
Read command hold time
tRCS
tRCH
tRRH
–
–
–
ns
0
–
0
–
0
–
ns 11
ns 11
Read command hold time
referenced to RAS
0
–
0
–
0
–
CAS to output in low-Z
tCLZ
tOFF
0
0
–
0
0
–
0
0
–
ns
8
Output buffer turn-off delay
13
15
20
ns 12
Semiconductor Group
7
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
5)6)
16F
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
Output buffer turn-off delay from tOEZ
0
13
0
15
0
20
ns 12
OE
Data to OE low delay
CAS high to data delay
OE high to data delay
tDZO
tCDD
tODD
0
–
–
–
0
–
–
–
0
–
–
–
ns 13
ns 14
ns 14
13
13
15
15
20
20
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
tWCH
tWP
8
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
–
ns
8
ns
tWCS
0
ns 15
ns
Write command to RAS lead time tRWL
Write command to CAS lead time tCWL
13
13
0
15
15
0
20
20
0
ns
Data setup time
tDS
ns 16
ns 16
ns 13
Data hold time
tDH
tDZC
10
0
10
0
15
0
Data to CAS low delay
Read-Modify-Write Cycle
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
126
68
–
–
–
–
–
150
80
–
–
–
–
–
180
95
–
–
–
–
–
ns
ns 15
ns 15
ns 15
ns
31
35
45
Column address to WE delay time tAWD
43
50
60
OE command hold time
tOEH
13
15
20
Fast Page Mode Cycle
Fast page mode cycle time
CAS precharge time
tPC
tCP
35
10
–
–
40
10
–
–
45
10
–
–
ns
ns
–
–
–
Access time from CAS precharge tCPA
30
35
40
ns
7
RAS pulse width
tRAS
50
30
200k 60
35
200k 70
40
200k ns
ns
CAS precharge to RAS Delay
tRHPC
–
–
–
Semiconductor Group
8
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
5)6)
16F
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle tPRWC
time
71
–
–
80
55
–
–
95
65
–
–
ns
ns
CAS precharge to WE
tCPWD
48
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
10
10
10
10
10
10
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time
tCPT
35
–
40
–
40
–
ns
Test Mode
CAS hold time
tCHRT
tWTS
tWTH
30
10
10
–
–
–
30
10
10
–
–
–
30
10
10
–
–
–
ns
ns
ns
Write command setup time
Write command hold time
Self Refresh Cycle
RAS pulse width
RAS precharge time
CAS hold time
tRASS
tRPS
tCHS
100k –
100k –
100k –
ns 17
ns 17
ns 17
95
–
–
110
-50
–
–
130
-50
–
–
-50
Semiconductor Group
9
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA).
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13)Either tDZC or tDZO must be satisfied.
14)Either tCDD or tODD must be satisfied.
15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of
the I/O pins (at access time) is indeterminate.
16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
Semiconductor Group
10
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRSH
tCAS
tRCD
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Column
Row
Row
V
IL
tRCH
tRAH
tRCS
tRRH
V
IH
V
IL
tAA
tOEA
V
IH
OE
V
IL
tCDD
tDZC
tODD
tDZO
V
IH
I/O
(Inputs)
V
tCAC
tCLZ
IL
tOFF
tOEZ
V
OH
I/O
(Outputs)
Hi Z
Valid Data Out
Hi Z
V
OL
tRAC
WL1
“H” or “L”
Read Cycle
Semiconductor Group
11
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
V
IL
tCWL
tRAH
tWCS
V
tWP
IH
V
IL
tWCH
tRWL
V
IH
OE
V
IL
tDH
tDS
V
IH
I/O
(Inputs)
Valid Data In
V
IL
V
OH
I/O
(Outputs)
Hi Z
V
OL
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
12
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
CAS
Address
WE
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
V
IL
tCWL
tRWL
tWP
tRAH
V
IH
V
IL
tOEH
V
IH
OE
V
tODD
tDS
tOEZ
IL
tDH
tDZO
tDZC
V
IH
I/O
(Inputs)
Valid Data
V
IL
tCLZ
tOEA
V
OH
Hi-Z
I/O
(Outputs)
Hi-Z
V
OL
WL3
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
13
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
V
IL
tRSH
tCAS
tRCD
tCRP
V
IH
V
CAS
IL
tRAH
tCAH
tASR
tASC
tASR
V
IH
Address
Row
Column
Row
V
IL
tCWL
tRWL
tWP
tAWD
tRAD
tCWD
tRWD
V
IH
WE
OE
V
IL
tAA
tRCS
tOEH
tOEA
V
IH
V
IL
tDS
tDH
tDZO
tDZC
V
IH
Valid
Data in
I/O
(Inputs)
V
IL
tCLZ
tCAC
tODD
tOEZ
V
OH
I/O
(Outputs)
Data
Out
V
OL
tRAC
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRP
tRASP
V
IH
RAS
V
IL
tRHCP
tPC
tCAS
tCP
tCAS
tRCD
tRSH
tCRP
tCAS
V
IH
CAS
V
IL
tCSH
tCAH
tRAH
tCAH
tCAH
tASR
tASC
tASR
tASC
tASC
V
IH
Column
Column
Row
Row
Column
Address
V
IL
tRAD
tRCS
tRCH
tRCH
tRCS
tRCS
V
IH
WE
OE
V
IL
tRRH
tCPA
tAA
tCPA
tAA
tOEA
tAA
tOEA
tOEA
V
IH
V
IL
tDZC
tDZC
tDZO
tDZC
tCDD
tODD
tDZO
tDZO
tODD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tCLZ
tCAC
tOFF
tCAC
tOFF
tOFF
tOEZ
tRAC
tOEZ
tOEZ
tCLZ
tCLZ
V
OH
I/O
(Outputs)
Valid
Data Out
Valid
Data Out
Valid
Data Out
V
OL
“H” or “L”
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
15
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRP
tRAS
V
IH
RAS
V
IL
tRSH
tPC
tCAS
tRCD
tCP
tCAS
tCAS
tCRP
V
IH
CAS
V
IL
tRAL
tRAH
tCAH
tCAH
tASR
tCAH
tASR
tASC
tASC
tASC
V
IH
Address
Column
Column
Row
Column
Column
V
IL
tCWL
tCWL
tWCH
tWP
tRAD
tWCS
tCWL
tWCH
tWP
tRWL
tWCS
tWCS
tWCH
tWP
V
IH
WE
OE
V
IL
V
IH
V
IL
tDH
tDH
tDH
tDS
tDS
tDS
V
IH
I/O
(Inputs)
Valid
Data In
Valid
Data In
Valid
Data In
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
16
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
R
SA
RP
t
t
P
RC
t
L
L
WR
WC
t
t
PW
HD
EOH
t
t
t
SD
D
t
Z
ARL
t
DO
S
OE
t
t
t
ACS
t
D
D
W
D
A
WC
t
WA
C
EO
A
t
Z
PC
t
t
AC
PC
LC
ACH
t
t
t
t
A
t
C
C
SA
ZD
L
t
t
WC
t
EOH
HD
PW
t
t
t
C
W
SD
S
t
D
S
A
Z
RP
t
t
OD
AC
t
t
OE
D
t
D
D
WC
t
WA
t
Z
PCW
t
OEA
t
ACH
LC
t
t
A
A
t
PC
t
C
L
DZC
SA
t
t
PC
t
WC
t
H
PW
t
EO
HD
t
t
Z
SD
t
D
OE
t
DO
D
t
ACS
WC
t
t
D
D
C
EOA
H
AW
WR
Z
t
t
H
t
AC
C
t
LC
t
A
t
SC
t
t
C
O
SA
t
ZD
t
S
D
ZDC
ARC
t
CR
t
t
CR
t
D
AR
H
t
AR
t
SAR
t
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
17
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCRP
tRPC
V
IH
CAS
V
IL
tRAH
tASR
tASR
V
IH
Address
Row
Row
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
WL9
RAS-Only Refresh Cycle
Semiconductor Group
18
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRP
tRP
tRAS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCSR
tCRP
tRPC
tCHR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
tOEZ
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
19
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
V
IH
RAS
V
IL
tRSH
tRCD
tCRP
tCHR
V
IH
CAS
V
tRAD
IL
tWRP
tASC
tASR
tRAH
tWRH
tCAH
tASR
V
IH
Column
Address
Row
Row
V
IL
tRRH
tRCS
V
IH
WE
OE
V
IL
tAA
tOEA
V
IH
V
IL
tDZC
tDZO
tCDD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs)
Valid Data Out
HI-Z
V
OL
WL11
“H” or “L”
Hidden Refresh Cycle (Read) Cycle
Semiconductor Group
20
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRC
tRP
tRP
tRAS
V
tRAS
IH
RAS
V
IL
tRCD
tRSH
tCHR
tCRP
V
IH
CAS
tRAD
V
IL
tRAH
tASR
tASC
tCAH
tASR
V
IH
Address
Row
Column
Row
V
IL
tWCS
tWRP tWRH
tWCH
tWP
V
IH
WE
V
IL
tDS
tDH
V
IH
I/O
(Input)
Valid Data
V
IL
V
OH
I/O
(Output)
HI-Z
V
OL
“H” or “L”
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
21
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRP
tRASS
tRPS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCRP
tCHS
tCSR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
WL13
“H” or “L”
CAS before RAS Self Refresh Cycle
Semiconductor Group
22
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
t
RP
tRAS
Read Cycle:
RAS
V
IH
IL
V
tRSH
tCAS
tCP
tCHR
tCSR
CAS
V
IH
V
tRAL
IL
tASR
tASC tCAH
Column
tAA
V
IH
IL
Address
WE
Row
V
tWRP
tRRH
tRCH
V
IH
IL
tCAC
V
tWRH
tOEA
tRCS
V
IH
IL
OE
V
tCDD
tDZC
V
tODD
I/O
IH
IL
(Inputs)
V
tDZO
tOFF
tCLZ
tOEZ
Out
V
I/O
(Outputs)
OH
OL
Data
V
tWCS
tWRP
tRWL
tCWL
tWCH
Write Cycle:
WE
V
IH
IL
V
tWRH
V
V
IH
IL
OE
tDS
tDH
I/O
(Inputs)
V
IH
IL
Data In
V
I/O
(Outputs)
V
IH
HI-Z
V
IL
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
23
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
tRC
tRP
tRAS
tRP
V
IH
RAS
CAS
V
tRPC
IL
tCSR
tCP
tCHR
tCRP
tRPC
V
IH
V
IL
tRAH
tASR
V
IH
Address
WE
Row
V
IL
tWTS
tWTH
V
IH
V
IL
V
IH
OE
V
IL
tODD
V
I/O
(Inputs)
IH
HI-Z
V
IL
tCDD
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL15
Test Mode Entry
Semiconductor Group
24
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Test Mode
As the HYB 3117800BSJ is organized internally as 1M x 16-bits, a test mode cycle using 2:1
compression can be used to improve test time. Note that in the 2M x 8 version the test time is
reduced by 1/2 for a N test pattern.
In a test mode “write” the data from each I/O pin is written into two 1M blocks simultaneously (all “1”
s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If the
internal two bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would indicate
a “0”. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test
mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used. Refresh
during test mode operation can be performed by normal read cycles or by WCBR refresh cylces.
Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other
addresses are don’t care.
Semiconductor Group
25
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Package Outlines
Plastic Package P-SOJ-28-3 (400 mil)
(Small Outline J-lead, SMD)
Semiconductor Group
26
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