SP001308154 [INFINEON]

RISC Microcontroller,;


型号：	SP001308154
厂家：	Infineon
描述：	RISC Microcontroller, 微控制器
文件：	总89页 (文件大小：1601K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XMC1400 AA-Step

Microcontroller Series

for Industrial Applications

XMC1000 Family

ARM^®Cortex^®-M0

32-bit processor core

Data Sheet

V1.3 2016-10

Microcontrollers

Edition 2016-10

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

XMC1400 AA-Step

Microcontroller Series

for Industrial Applications

XMC1000 Family

ARM^®Cortex^®-M0

32-bit processor core

Data Sheet

V1.3 2016-10

Microcontrollers

XMC1400 AA-Step

XMC1000 Family

XMC1400 Data Sheet

Revision History: V1.3 2016-10

Previous Versions:

V1.2 2016-08

V1.1 2016-06

V1.0 2016-02

V0.3 2015-10

Page

Subjects

42,

In Absolute Maximum Ratings renamed parameter V_CMto V_INP2, as the

limitation is related to most P2 pins, also if no ACMP is available.

Clarified limit to pins P2.[1,2,6:9,11] in Overload specification.

Corrected XMC1402-T038X0200 and XMC1402-Q048X0200 marking

variants in Table 2

V1.2 2016-08

many

Added XMC™ trademark

11, 13, 15 Added XMC1402-T038X0200, XMC1402-Q040X0200 and

XMC1402-Q048X0200 marking variants

V1.1 2016-06

many

Added TSSOP-38-9 package

11, 13, 15 Added XMC1402-T038 marking variants in TSSOP-38

11, 13, 15 Added XMC1403-Q040 marking variants

V1.0 2016-02

The device provides four USIC channels.

XMC1401 devices available for max. ambient temperature of 85°C.

Reformatted pinout table.

Updated footnote to the definition of the start-up times of OSC_XTAL and

RTC_XTAL oscillators.

Added Δf_LTparameter to on-chip oscillators DCO1 and DCO2.

Updated package outline drawings.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Trademarks

C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.

ARM^®, ARM Powered^®, Cortex^®, Thumb^®and AMBA^®are registered trademarks of

ARM, Limited.

CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are

trademarks of ARM, Limited.

We Listen to Your Comments

Is there any information in this document that you feel is wrong, unclear or missing?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

mcdocu.comments@infineon.com

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Table of Contents

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.1

1.2

1.3

1.4

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Port Pin for Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 32

3.1

Electrical Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . . 54

Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Power-Up and Supply Threshold Characteristics . . . . . . . . . . . . . . . . . 71

On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 74

SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 76

Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 81

3.1.1

3.1.2

3.1.3

3.1.4

3.2

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.2.7

3.2.8

3.3

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

3.3.6.1

3.3.6.2

3.3.6.3

Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.1

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Table of Contents

4.1.1

4.2

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

About this Document

This Data Sheet is addressed to embedded hardware and software developers. It

provides the reader with detailed descriptions about the ordering designations, available

features, electrical and physical characteristics of the XMC1400 series devices.

The document describes the characteristics of a superset of the XMC1400 series

devices. For simplicity, the various device types are referred to by the collective term

XMC1400 throughout this document.

XMC1000 Family User Documentation

The set of user documentation includes:

•

Reference Manual

– decribes the functionality of the superset of devices.

Data Sheets

•

– list the complete ordering designations, available features and electrical

characteristics of derivative devices.

•

Errata Sheets

– list deviations from the specifications given in the related Reference Manual or

Data Sheets. Errata Sheets are provided for the superset of devices.

Attention: Please consult all parts of the documentation set to attain consolidated

knowledge about your device.

Application related guidance is provided by Users Guides and Application Notes.

Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions

of those documents.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Summary of Features

The XMC1400 devices are members of the XMC1000 Family of microcontrollers based

on the ARM Cortex-M0 processor core. The XMC1400 series addresses the real-time

control needs of motor control and digital power conversion. It also features peripherals

for LED Lighting applications and Human-Machine Interface (HMI).

CPU

Analog

System

SWD

SPD

ARM^®

Cortex^®

Debug

System

–

EVR

2 x DCO

DTS

NVIC

ANACTRL

AHB to APB

Bridge

PRNG

PAU

AHB-Lite Bus

FLASH

MATH

WDT

SCU

USIC0

USIC1

VADC

SRAM

CCU40

CCU41

CCU80

ROM

MultiCAN+

BCCU0

PORTS

RTC

ACMP &

ORC

ERU0

ERU1

LEDTS0

LEDTS1

LEDTS2

CCU81

POSIF0

POSIF1

Figure 1

Block Diagram

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Features

CPU subsystem

•

32-bit ARM Cortex-M0 CPU Core

– 0.84 DMIPS/MHz (Dhrystone 2.1) at

48 MHz

Nested Vectored Interrupt Controller

64 interrupt nodes

MATH coprocessor

Analog Frontend Peripherals

•

A/D Converters (up to 12 analog inputs)

– 2 sample and hold stages

– fast 12-bit ADC (up to 1.1 MS/s),

adjustable gain

•

– 0 V to 5.5 V input range

– 24-bit

(CORDIC)

– 32-bit divide operation

2x4 channels ERU

interconnections

On-Chip Memories

trigonometric

calculation

•

Up to

channels out of range

comparators

•

Up to 4 fast analog comparators

Temperature Sensor

•

for

event

Industrial Control Peripherals

•

2x4 16-bit 96 MHz CCU4 timers for signal

monitoring and PWM

•

8 Kbyte ROM

16 Kbyte SRAM (with parity)

up to 200 Kbyte Flash (with ECC)

•

2x4 16-bit 96 MHz CCU8 timers for

complex PWM, complementary high/low

side switches and multi phase control

2x POSIF for hall and quadrature

encoders, motor positioning

Supply, Reset and Clock

•

1.8 V to 5.5 V supply with power on reset

and brownout detector

On-chip clock monitor

External crystal oscillator support (32 kHz

and 4 to 20 MHz)

Internal slow and fast oscillators without

the need of PLL

•

9 channel BCCU (brightness and color

control) for LED lighting applications

Up to 56 Input/Output Ports

•

1.8 V to 5.5 V capable

up to 8 high current pads (50 mA sink)

System Control

On-Chip Debug Support

•

Window watchdog

Real time clock module

Pseudo random number generator

•

4 breakpoints, 2 watchpoints

ARM serial wire debug, single-pin debug

interfaces

Communication Peripherals

Programming Support

•

Four USIC channels, usable as

– UART (up to 12 Mb/s)

– single-SPI (up to 12 Mb/s)

– double-SPI (up to 2 × 12 Mb/s)

– quad-SPI (up to 4 × 12 Mb/s)

– IIC (up to 400 kb/s)

•

Single-pin bootloader

Secure bootstrap loader SBSL (optional)

Packages

•

TSSOP-38 (9.7 × 6.4 mm²)

VQFN-40/48/64 (5×5/7×7/8×8 mm²)

LQFP-64 (12 × 12 mm²)

– IIS (up to 12 Mb/s)

Tools

– LIN interfaces (20kb/s)

•

LEDTS in Human-Machine interface

– up to 24 touch pads

– drive up to 144 LEDs

MultiCAN+, Full-CAN/Basic-CAN with 2

nodes, 32 message objects (up to

1 MBaud)

•

Free DAVE™ toolchain with low

level drivers and apps

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

1.1

Device Overview

The following table lists the available features per device type for the XMC1400 series.

Table 1

Features of XMC1400 Device Types¹⁾

Features

CPU frequency 48 MHz

Operating

temperature

(ambient)

-40 to

85 °C

-40 to 105 °C

Operating

voltage

1.8 V to 5.5 V

Flash options

(Kbytes)

64, 64, 32, 32, 32, 64, 64, 64, 64, 64, 64, 64, 64,

128 128 64, 64, 64, 128 128 128 128 128 128 128 128

128 128 128 200 200 200 200 200 200 200 200

200 200 200

SRAM (Kbytes) 16 16 16 16 16 16 16 16 16 16 16 16 16

MATH

CCU4

CCU8

POSIF

BCCU

USIC

2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 /

(modules /

channels)

LEDTS

MultiCAN+ -

(nodes /

2 / 2 / 2 / 2 / 2 / 2 /

32 32 32 32 32 32

MOs)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Table 1

Features of XMC1400 Device Types¹⁾(cont’d)

Features

ADC

2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 / 2 /

(kernels / 12 12 12 12 12 12 12 12 12 12 12 12 12

analog

inputs)

ACMP

GPIOs

34 48 26 27 34 48 48 27 34 48 34 48 48

GPIs

Packages

1) Features that are not included in this table are available in all the derivatives

1.2

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a

specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:

•

<DDD> the derivatives function set

<Z> the package variant

– T: TSSOP

– Q: VQFN

– F: LQFP

•

<PPP> package pin count

<T> the temperature range:

– F: -40°C to 85°C

– X: -40°C to 105°C

•

<FFFF> the Flash memory size in Kbytes.

For ordering codes for the XMC1400 please contact your sales representative or local

distributor.

This document describes several derivatives of the XMC1400 series, some descriptions

may not apply to a specific product. Please see Table 2.

For simplicity the term XMC1400 is used for all derivatives throughout this document.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

1.3

Device Types

These device types are available and can be ordered through Infineon’s direct and/or

distribution channels.

Table 2

Synopsis of XMC1400 Device Types

Package

Derivative

Flash Kbytes

XMC1401-Q048F0064

XMC1401-Q048F0128

XMC1401-F064F0064

XMC1401-F064F0128

XMC1402-T038X0032

XMC1402-T038X0064

XMC1402-T038X0128

XMC1402-T038X0200

XMC1402-Q040X0032

XMC1402-Q040X0064

XMC1402-Q040X0128

XMC1402-Q040X0200

XMC1402-Q048X0032

XMC1402-Q048X0064

XMC1402-Q048X0128

XMC1402-Q048X0200

XMC1402-Q064X0064

XMC1402-Q064X0128

XMC1402-Q064X0200

XMC1402-F064X0064

XMC1402-F064X0128

XMC1402-F064X0200

XMC1403-Q040X0064

XMC1403-Q040X0128

XMC1403-Q040X0200

XMC1403-Q048X0064

XMC1403-Q048X0128

PG-VQFN-48

PG-LQFP-64

PG-TSSOP-38

PG-VQFN-40

PG-VQFN-48

PG-VQFN-64

PG-LQFP-64

PG-VQFN-40

PG-VQFN-48

128

200

128

200

128

200

128

200

128

200

128

200

128

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Table 2

Synopsis of XMC1400 Device Types (cont’d)

Derivative

Package

Flash Kbytes

XMC1403-Q048X0200

XMC1403-Q064X0064

XMC1403-Q064X0128

XMC1403-Q064X0200

XMC1404-Q048X0064

XMC1404-Q048X0128

XMC1404-Q048X0200

XMC1404-Q064X0064

XMC1404-Q064X0128

XMC1404-Q064X0200

XMC1404-F064X0064

XMC1404-F064X0128

XMC1404-F064X0200

PG-VQFN-48

PG-VQFN-64

PG-VQFN-48

PG-VQFN-64

PG-LQFP-64

200

128

200

128

200

128

200

128

200

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

1.4

Chip Identification Number

The Chip Identification Number allows software to identify the marking. It is an 8 words

value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at

address location : 1000 0F00_H(MSB) - 1000 0F1B_H(LSB). The least significant word and

most significant word of the Chip Identification Number are the value of registers

DBGROMID and IDCHIP, respectively.

Table 3

XMC1400 Chip Identification Number

Value

Derivative

Marking

XMC1401-Q048F0064

XMC1401-Q048F0128

XMC1401-F064F0064

XMC1401-F064F0128

XMC1402-T038X0032

XMC1402-T038X0064

XMC1402-T038X0128

XMC1402-T038X0200

XMC1402-Q040X0032

XMC1402-Q040X0064

XMC1402-Q040X0128

XMC1402-Q040X0200

XMC1402-Q048X0032

00014082 07CF00FF 1E071FF7 20006000

00000D00 00001000 00011000 10204083_H

00014082 07CF00FF 1E071FF7 20006000

00000D00 00001000 00021000 10204083_H

000140A2 07CF00FF 1E071FF7 20006000

00000D00 00001000 00011000 10204083_H

000140A2 07CF00FF 1E071FF7 20006000

00000D00 00001000 00021000 10204083_H

00014013 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00009000 10204083_H

00014013 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00011000 10204083_H

00014013 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00021000 10204083_H

00014013 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00033000 10204083_H

00014043 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00009000 10204083_H

00014043 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00011000 10204083_H

00014043 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00021000 10204083_H

00014043 07FF00FF 1E071FF7 000F900F

00000D00 00001000 00033000 10204083_H

00014083 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00009000 10204083_H

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Table 3

XMC1400 Chip Identification Number (cont’d)

Derivative

Value

Marking

XMC1402-Q048X0064

XMC1402-Q048X0128

XMC1402-Q048X0200

XMC1402-Q064X0064

XMC1402-Q064X0128

XMC1402-Q064X0200

XMC1402-F064X0064

XMC1402-F064X0128

XMC1402-F064X0200

XMC1403-Q040X0064

XMC1403-Q040X0128

XMC1403-Q040X0200

XMC1403-Q048X0064

XMC1403-Q048X0128

XMC1403-Q048X0200

XMC1403-Q064X0064

XMC1403-Q064X0128

00014083 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00011000 10204083_H

00014083 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00021000 10204083_H

00014083 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00033000 10204083_H

00014093 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00011000 10204083_H

00014093 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00021000 10204083_H

00014093 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00033000 10204083_H

000140A3 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00011000 10204083_H

000140A3 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00021000 10204083_H

000140A3 07FF00FF 1E071FF7 100F900F

00000D00 00001000 00033000 10204083_H

00014043 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00011000 10204083_H

00014043 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00021000 10204083_H

00014043 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00033000 10204083_H

00014083 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00011000 10204083_H

00014083 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00021000 10204083_H

00014083 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00033000 10204083_H

00014093 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00011000 10204083_H

00014093 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00021000 10204083_H

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Table 3

XMC1400 Chip Identification Number (cont’d)

Derivative

Value

Marking

XMC1403-Q064X0200

XMC1404-Q048X0064

XMC1404-Q048X0128

XMC1404-Q048X0200

XMC1404-Q064X0064

XMC1404-Q064X0128

XMC1404-Q064X0200

XMC1404-F064X0064

XMC1404-F064X0128

XMC1404-F064X0200

00014093 07CF00FF 1E071FF7 00B00000

00000D00 00001000 00033000 10204083_H

00014083 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00011000 10204083_H

00014083 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00021000 10204083_H

00014083 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00033000 10204083_H

00014093 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00011000 10204083_H

00014093 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00021000 10204083_H

00014093 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00033000 10204083_H

000140A3 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00011000 10204083_H

000140A3 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00021000 10204083_H

000140A3 07FF00FF 1E071FF7 30BFF00F

00000D00 00001000 00033000 10204083_H

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

This section summarizes the logic symbols and package pin configurations with a

detailed list of the functional I/O mapping.

2.1

Logic Symbols

V_DDP

(2)

V_SSP

(2)

Port 0

12 bit

Port 0 / XTAL

4 bit

XMC1400

TSSOP-38

Port 1 / High-current

6 bit

Port 2 / Analog input

4 bit

Port 2 / Analog input

8 bit

Figure 2

XMC1400 Logic Symbol for TSSOP-38-9

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

V_DDV_SSV_DDPV_SSP

(1) (1) (2) (1)

Exp. Die Pad

V_SSP

(

)

Port 0

12 bit

Port 0 / XTAL

4 bit

XMC1400

VQFN-40

Port 1 / High-current

7 bit

Port 2 / Analog input

4 bit

Port 2 / Analog input

8 bit

Figure 3

XMC1400 Logic Symbol for PG-VQFN-40-17

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

V_DDV_SS

V_DDPV_SSP

(1) (1) (3) (1)

Exp. Die Pad

V_SSP

(

)

Port 0

12 bit

Port 0 / XTAL

4 bit

Port 1 / High-current

7 bit

XMC1400

VQFN-48

Port 2 / Analog input

6 bit

Port 2 / Analog input

8 bit

Port 3

1 bit

Port 4

4 bit

Figure 4

XMC1400 Logic Symbol for PG-VQFN-48-73

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

V_DDV_SSV_DDPV_SSP

(1) (1)

(4) (2)

1) VQFN64 only

Exp. Die Pad

V_SSP

(

)

Port 0

12 bit

Port 0 / XTAL

4 bit

Port 1 / High-current

8 bit

XMC1400

VQFN-64 / LQFP-64

Port 1

1 bit

Port 2 / Analog input

6 bit

Port 2 / Analog input

8 bit

Port 3

5 bit

Port 4

12 bit

Figure 5

XMC1400 Logic Symbol for PG-LQFP-64-26 / PG-VQFN-64-6

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

2.2

Pin Configuration and Definition

The following figures summarize all pins, showing their locations on the different

packages.

P2.4

P2.5

P2.3

Top View

P2.2

P2.6

P2.1

P2.7

P2.0

P2.8

P0.15

P0.14

P0.13

P2.9

P2.10

P2.11

_SSP/V_SS

P0.12

P0.11

P0.10

V_DDP/V_DD

P1.5

P1.4

P1.3

P0.9

P0.8

V_DDP

P1.2

P1.1

P1.0

V_SSP

P0.7

P0.6

P0.5

P0.4

P0.3

P0.0

P0.1

P0.2

Figure 6

XMC1400 PG-TSSOP-38-9 Pin Configuration (top view)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

Analog input / P2.0

Analog input / P2.1

Analog input / P2.2

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

Analog input / P2.3

Analog input / P2.4

Analog input / P2.5

Analog input / P2.6

Analog input / P2.7

Analog input / P2.8

Analog input / P2.9

P1.0 / High-current

P1.1 / High-current

Figure 7

XMC1400 PG-VQFN-40-17 Pin Configuration (top view)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

P4.6

P4.7

P0.7

P0.6

P0.5

P0.4

P0.3

Analog input / P2.0

Analog input / P2.1

Analog input / P2.2

Analog input / P2.3

Analog input / P2.4

Analog input / P2.5

Analog input / P2.6

P0.2

P0.1

P0.0

P3.0

V_DDP

Analog input / P2.7

Analog input / P2.8

Analog input / P2.9

P1.0 / High-current

P1.1 / High-current

Figure 8

XMC1400 PG-VQFN-48-73 Pin Configuration (top view)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

V_SSP

V_DDP

P0.7

P0.6

P0.5

P0.4

P0.3

P4.6

P4.7

P4.8

P4.9

P0.2

P0.1

P4.10

P4.11

P0.0

P3.4

Analog input / P2.0

Analog input / P2.1

Analog input / P2.2

Analog input / P2.3

Analog input / P2.4

Analog input / P2.5

Analog input / P2.6

P3.3

P3.2

P3.1

P3.0

V_DDP

P1.0 / High-current

P1.1 / High-current

Analog input / P2.7

Figure 9

XMC1400 PG-LQFP-64-26 / PG-VQFN-64-6 Pin Configuration (top

view)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

2.2.1

Package Pin Summary

The following general building block is used to describe each pin:

Table 4

Function

Px.y

Package Pin Mapping Description

Package A

Package B

...

Pad Type

Pad Class

The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),

followed by the supply pins.

The following columns, titled with the supported package variants, lists the package pin

number to which the respective function is mapped in that package.

The “Pad Type” indicates the employed pad type:

•

STD_INOUT (standard bi-directional pads)

STD_INOUT/AN (standard bi-directional pads with analog input)

STD_INOUT/clock (standard bi-directional pads with oscillator function)

High Current (high current bi-directional pads)

STD_IN/AN (standard input pads with analog input)

Power (power supply)

Details about the pad properties are defined in the Electrical Parameter chapter.

Table 5 Package Pin Mapping

Function LQFP

VQFN

TSSOP Pad Type

Notes

64,

VQFN

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

STD_INOUT

P0.8/

RTC_

XTAL1

STD_INOUT

/clock_IN

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

Table 5

Package Pin Mapping (cont’d)

Function LQFP

VQFN

TSSOP Pad Type

Notes

64,

VQFN

P0.9/

RTC_

XTAL2

STD_INOUT

/clock_O

P0.10/

XTAL1

STD_INOUT

/clock_IN

P0.11/

XTAL2

STD_INOUT

/clock_O

P0.12

P0.13

P0.14

P0.15

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P1.8

P2.0

STD_INOUT

High Current

STD_INOUT

/AN

P2.1

STD_INOUT

/AN

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

STD_IN/AN

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

Table 5

Package Pin Mapping (cont’d)

Function LQFP

VQFN

TSSOP Pad Type

Notes

64,

VQFN

P2.8

P2.9

P2.10

STD_IN/AN

STD_INOUT

/AN

P2.11

P2.12

P2.13

STD_INOUT

/AN

STD_INOUT

/AN

STD_INOUT

/AN

P3.0

P3.1

P3.2

P3.3

P3.4

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

P4.8

P4.9

P4.10

P4.11

VSS

STD_INOUT

Power

Supply GND, ADC

reference GND

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

Table 5

Package Pin Mapping (cont’d)

Function LQFP

VQFN

TSSOP Pad Type

Notes

64,

VQFN

VDD

Power

Supply VDD, ADC

reference voltage/

ORC reference

voltage

VDDP

When VDD is

supplied, VDDP

has to be supplied

with the same

voltage.

VDDP

VSSP

Power

I/O port supply

I/O port ground

Exp.

Pad

(in

VQFN

64 only)

Exp.

Pad

Exp.

Pad

Exposed Die Pad

The exposed die

pad is connected

internallytoVSSP.

For proper

operation, it is

mandatory to

connect the

exposed pad to

the board ground.

For thermal

aspects, please

refer to the

Package and

Reliability chapter.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

2.2.2

Port Pin for Boot Modes

Port functions can be overruled by the boot mode selected. The type of boot mode is

selected via BMI. Table 6 shows the port pins used for the various boot modes.

Table 6

Port Pin for Boot Modes

Boot

Boot Description

P0.13

P0.14

CS(O)

SWDIO_0

SPD_0

RX/TX

SSC BSL mode

Debug mode (SWD)

Debug mode (SPD)

ASC BSL half-duplex mode

ASC BSL full-duplex mode

CAN BSL mode

SCLK(O)

SWDCLK_0

SSC BSL mode

P0.15

Debug mode (SWD)

ASC BSL full-duplex mode

CAN BSL mode

DATA(I/O)

SWDCLK_1

SSC BSL mode

P1.2

P1.3

Debug mode (SWD)

ASC BSL full-duplex mode

CAN BSL mode

SWDIO_1

SPD_1

RX/TX

Debug mode (SWD)

Debug mode (SPD)

ASC BSL half-duplex mode

ASC BSL full-duplex mode

CAN BSL mode

P4.6

P4.7

HWCON0

HWCON1

Boot Pins

(Boot from pins mode must be selected)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

2.2.3

Port I/O Function Description

The following general building block is used to describe the I/O functions of each PORT

pin:

Table 7

Port I/O Function Description

Outputs

Function

Inputs

ALT1

ALTn

Input

P0.0

Pn.y

MODA.OUT

MODC.INA

MODA.INA

MODA.OUT

MODC.INB

Pn.y

XMC1000

Control Logic

PAD

V_DDP

Input 0

...

MODA.INA

Input n

HWI0

MODA

MODB

Pn.y

HWI1

ALT1

MODB.OUT

...

ALTn

HWO0

HWO1

GND

Figure 10

Simplified Port Structure

Pn.y is the port pin name, defining the control and data bits/registers associated with it.

As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT

defines the output value.

Up to nine alternate output functions (ALT1 to ALT9) can be mapped to a single port pin,

selected by Pn_IOCR.PC. The output value is directly driven by the respective module,

with the pin characteristics controlled by the port registers (within the limits of the

connected pad).

The port pin input can be connected to multiple peripherals. Most peripherals have an

input multiplexer to select between different possible input sources.

The input path is also active while the pin is configured as output. This allows to feedback

an output to on-chip resources without wasting an additional external pin.

Please refer to the Port I/O Functions table for the complete Port I/O function mapping.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

General Device Information

2.2.4

Hardware Controlled I/O Function Description

The following general building block is used to describe the hardware I/O and pull control

functions of each PORT pin:

Table 8

Hardware Controlled I/O Function Description

Function

Outputs

HWO0

Inputs

Pull Control

HW0_PD

HWI0

HW0_PU

P0.0

Pn.y

MODB.OUT

MODB.INA

MODC.OUT

By Pn_HWSEL, it is possible to select between different hardware “masters”

(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).

Hardware control overrules settings in the respective port pin registers. Additional

hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the

peripherals can be used to control the pull devices of the pin.

Please refer to the Hardware Controlled I/O Functions table for the complete hardware

I/O and pull control function mapping.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

Port I/O Function Table

Table 9

Port I/O Functions

Function

Outputs

ALT5

Inputs

Input

ALT1

ALT2

ALT3

ALT4

ALT6

ALT7

ALT8

ALT9

Input

Input Input

Input

P0.0

P0.1

P0.2

P0.3

P0.4

ERU0.P LEDTS0 ERU0.G CCU40. CCU80. USIC0_ USIC0_ CCU81. USIC1_ BCCU0. CCU40.I

DOUT0 .LINE7 OUT0 OUT0 OUT00 CH0.SE CH1.SE OUT00 CH1.DO TRAPIN N0AC

LO0 LO0 UT0

USIC1_ USIC0_

CH1.DX CH0.D

USIC0_

CH1.DX

X2A

ERU0.P LEDTS0 ERU0.G CCU40. CCU80. BCCU0. SCU.VD USIC1_ USIC1_

CCU40.I

N1AC

USIC1_ USIC1_

CH1.DX CH1.D

DOUT1 .LINE6 OUT1

OUT1

OUT01 OUT8

ROP

CH1.SC CH1.DO

LKOUT UT0

X1A

ERU0.P LEDTS0 ERU0.G CCU40. CCU80. VADC0. CCU80. USIC1_ USIC1_

CCU40.I

N2AC

USIC1_ USIC1_

CH0.DX CH0.D

DOUT2 .LINE5 OUT2

OUT2

OUT02 EMUX02 OUT10 CH0.SC CH0.DO

LKOUT UT0

X1A

ERU0.P LEDTS0 ERU0.G CCU40. CCU80. VADC0. CCU80. USIC1_ USIC1_

CCU40.I

N3AC

USIC1_

CH0.DX

DOUT3 .LINE4 OUT3

OUT3

OUT03 EMUX01 OUT11 CH1.SC CH0.DO

LKOUT UT0

BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. VADC0. WWDT. USIC1_ CAN.N0

CCU41.I CCU80.I

N0AB N0AB

CAN.N0

_RXDA

OUT0

.LINE3 .COL3 OUT1

OUT13 EMUX00 SERVIC CH1.SE _TXD

E_OUT LO0

P0.5

P0.6

BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. ACMP2. CCU80. VADC0. CAN.N0

OUT1 .LINE2 .COL2 OUT0 OUT12 OUT OUT01 EMUX10 _TXD

CCU41.I CCU80.I

N1AB N1AB

CAN.N0

_RXDB

BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ VADC0. CCU41.

CCU40.I CCU41.I

N0AB N2AB

USIC0_

CH1.DX

OUT2

.LINE1 .COL1 OUT0

OUT11 CH1.MC CH1.DO EMUX11 OUT0

LKOUT UT0

P0.7

BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ VADC0. CCU41.

CCU40.I CCU41.I

USIC0_ USIC0_ USIC0_

CH0.D CH1.DX CH1.DX

OUT3

.LINE0 .COL0 OUT1

OUT10 CH0.SC CH1.DO EMUX12 OUT1

LKOUT UT0

N1AB

N3AB

X1C

P0.8/

BCCU0. LEDTS1 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ CCU81. CCU41.

CCU40.I

N2AB

USIC0_

CH0.D

X1B

USIC0_

CH1.DX

RTC_XTAL1 OUT4

.LINE0 .COLA OUT2

OUT20 CH0.SC CH1.SC OUT20 OUT2

LKOUT LKOUT

P0.9/

BCCU0. LEDTS1 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ CCU81. CCU41.

.LINE1 .COL6 OUT3 OUT21 CH0.SE CH1.SE OUT21 OUT3

LO0 LO0

CCU40.I

N3AB

USIC0_

CH0.D

X2B

USIC0_

CH1.DX

RTC_XTAL2 OUT5

P0.10/

XTAL1

BCCU0. LEDTS1 LEDTS0 ACMP0. CCU80. USIC0_ USIC0_ CCU81.

OUT6 .LINE2 .COL5 OUT OUT22 CH0.SE CH1.SE OUT22

LO1 LO1

CCU80.I CCU81.I

N2AB N2AB

USIC0_

CH0.D

X2C

USIC0_

CH1.DX

P0.11/

XTAL2

BCCU0. LEDTS1 LEDTS0 USIC0_ CCU80. USIC0_ USIC0_ CCU81.

OUT7 .LINE3 .COL4 CH0.MC OUT23 CH0.SE CH1.SE OUT23

LKOUT LO2 LO2

USIC0_

CH0.D

X2D

USIC0_

CH1.DX

P0.12

BCCU0. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ CCU80.

CAN.N1 BCCU0. CCU40.I CCU40.I CCU40.I CCU81.I CCU40.I CCU80.I USIC0_ CCU80.I CCU80.I CAN.N1 CCU80.I

OUT6

.LINE4 .COL3 .COL3 OUT33 CH0.SE OUT20

LO3

_TXD

TRAPIN N0AA

N1AA

N2AA

N0AU

N3AA

N0AA

CH0.D N1AA

X2E

N2AA

_RXDA N3AA

Table 9

Port I/O Functions (cont’d)

Function

Outputs

Inputs

Input

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

Input

Input Input

Input

P0.13

P0.14

P0.15

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P1.8

P2.0

P2.1

WWDT. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ CCU80.

SERVIC .LINE5 .COL2 .COL2 OUT32 CH0.SE OUT21

CAN.N1

_TXD

CCU80.I CCU81.I POSIF0.

N3AB N1AU IN0B

USIC0_

CH0.D

X2F

CAN.N1

_RXDB

E_OUT

LO4

BCCU0. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_

OUT7 .LINE6 .COL1 .COL1 OUT31 CH0.DO CH0.SC

UT0 LKOUT

CAN.N0

_TXD

CCU81.I POSIF0. USIC0_ USIC0_ USIC1_

N2AU IN1B CH0.DX CH0.D CH1.DX

0A X1A 5B

CAN.N0

_RXDC

BCCU0. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_

OUT8 .LINE7 .COL0 .COL0 OUT30 CH0.DO CH1.MC

UT0 LKOUT

CAN.N0

_TXD

CCU81.I POSIF0. USIC0_

USIC1_ USIC1_ CAN.N0

CH1.DX CH1.DX _RXDD

N3AU

IN2B

CH0.DX

BCCU0. CCU40. LEDTS0 LEDTS1 CCU80. ACMP1. USIC0_ CCU81. CAN.N0

POSIF0. USIC0_

IN2A

CAN.N0

_RXDG

OUT0

.COL0 .COLA OUT00 OUT

CH0.DO OUT00 _TXD

UT0

CH0.DX

ERU1.P CCU40. LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N0

DOUT1 OUT1 .COL1 .COL0 OUT01 CH0.DO CH1.SE OUT01 _TXD

UT0 LO0

POSIF0. USIC0_ USIC0_

IN1A

USIC0_ CAN.N0

CH1.DX _RXDH

CH0.DX CH0.D

X1D

ERU1.P CCU40. LEDTS0 LEDTS1 CCU80. ACMP2. USIC0_ CCU81. CAN.N1

POSIF0.

IN0A

USIC0_

CH1.DX

CAN.N1

_RXDG

DOUT2 OUT2

.COL2 .COL1 OUT10 OUT

CH1.DO OUT10 _TXD

UT0

ERU1.P CCU40. LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N1

USIC0_ USIC0_ CAN.N1

CH1.DX CH1.DX _RXDH

DOUT3 OUT3

.COL3 .COL2 OUT11 CH1.SC CH1.DO OUT11 _TXD

LKOUT UT0

ERU1.P USIC0_ LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CCU41.

DOUT0 CH1.SC .COL4 .COL3 OUT20 CH0.SE CH1.SE OUT20 OUT0

USIC0_

CH0.DX

USIC0_

CH1.DX

LKOUT

LO0

LO1

ERU1.P USIC0_ LEDTS0 BCCU0. CCU80. USIC0_ USIC0_ CCU81. CCU41.

USIC0_

CH1.DX

DOUT1 CH0.DO .COLA OUT1

UT0

OUT21 CH0.SE CH1.SE OUT21 OUT1

LO1 LO2

ERU1.P USIC0_ LEDTS0 USIC0_ BCCU0. USIC0_ USIC0_ CCU81. CCU41.

DOUT2 CH1.DO .COL5 CH0.SC OUT2 CH0.SE CH1.SE OUT30 OUT2

UT0 LKOUT LO2 LO3

POSIF1. USIC0_

IN2A

CH0.DX

BCCU0. CCU40. LEDTS0 LEDTS1

OUT8 OUT3 .COL6 .COL4

ACMP3. ERU1.P CCU81. CCU41.

OUT DOUT3 OUT31 OUT3

POSIF1. USIC1_

IN1A

USIC1_

CH1.DX

CH0.DX

BCCU0. CCU40. USIC1_ VADC0.

ACMP1. ERU1.P CCU81.

OUT DOUT0 OUT32

POSIF1. USIC1_ USIC1_

IN0A CH0.DX CH0.D

3B X4B

USIC1_

CH1.DX

OUT0

CH1.SC EMUX02

LKOUT

ERU0.P CCU40. ERU0.G LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N0

DOUT3 OUT0 OUT3 .COL5 OUT20 CH0.DO CH0.SC OUT20 _TXD

UT0 LKOUT

VADC0.

G0CH5

USIC0_ USIC0_

CH0.DX CH0.D

USIC0_ CAN.N0 ERU0.0

CH1.DX _RXDE B0

X1E

ERU0.P CCU40. ERU0.G LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N0 ACMP2.I VADC0.

DOUT2 OUT1 OUT2 .COL6 OUT21 CH0.DO CH1.SC OUT21 _TXD NP G0CH6

UT0 LKOUT

USIC0_

CH0.DX

USIC0_ USIC0_ CAN.N0 ERU0.1

CH1.DX CH1.DX _RXDF B0

Table 9

Port I/O Functions (cont’d)

Function

Outputs

Inputs

Input

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

Input

Input Input

Input

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P3.0

P3.1

ACMP2.I VADC0.

NN G0CH7

ORC0.AI USIC1_

USIC0_ USIC0_ USIC0_

CH0.DX CH0.D CH1.DX

ERU0.0

CH0.DX

X4A

VADC0. ORC1.AI USIC1_ USIC1_ USIC1_ USIC0_ USIC0_ USIC0_

G1CH5 CH0.DX CH0.DX CH1.DX CH0.D CH1.DX CH1.DX

3E 4E 5C X5B 3C 4C

ERU0.1

VADC0. ORC2.AI USIC1_ USIC1_ USIC0_ USIC0_ USIC1_ USIC0_

G1CH6 CH1.DX CH1.DX CH0.DX CH0.D CH0.DX CH1.DX

ERU0.0

X4B

VADC0. ORC3.AI USIC1_

USIC0_

CH0.DX

USIC0_ USIC0_

CH1.DX CH1.DX

ERU0.1

G1CH7

CH1.DX

ACMP1.I VADC0.

ORC4.AI USIC1_ USIC1_ USIC0_ USIC0_ USIC0_

N CH1.DX CH1.DX CH0.DX CH0.D CH1.DX

ERU0.2

G0CH0

X4E

ACMP1.I

VADC0. ORC5.AI USIC1_

USIC0_

CH0.DX

USIC0_ USIC0_

CH1.DX CH1.DX

ERU0.3

G1CH1

CH1.DX

ACMP0.I VADC0. VADC0. ORC6.AI

NN G0CH1 G1CH0

USIC0_ USIC0_ USIC0_

CH0.DX CH0.D CH1.DX

ERU0.3

X4D

ACMP0.I VADC0. VADC0. ORC7.AI

USIC0_

CH0.DX

USIC0_ USIC0_

CH1.DX CH1.DX

ERU0.3

G0CH2 G1CH4 N

ERU0.P CCU40. ERU0.G LEDTS1 CCU80. ACMP0. USIC0_

CAN.N1

_TXD

VADC0. VADC0.

G0CH3 G1CH2

USIC0_ USIC0_ USIC0_

CH0.DX CH0.D CH1.DX

CAN.N1 ERU0.2

_RXDE B0

DOUT1 OUT2

OUT1

.COL4 OUT30 OUT

CH1.DO

UT0

X4C

ERU0.P CCU40. ERU0.G LEDTS1 CCU80. USIC0_ USIC0_

CAN.N1 ACMP.R VADC0. VADC0.

USIC0_ USIC0_ CAN.N1 ERU0.2

CH1.DX CH1.DX _RXDF B1

DOUT0 OUT3

OUT0

.COL3 OUT31 CH1.SC CH1.DO

LKOUT UT0

_TXD

G0CH4 G1CH3

BCCU0. VADC0. USIC1_ USIC1_

ACMP2. USIC1_ LEDTS2

ACMP3.I

USIC1_ USIC1_ USIC1_ USIC1_

CH0.DX CH0.D CH1.DX CH1.DX

ERU1.3

OUT3

EMUX00 CH0.SC CH1.SC

LKOUT LKOUT

OUT

CH1.DO .COL6

UT0

X4A

BCCU0. CCU40. USIC1_ CCU81.

VADC0. USIC1_ CCU81. CCU41. ACMP3.I

USIC1_

CH0.DX

USIC1_

CH1.DX

ERU1.3

OUT4

OUT3

CH0.MC OUT31

LKOUT

EMUX01 CH1.DO OUT33 OUT3

UT0

BCCU0. USIC1_ USIC1_ LEDTS2 CCU80. ACMP1. USIC1_ CCU81. CCU41. BCCU0. CCU41.I CCU41.I CCU41.I CCU41.I CCU81.I CCU81.I CCU81. USIC1_ USIC1_ CCU81.I ERU1.0

OUT0

CH1.DO CH1.SC .COLA OUT21 OUT

UT0 LKOUT

CH0.SE OUT21 OUT0

LO1

TRAPIN N0AA

N1AA

N2AA

N3AA

N0AA

N1AA

IN2AA CH1.DX CH1.DX N3AA

BCCU0. USIC1_

LEDTS2 CCU80. ACMP3. USIC1_ CCU81. CCU41.

USIC1_ USIC1_

CH0.D CH1.DX

ERU1.1

OUT1

CH1.DO

UT0

.COL0 OUT20 OUT

CH0.SE OUT20 OUT1

LO0

X2F

Table 9

Port I/O Functions (cont’d)

Function

Outputs

Inputs

Input

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

Input

Input Input

Input

P3.2

P3.3

P3.4

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

P4.8

P4.9

BCCU0. USIC1_

LEDTS2 CCU80. ACMP2. USIC1_ CCU81. CCU41.

USIC1_ USIC1_ USIC1_ USIC1_

CH0.DX CH0.D CH1.DX CH1.DX

ERU1.2

OUT2

CH1.SC

LKOUT

.COL1 OUT11 OUT

CH0.SC OUT11 OUT2

LKOUT

X4C

BCCU0. USIC1_

LEDTS2 CCU80. ACMP0. USIC1_ CCU81. CCU41.

USIC1_

CH0.DX

USIC1_

CH1.DX

ERU1.1

OUT5

CH0.DO

UT0

.COL2 OUT10 OUT

CH1.SE OUT10 OUT3

LO0

BCCU0. USIC1_ USIC1_ LEDTS2 CCU80. USIC1_ USIC1_ CCU81.

OUT6 CH0.DO CH0.SC .COL3 OUT01 CH1.MC CH1.SE OUT01

UT0 LKOUT LKOUT LO1

USIC1_ USIC1_

CH0.DX CH0.D

USIC1_

CH1.DX

ERU1.2

X1E

BCCU0. ERU1.P LEDTS2 ERU1.G CCU40. ACMP1. USIC1_ CCU81. CCU41.

CCU40.I CCU41.I CCU80.I

N0BA N0AC N0AU

USIC1_ USIC1_

CH0.DX CH0.D

OUT0

DOUT0 .COL5 OUT0

OUT0

OUT

CH1.SE OUT10 OUT0

LO1

X4D

BCCU0. ERU1.P LEDTS2 ERU1.G CCU40. ACMP3. USIC1_ CCU81. CCU41.

CCU40.I CCU41.I CCU80.I

N1BA N1AC N1AU

POSIF1. USIC1_

OUT8

DOUT1 .COL4 OUT1

OUT1

OUT

CH1.SE OUT11 OUT1

LO2

IN0B

CH0.DX

BCCU0. ERU1.P CCU81. ERU1.G CCU40. ACMP2. USIC1_ CCU81. CCU41.

CCU40.I CCU41.I CCU80.I CCU81.I POSIF1. USIC1_

OUT4

DOUT2 OUT20 OUT2

OUT2

OUT

CH1.SE OUT12 OUT2

LO3

N2BA

N2AC

N2AU

N1AB

IN1B

CH0.DX

BCCU0. ERU1.P CCU81. ERU1.G CCU40. ACMP0. USIC1_ CCU81. CCU41.

CCU40.I CCU41.I CCU80.I

POSIF1.

IN2B

USIC1_

CH0.D

X1B

OUT5

DOUT3 OUT21 OUT3

OUT3

OUT

CH0.SC OUT13 OUT3

LKOUT

N3BA

N3AC

N3AU

BCCU0. LEDTS2

OUT0 .LINE0

LEDTS1 CCU80. USIC1_

.COLA OUT00 CH0.DO

UT0

CCU81. CCU41.

OUT00 OUT0

CCU41.I

N0AV

USIC1_

CH0.DX

USIC1_

CH1.DX

ERU1.0

BCCU0. LEDTS2

OUT8 .LINE1

LEDTS1 CCU80. USIC1_ USIC1_ CCU81. CCU41.

.COL6 OUT01 CH0.DO CH0.SC OUT01 OUT1

CCU41.I

N1AV

USIC1_ USIC1_

CH0.DX CH0.D

ERU1.1

UT0

LKOUT

X1C

BCCU0. LEDTS2 CCU81. LEDTS1 CCU80.

OUT2 .LINE2 OUT10 .COL5 OUT10

USIC1_ CCU81. CCU41.

CH0.SC OUT02 OUT2

LKOUT

CCU41.I

N2AV

CCU81.I

N0AB

USIC1_

CH0.D

X1D

ERU1.2

BCCU0. LEDTS2 CCU81. LEDTS1 CCU80.

OUT5 .LINE3 OUT11 .COL4 OUT11

USIC1_ CCU81. CCU41.

CH0.SE OUT03 OUT3

LO0

CCU41.I

N3AV

USIC1_

CH0.D

X2A

ERU1.0

BCCU0. LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CAN.N1

CCU40.I CCU41.I

N0AV N0BA

USIC1_

CH0.D

X2B

CAN.N1

_RXDC

OUT7

.LINE4 .COL3 .COL3 OUT30 OUT0

CH0.SE OUT30 _TXD

LO1

BCCU0. LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CAN.N1

CCU40.I CCU41.I

N1AV N1BA

USIC1_

CH0.D

X2C

CAN.N1

_RXDD

OUT3

.LINE5 .COL2 .COL2 OUT31 OUT1

CH0.SE OUT31 _TXD

LO2

Table 9

Port I/O Functions (cont’d)

Function

Outputs

Inputs

Input

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

ALT8

ALT9

Input

Input Input

Input

P4.10

P4.11

LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CCU81. BCCU0. CCU40.I CCU41.I

CCU81.I

N3AB

USIC1_ USIC1_

CH0.D CH1.DX

.LINE6 .COL1 .COL1 OUT00 OUT2

CH0.SE OUT32 OUT00 TRAPIN N2AV

LO3

N2BA

X2D

LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CCU81.

CCU40.I CCU41.I

USIC1_ USIC1_ USIC1_

CH0.D CH1.DX CH1.DX

.LINE7 .COL0 .COL0 OUT01 OUT3

CH0.SE OUT33 OUT01

LO4

N3AV

N3BA

X2E

Table 10

Hardware I/O Controlled Functions

Outputs

HWO0

Outputs

HWO1

Inputs

Pull Control

HW0_PD

Pull Control

HW0_PU

Pull Control

HW1_PD

Pull Control

HW1_PU

Function

HWI0

HWI1

P0.0

P0.1

LEDTS0.

EXTENDED7

LEDTS0.TSIN7

Reserved for LEDTS Reserved for LEDTS Reserved for LEDTS Scheme B:

Scheme A:

pull-down enabled

always

pull-up enabled and pull-down disabled, and

vice versa

pull-down disabled

always

LEDTS0.

EXTENDED6

LEDTS0.TSIN6

LEDTS0.TSIN5

LEDTS0.TSIN4

LEDTS0.TSIN3

LEDTS0.TSIN2

LEDTS0.TSIN1

LEDTS0.TSIN0

LEDTS1.TSIN0

LEDTS1.TSIN1

LEDTS1.TSIN2

LEDTS1.TSIN3

LEDTS1.TSIN4

LEDTS1.TSIN5

LEDTS1.TSIN6

LEDTS1.TSIN7

LEDTS0.TSIN6

LEDTS0.TSIN5

LEDTS0.TSIN4

LEDTS0.TSIN3

LEDTS0.TSIN2

LEDTS0.TSIN1

LEDTS0.TSIN0

LEDTS1.TSIN0

LEDTS1.TSIN1

LEDTS1.TSIN2

LEDTS1.TSIN3

LEDTS1.TSIN4

LEDTS1.TSIN5

LEDTS1.TSIN6

LEDTS1.TSIN7

P0.2

LEDTS0.

EXTENDED5

P0.3

LEDTS0.

EXTENDED4

P0.4

LEDTS0.

EXTENDED3

P0.5

LEDTS0.

EXTENDED2

P0.6

LEDTS0.

EXTENDED1

P0.7

LEDTS0.

EXTENDED0

P0.8

LEDTS1.

EXTENDED0

P0.9

LEDTS1.

EXTENDED1

P0.10

P0.11

P0.12

P0.13

P0.14

P0.15

LEDTS1.

EXTENDED2

LEDTS1.

EXTENDED3

LEDTS1.

EXTENDED4

LEDTS1.

EXTENDED5

LEDTS1.

EXTENDED6

LEDTS1.

EXTENDED7

P1.0

P1.1

P1.2

USIC0_CH0.DOUT0

USIC0_CH0.DOUT1

USIC0_CH0.DOUT2

USIC0_CH0.HWIN0 BCCU0.OUT2

USIC0_CH0.HWIN1 BCCU0.OUT3

USIC0_CH0.HWIN2 BCCU0.OUT4

BCCU0.OUT2

BCCU0.OUT3

BCCU0.OUT4

Table 10

Hardware I/O Controlled Functions

Outputs

HWO0

Outputs

Inputs

HWI0

Inputs

HWI1

Pull Control

HW0_PD

Pull Control

HW1_PD

Pull Control

HW1_PU

Function

HWO1

HW0_PU

BCCU0.OUT5

BCCU0.OUT6

BCCU0.OUT7

BCCU0.OUT8

P1.3

P1.4

P1.5

P1.6

P1.7

P1.8

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P3.0

P3.1

P3.2

P3.3

P3.4

P4.0

P4.1

P4.2

P4.3

USIC0_CH0.DOUT3

USIC0_CH0.HWIN3 BCCU0.OUT5

BCCU0.OUT6

BCCU0.OUT7

BCCU0.OUT8

BCCU0.OUT1

BCCU0.OUT6

BCCU0.OUT0

ACMP2.OUT

BCCU0.OUT8

ACMP1.OUT

BCCU0.OUT2

BCCU0.OUT8

BCCU0.OUT1

BCCU0.OUT7

BCCU0.OUT4

BCCU0.OUT5

BCCU0.OUT3

BCCU0.OUT4

BCCU0.OUT1

BCCU0.OUT6

BCCU0.OUT0

ACMP2.OUT

BCCU0.OUT8

ACMP1.OUT

BCCU0.OUT2

BCCU0.OUT8

BCCU0.OUT1

BCCU0.OUT7

BCCU0.OUT4

BCCU0.OUT5

BCCU0.OUT3

BCCU0.OUT4

CCU40.OUT3

CCU40.OUT2

CCU40.OUT3

CCU40.OUT2

CCU41.OUT0

CCU41.OUT2

CCU41.OUT0

CCU41.OUT2

USIC1_CH0.DOUT3

USIC1_CH0.DOUT2

USIC1_CH0.DOUT1

USIC1_CH0.DOUT0

USIC1_CH0.HWIN3

USIC1_CH0.HWIN2

USIC1_CH0.HWIN1

USIC1_CH0.HWIN0

Table 10

Hardware I/O Controlled Functions

Outputs

HWO0

Outputs

HWO1

Inputs

Pull Control

HW0_PD

Pull Control

HW0_PU

Pull Control

HW1_PD

Pull Control

HW1_PU

Function

HWI0

HWI1

P4.4

P4.5

P4.6

P4.7

P4.8

P4.9

P4.10

P4.11

LEDTS2.

EXTENDED0

LEDTS2.TSIN0

Reserved for LEDTS Reserved for LEDTS Reserved for LEDTS Scheme B:

Scheme A:

pull-down enabled

always

pull-up enabled and pull-down disabled, and

vice versa

pull-down disabled

always

LEDTS2.

EXTENDED1

LEDTS2.TSIN1

LEDTS2.TSIN2

LEDTS2.TSIN3

LEDTS2.TSIN4

LEDTS2.TSIN5

LEDTS2.TSIN6

LEDTS2.TSIN7

LEDTS2.TSIN1

LEDTS2.TSIN2

LEDTS2.TSIN3

LEDTS2.TSIN4

LEDTS2.TSIN5

LEDTS2.TSIN6

LEDTS2.TSIN7

LEDTS2.

EXTENDED2

LEDTS2.

EXTENDED3

LEDTS2.

EXTENDED4

LEDTS2.

EXTENDED5

LEDTS2.

EXTENDED6

LEDTS2.

EXTENDED7

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

This section provides the electrical parameter which are implementation-specific for the

XMC1400.

3.1

General Parameters

3.1.1

Parameter Interpretation

The parameters listed in this section represent partly the characteristics of the XMC1400

and partly its requirements on the system. To aid interpreting the parameters easily

when evaluating them for a design, they are indicated by the abbreviations in the

“Symbol” column:

•

Such parameters indicate Controller Characteristics, which are distinctive feature of

the XMC1400 and must be regarded for a system design.

•

Such parameters indicate System Requirements, which must be provided by the

application system in which the XMC1400 is designed in.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.1.2

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Table 11

Absolute Maximum Rating Parameters

Symbol Values

Parameter

Unit Note /

Test Cond

Min Typ. Max.

ition

Junction temperature

Storage temperature

T_J

SR -40

–

115

125

°C

–

T_ST

Voltage on power supply pin V_DDPSR -0.3

with respect to V_SSP

Voltage on digital pins with

respect to V_SSP

V_IN

SR -0.5

–

_DDP+ 0.5

whichever

is lower

or max. 6

Voltage on P2 pins with

V_INP2SR -0.3

V_DDP+ 0.3

–

respect to V_SSP

Voltage on analog input pins V_AIN

with respect to V_SSP

-0.5

V_DDP+ 0.5

whichever

is lower

V_AREFSR

or max. 6

Input current on any pin

during overload condition

I_IN

SR -10

–

Absolute maximum sum of all ΣI_INSR -50

inputcurrentsduring overload

condition

+50

–

1) Excluding port pins P2.[1,2,6,7,8,9,11].

2) Applicable to port pins P2.[1,2,6,7,8,9,11].

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.1.3

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience

overload currents and voltages that go beyond their own IO power supplies specification.

Table 12 defines overload conditions that will not cause any negative reliability impact if

all the following conditions are met:

•

full operation life-time is not exceeded

Operating Conditions are met for

– pad supply levels (V_DDP

)

– temperature

If a pin current is outside of the Operating Conditions but within the overload

conditions, then the parameters of this pin as stated in the Operating Conditions can no

longer be guaranteed. Operation is still possible in most cases but with relaxed

parameters.

Note: An overload condition on one or more pins does not require a reset.

Note: A series resistor at the pin to limit the current to the maximum permitted overload

current is sufficient to handle failure situations like short to battery.

Table 12

Overload Parameters

Symbol

Parameter

Values

Unit Note /

Test Condition

Min. Typ. Max.

Input current on any port pin I_OVSR -5

during overload condition

–

Absolute sum of all input

circuit currents during

overload condition

I_OVSSR

–

Figure 11 shows the path of the input currents during overload via the ESD protection

structures. The diodes against V_DDPand ground are a simplified representation of these

ESD protection structures.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

V_DDP

Pn.y

I_OVx

GND

ESD

GND

Pad

Figure 11

Input Overload Current via ESD structures

Table 13 and Table 14 list input voltages that can be reached under overload conditions.

Note that the absolute maximum input voltages as defined in the Absolute Maximum

Ratings must not be exceeded during overload.

Table 13

PN-Junction Characterisitics for positive Overload

_OV= 5 mA

Pad Type

Standard, High-current,

AN/DIG_IN

_IN= V_DDP+ 0.5 V

_AIN= V_DDP+ 0.5 V

_AREF= V_DDP+ 0.5 V

P2.[1,2,6:9,11]

_INP2= V_DDP+ 0.3 V

Table 14

PN-Junction Characterisitics for negative Overload

_OV= 5 mA

Pad Type

Standard, High-current,

AN/DIG_IN

_IN= V_SS- 0.5 V

_AIN= V_SS- 0.5 V

_AREF= V_SS- 0.5 V

P2.[1,2,6:9,11]

_INP2= V_SS- 0.3 V

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.1.4

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation and reliability of the XMC1400. All parameters specified in the following tables

refer to these operating conditions, unless noted otherwise.

Table 15

Operating Conditions Parameters

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

SR -40

-40

Digital supply voltage¹⁾V_DDPSR 1.8

Typ.

Max.

Ambient Temperature T_A

−

°C

Temp. Range F

Temp. Range X

105

5.5

Short circuit current of I_SC

SR -5

digital outputs

Absolute sum of short ΣI_{SC_D}SR

circuit currents of the

device

−

1) See also the Supply Monitoring thresholds, Chapter 3.3.2.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2

DC Parameters

3.2.1

Input/Output Characteristics

Table 16 provides the characteristics of the input/output pins of the XMC1400.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Note: Unless otherwise stated, input DC and AC characteristics, including peripheral

timings, assume that the input pads operate with the standard hysteresis.

Table 16

Input/Output Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

Output low voltage on

port pins

(with standard pads)

V_OLPCC

–

1.0

_OL= 11 mA (5 V)

_OL= 7 mA (3.3 V)

–

0.4

1.0

_OL= 5 mA (5 V)

_OL= 3.5 mA (3.3 V)

Output low voltage on

high current pads

V_OLP1CC

_OL= 50 mA (5 V)

_OL= 25 mA (3.3 V)

–

0.32

0.4

–

_OL= 10 mA (5 V)

_OL= 5 mA (3.3 V)

Output high voltage on V_OHPCC V_DDP

_OH= -10 mA (5 V)

_OH= -7 mA (3.3 V)

port pins

(with standard pads)

1.0

V_DDP

0.4

–

_OH= -4.5 mA (5 V)

_OH= -2.5 mA (3.3 V)

Output high voltage on V_OHP1CC V_DDP

_OH= -6 mA (5 V)

_OH= -8 mA (3.3 V)

_OH= -4 mA (3.3 V)

high current pads

0.32

V_DDP

1.0

V_DDP

0.4

Input low voltage on port V_ILPSSR

pins

–

0.19 × V

V_DDP

CMOS Mode

(5 V, 3.3 V & 2.2 V)

(Standard Hysteresis)

Input high voltage on

port pins

V_IHPSSR 0.7 ×

–

CMOS Mode

(5 V, 3.3 V & 2.2 V)

V_DDP

(Standard Hysteresis)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 16

Input/Output Characteristics (Operating Conditions apply) (cont’d)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

Input low voltage on port V_ILPLSR

–

0.08 × V

CMOS Mode

pins

V_DDP

(5 V, 3.3 V & 2.2 V)

(Large Hysteresis)

Input high voltage on

port pins

V_IHPLSR 0.85 ×

–

CMOS Mode

(5 V, 3.3 V & 2.2 V)

V_DDP

(Large Hysteresis)

Rise/fall time on High

Current Pad¹⁾

t_HCPR

t_HCPF

–

50 pF @ 5 V²⁾

50 pF @ 3.3 V³⁾

50 pF @ 1.8 V⁴⁾

Rise/fall time on

Standard Pad¹⁾

t_R, t_FCC

–

50 pF @ 5 V⁵⁾

50 pF @ 3.3 V⁶⁾.

50 pF @ 1.8 V⁷⁾.

Input Hysteresis on port HYS CC 0.08 ×

–

CMOS Mode (5 V),

Standard Hysteresis

pin except P2.3 - P2.9⁸⁾

V_DDP

0.03 ×

V_DDP

CMOS Mode (3.3 V),

Standard Hysteresis

0.02 ×

V_DDP

CMOS Mode (2.2 V),

Standard Hysteresis

0.5 ×

V_DDPV_DDP

0.75 × V

CMOS Mode(5 V),

Large Hysteresis

0.4 ×

V_DDPV_DDP

0.75 × V

CMOS Mode(3.3 V),

Large Hysteresis

0.2 ×

V_DDPV_DDP

0.65 × V

CMOS Mode(2.2 V),

Large Hysteresis

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 16

Input/Output Characteristics (Operating Conditions apply) (cont’d)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

Input Hysteresis on port HYS_ CC 0.08 ×

–

CMOS Mode (5 V),

Standard Hysteresis

pin P2.3 - P2.9⁸⁾

V_DDP

0.03 ×

V_DDP

–

CMOS Mode (3.3 V),

Standard Hysteresis

0.02 ×

V_DDP

CMOS Mode (2.2 V),

Standard Hysteresis

0.35 × 0.75 × V

V_DDPV_DDP

CMOS Mode(5 V),

Large Hysteresis

0.25 × 0.75 × V

V_DDPV_DDP

CMOS Mode(3.3 V),

Large Hysteresis

0.15 × 0.65 × V

V_DDPV_DDP

CMOS Mode(2.2 V),

Large Hysteresis

Pin capacitance (digital C_IO

inputs/outputs)

–

Pull-up current on port I_PUP

pins

–

-80

–

μA

_IH,min(5 V)

-95

–

_IL,max(5 V)

_IH,min(3.3 V)

_IL,max(3.3 V)

_IL,max(5 V)

_IH,min(5 V)

-50

–

-65

–

Pull-down current on

port pins

I_PDP

–

_IL,max(3.3 V)

_IH,min(3.3 V)

Input leakage current

except P0.11⁹⁾

I_OZP

CC -1

0 < V_IN< V_DDP

T_A≤ 105 °C

Input leakage current for I_OZP1CC -10

μA

0 < V_IN< V_DDP

T_A≤ 105 °C

10)

P0.11⁹⁾

Voltage on any pin

V_PO

I_MP

–

0.3

during V_DDPpower off

Maximum current per

pin (excluding P1, V_DDP

and V_SS)

SR -10

–

Maximum current per

high currrent pins

I_MP1ASR -10

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 16

Input/Output Characteristics (Operating Conditions apply) (cont’d)

Parameter

Symbol

Limit Values Unit Test Conditions

Min.

Max.

Maximum current into

I_MVDD1SR

–

520

_DDP(VQFN64,

LQFP64)

Maximum current into

I_MVDD2SR

I_MVDD3SR

–

390

260

390

260

_DDP(VQFN48)

Maximum current into

_DDP(VQFN40)

Maximum current out of I_MVSS1SR

_SS(VQFN64, LQFP64)

Maximum current out of I_MVSS2SR

_SS(VQFN48)

Maximum current out of I_MVSS3SR

_SS(VQFN40)

1) Rise/Fall time parameters are taken with 10% - 90% of supply.

2) Additional rise/fall time valid for C_L= 50 pF - C_L= 100 pF @ 0.150 ns/pF at 5 V supply voltage.

3) Additional rise/fall time valid for C_L= 50 pF - C_L= 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.

4) Additional rise/fall time valid for C_L= 50 pF - C_L= 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.

5) Additional rise/fall time valid for C_L= 50 pF - C_L= 100 pF @ 0.225 ns/pF at 5 V supply voltage.

6) Additional rise/fall time valid for C_L= 50 pF - C_L= 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.

7) Additional rise/fall time valid for C_L= 50 pF - C_L= 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.

8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot

be guaranteed that it suppresses switching due to external system noise.

9) An additional error current (I_INJ) will flow if an overload current flows through an adjacent pin.

10) However, for applications with strict low power-down current requirements, it is mandatory that no active

voltage source is supplied at any GPIO pin when V_DDPis powered off.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2.2

Analog to Digital Converters (ADC)

Table 17 shows the Analog to Digital Converter (ADC) characteristics.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 17

ADC Characteristics (Operating Conditions apply)¹⁾

Parameter

Symbol

Values

Unit Note / Test Condition

Min. Typ. Max.

Supply voltage range V_{DD_int}

(internal reference) SR

2.0

–

3.0

SHSCFG.AREF = 11_B;

CALCTR.CALGNSTC =

0C_Hfor f_SH= 32 MHz,

12_Hfor f_SH= 48 MHz

3.0

–

5.5

SHSCFG.AREF = 10_B

SHSCFG.AREF = 00_B

Supply voltage range V_{DD_ext}3.0

(external reference) SR

Analog input voltage

range

_AINSR V_SSP

–

V_DDP

+ 0.05

- 0.05

Auxiliary analog

V_REFGNDV_SSP

1.0

0.2

G0CH0

G1CH0

reference ground²⁾

- 0.05

V_SSP

- 0.05

Internal reference

voltage (full scale

value)

V_REFINT

Switched

capacitance of an

analog input

C_AINS

–

1.2

4.5

–

pF GNCTRxz.GAINy = 00_B

(unity gain)

pF GNCTRxz.GAINy = 01_B

(gain g1)

pF GNCTRxz.GAINy = 10_B

(gain g2)

pF GNCTRxz.GAINy = 11_B

(gain g3)

Total capacitance of C_AINT

an analog input CC

Total capacitance of C_AREFT

–

the reference input

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 17

ADC Characteristics (Operating Conditions apply)¹⁾(cont’d)

Parameter

Symbol

Values

Unit Note / Test Condition

Min. Typ. Max.

Gain settings

G_INCC

–

GNCTRxz.GAINy = 00_B

(unity gain)

GNCTRxz.GAINy = 01_B

(gain g1)

GNCTRxz.GAINy = 10_B

(gain g2)

GNCTRxz.GAINy = 11_B

(gain g3)

Sample Time

t_sample

–

1 /

f_ADCf

_DD= 5.0 V,

_ADCI= 48 MHz

_DD= 5.0 V,

_ADCI= 32 MHz

_DD= 3.3 V,

_ADCI= 32 MHz

_DD= 2.0 V,

_ADCI= 32 MHz

1 /

f_ADC

1 /

f_ADC

1 /

f_ADC

Conversion time

in fast compare

mode

_CFCC

1 /

f_ADC

Conversion time

in 12-bit mode

_C12CC

1 /

f_ADC

Maximum sample

–

f_ADC

42.5

–

1 sample

pending

rate in 12-bit mode⁴⁾

f_ADC

62.5

2 samples

pending

Conversion time

in 10-bit mode

_C10CC

1 /

f_ADC

Maximum sample

–

f_ADC

40.5

–

1 sample

pending

rate in 10-bit mode⁴⁾

f_ADC

58.5

2 samples

pending

Conversion time

in 8-bit mode

_C8CC

1 /

f_ADC

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 17

ADC Characteristics (Operating Conditions apply)¹⁾(cont’d)

Parameter

Symbol

Values

Unit Note / Test Condition

Min. Typ. Max.

Maximum sample

rate in 8-bit mode⁴⁾

_C8CC

–

f_ADC

38.5

–

1 sample

pending

–

f_ADC

54.5

2 samples

pending

RMS noise⁵⁾

EN_RMS

1.5

–

LSB DC input,

SHSCFG.AREF = 00_B,

GNCTRxz.GAINy = 00_B

(unity gain),

V_DD= 5.0 V,

V_AIN= 2.5 V,

25°C

DNL error

INL error

EA_DNL

–

±2.0 –

±4.0 –

±0.5 –

±3.6 –

LSB

EA_INL

LSB

Gain error with

external reference

EA_GAIN

SHSCFG.AREF = 00_B

(calibrated)

Gain error with

EA_GAIN

SHSCFG.AREF = 1X_B

(calibrated),

-40°C - 110°C

internal reference⁶⁾

–

±2.0 –

±8.0 –

SHSCFG.AREF = 1X_B

(calibrated),

0°C - 85°C

Offset error

EA_OFF

mV Calibrated,

_DD= 5.0 V

1) The parameters are defined for ADC clock frequencies f_SH= 32 MHz for the full supply range, and f_SH= 48

MHz at V_{DD_int}, V_{DD_ext}= 5 V. Usage of any other frequencies may affect the ADC performance.

2) The alternate reference ground connection is separate for each converter. This mode, therefore, provides the

lowest noise impact.

3) No pending samples assumed, excluding sampling time and calibration.

4) Includes synchronization and calibration (average of gain and offset calibration).

5) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(A_MAXeff/ N_RMS).

With A_MAXeff= 2^N/ 2, SNR[dB] = 20 × log ( 2048 / N_RMS) [N = 12].

N_RMS= 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.

6) Includes error from the reference voltage.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

CH7

V_AIN

SAR

Converter

CH0

V_REF

V_REFGND

V_REFINT

V_AREF

VSS

VDD

Internal

Reference

V_DDint

V_DDext

CHNR

REFSEL

AREF

MC_VADC_AREFPATHS

Figure 12

ADC Voltage Supply

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2.3

Out of Range Comparator (ORC) Characteristics

The Out-of-Range Comparator (ORC) triggers on analog input voltages (V_AIN) above

V_DDPon selected input pins (ORCx.AIN) and generates a service request trigger

(ORCx.OUT).

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 18

Out of Range Comparator (ORC) Characteristics (Operating

Conditions apply; V_DDP= 3.0 V - 5.5 V; C_L= 0.25pF)

Parameter

Symbol

Values

Unit Note / Test Condition

Min. Typ. Max.

DC Switching Level V_ODCCC

−

180 mV V_AIN≥ V_DDP+ V_ODC

Hysteresis

V_OHYSCC 15

t_OPDDCC 103

−

Always detected

Overvoltage Pulse

ns V_AIN≥ V_DDP+ 150 mV

ns V_AIN≥ V_DDP+ 350 mV

ns V_AIN≥ V_DDP+ 150 mV

ns V_AIN≥ V_DDP+ 350 mV

−

Never detected

t_OPDNCC

−

Overvoltage Pulse

Detection Delay

Release Delay

Enable Delay

t_ODDCC 39

132 ns V_AIN≥ V_DDP+ 150 mV

121 ns V_AIN≥ V_DDP+ 350 mV

240 ns V_AIN≤ V_DDP; V_DDP= 5 V

340 ns V_AIN≤ V_DDP; V_DDP= 3.3 V

t_ORDCC 44

t_OEDCC

−

300 ns

ORCCTRL.ENORCx = 1

V_DDP

ORCx.AIN

V_SS

ORCx.OUT

t_ODD

t_ORD

Figure 13

ORCx.OUT Trigger Generation

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

V_AIN(V)

T > t_OPDD

t_OPDN< T < t_OPDD

T < t_OPDN

V_DDP+ 350 mV

V_DDP+ 150 mV

t_OPDN< T < t_OPDD

T > t_OPDD

T < t_OPDN

T > t_OPDD

V_DDP+ 60 mV

V_DDP

Never

detected

Overvoltage

Pulse

Never

detected

Overvoltage

Pulse

Overvoltage

may be

detected

Never

detected

Overvoltage

Pulse

Overvoltage

may be

detected

Always detected

Overvoltage Pulse

Always detected

Overvoltage Pulse

Overvoltage

may be

detected

(long enough,

level uncertain

(Too low)

(Too short)

)

V_SSA

Figure 14

ORC Detection Ranges

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2.4

Analog Comparator Characteristics

Table 19 below shows the Analog Comparator characteristics.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 19

Analog Comparator Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Notes/

Test Conditions

Min. Typ. Max.

Input Voltage

Input Offset

V_CMP

SR -0.05

–

V_DDP

0.05

V_CMPOFFCC

t_PDELAYCC

–

+/-3

–

mV High power mode

Δ V_CMP< 200 mV

Propagation

Delay¹⁾

High power mode,

Δ V_CMP= 100 mV

High power mode,

Δ V_CMP= 25 mV

250

700

100

Low power mode,

Δ V_CMP= 100 mV

Low power mode,

Δ V_CMP= 25 mV

Current

Consumption

I_ACMP

μA First active ACMP in

high power mode,

ΔV_CMP> 30 mV

–

μA Each additional ACMP

in high power mode,

ΔV_CMP> 30 mV

–

μA First active ACMP in

low power mode

μA Each additional ACMP

in low power mode

Input Hysteresis V_HYS

–

+/-15

–

Filter Delay¹⁾

t_FDELAYCC

1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2.5

Temperature Sensor Characteristics

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 20

Temperature Sensor Characteristics

Parameter

Symbol

Values

Min. Typ. Max.

Unit Note /

Test Condition

Measurement time

t_MCC

−

115

°C

Temperature sensor range

Sensor Accuracy¹⁾

_SRSR -40

−

T_TSAL

-6

-10

−

–

T_J> 20°C

–

0°C ≤ T_J≤ 20°C

T_J< 0°C

-/+8

Start-up time

_TSSTSR −

−

μs

1) The temperature sensor accuracy is independent of the supply voltage.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2.6

Oscillator Pins

Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters

for the oscillator operation. Please refer to the limits specified by the crystal or

ceramic resonator supplier.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

The oscillator pins can be operated with an external crystal/resonator (see Figure 15) or

in direct input mode (see Figure 16).

XTAL1

f_OSC

GND

XTAL2

Damping resistor

may be needed for

some crystals

V_{PPX_min}

V_PPX

V_{PPX_min}≤ V_PPX≤ V_{PPX_max}

t_OSCS

Figure 15

Oscillator in Crystal Mode

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

External Clock

Source

Direct Input Mode

XTAL1

XTAL2

not connected

V_{IHBX_max}

V_{IHBX_min}

V_{ILBX_max}

V_SS

V_{ILBX_min}

Figure 16

Oscillator in Direct Input Mode

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 21

OSC_XTAL Parameters

Parameter

Symbol

Min.

Values

Unit Note /

Test Condition

Typ.

Max.

Input frequency

_OSCSR

−

MHz Direct Input Mode

MHz External Crystal

Mode

Oscillator start-up

time¹⁾²⁾

t_OSCS

−

Input voltage at XTAL1 V_IXSR -0.3

1.5

External Crystal

Mode

-0.3

−

5.5

1.7

Direct Input Mode

Input amplitude (peak-

to-peak) at XTAL1²⁾³⁾

_PPXSR 0.6

External Crystal

Mode

1) t_OSCSis defined from the moment the oscillator is enabled wih SCU_ANAOSCHPCTRL.MODE until the

oscillations reach an amplitude at XTAL1 of 0.9 * V_PPX

2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and

amplitude as recommended and specified by crystal suppliers.

3) If the shaper unit is enabled and not bypassed.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 22

RTC_XTAL Parameters

Symbol

Parameter

Values

Typ.

Unit Note /

Test Condition

Min.

f_OSCSR −

Max.

Input frequency

32.768 −

kHz

Oscillator start-up

time¹⁾²⁾

t_OSCS

−

Input voltage at

RTC_XTAL1

V_IXSR -0.3

V_PPXSR 0.2

1.5

1.2

Input amplitude (peak-

to-peak) at

RTC_XTAL1²⁾³⁾

1) t_OSCSis defined from the moment the oscillator is enabled by the user with SCU_ANAOSCLPCTRL.MODE

until the oscillations reach an amplitude at RTC_XTAL1 of 0.9 * V_PPX

2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and

amplitude as recommended and specified by crystal suppliers.

3) If the shaper unit is enabled and not bypassed.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2.7

Power Supply Current

The total power supply current defined below consists of a leakage and a switching

component.

Application relevant values are typically lower than those given in the following tables,

and depend on the customer's system operating conditions (e.g. thermal connection or

used application configurations).

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 23

Power Supply parameter table; V_DDP= 5V

Symbol Values

Min. Typ.¹⁾

Parameter

Unit Note /

Test Condition

Max.

Active mode current

Peripherals enabled

f_MCLK/ f_PCLKin MHz²⁾

_DDPAECC −

14.1

9.8

7.8

6.4

4.4

6.2

4.6

3.6

3.1

1.8

9.6

−

mA 48 / 96

mA 24 / 48

mA 16 / 32

mA 8 / 16

mA 1 / 1

−

Active mode current

Peripherals disabled

f_MCLK/ f_PCLKin MHz³⁾

I_DDPAD

−

mA 48 / 96

mA 24 / 48

mA 16 / 32

mA 8 / 16

mA 1 / 1

−

Active mode current

Code execution from

RAM

I_DDPAR

mA 48 / 96

Flash is powered down

f_MCLK/ f_PCLKin MHz

Sleep mode current

_DDPSECC −

11.0

7.6

6.4

5.3

4.2

−

mA 48 / 96

mA 24 / 48

mA 16 / 32

mA 8 / 16

mA 1 / 1

Peripherals clock enabled

−

f_MCLK/ f_PCLKin MHz⁴⁾

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 23

Power Supply parameter table; V_DDP= 5V

Parameter

Symbol

Values

Min. Typ.¹⁾

Unit Note /

Test Condition

Max.

Sleep mode current

Peripherals clock

disabled

I_DDPSD

−

2.8

−

mA 48 / 96

mA 24 / 48

mA 16 / 32

mA 8 / 16

mA 1 / 1

mA 48 / 96

mA 24 / 48

mA 16 / 32

mA 8 / 16

mA 1 / 1

2.2

2.0

1.9

1.7

2.2

1.7

1.4

1.2

1.1

0.27

Flash active

f_MCLK/ f_PCLKin MHz⁵⁾

Sleep mode current

Peripherals clock

disabled

I_DDPSR

Flash powered down

f_MCLK/ f_PCLKin MHz⁶⁾

Deep Sleep mode

current⁷⁾

I_DDPDS

Wake-up time from Sleep

to Active mode⁸⁾

_SSACC

_DSACC

−

cycl

Wake-up time from Deep

Sleep to Active mode⁹⁾

290

μsec

1) The typical values are measured at T_A= + 25 °C and V_DDP= 5 V.

2) CPU and all peripherals clock enabled, Flash is in active mode.

3) CPU enabled, all peripherals clock disabled, Flash is in active mode.

4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.

5) CPU in sleep, Flash is in active mode.

6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.

7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.

8) CPU in sleep, Flash is in active mode during sleep mode.

9) CPU in sleep, Flash is in powered down mode during deep sleep mode.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Figure 17 shows typical graphs for active mode supply current for V_DDP= 5 V, V_DDP

3.3 V, V_DDP= 1.8 V across different clock frequencies.

16.0

14.0

12.0

10.0

IDDPAE 5V / 3.3V

IDDPAE 1.8V

8.0

6.0

4.0

2.0

0.0

I (mA)

IDDPAD 5V / 3.3V /1.8V

1/1

8/16 16/32 24/48 48/96

MCLK / PCLK (MHz)

Condition:

1. TA = +25° C

Figure 17

Active mode, a) peripherals clocks enabled, b) peripherals clocks

disabled: Supply current I_DDPAover supply voltage V_DDPfor different

clock frequencies

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Figure 18 shows typical graphs for sleep mode current for V_DDP= 5 V, V_DDP= 3.3 V,

V_DDP= 1.8 V across different clock frequencies.

2.5

2.0

1.5

I (mA)

1.0

IDDPSR 5V / 3.3V / 1.8V

0.5

0.0

1/1

8/16

16/32 24/48 32/64

MCLK / PCLK (MHz)

Condition:

1. TA = +25° C

Figure 18

Sleep mode, peripherals clocks disabled, Flash powered down:

Supply current I_DDPSDover supply voltage V_DDPfor different clock

frequencies

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 24 provides the active current consumption of some modules operating at 5 V

power supply at 25° C. The typical values shown are used as a reference guide on the

current consumption when these modules are enabled.

Table 24

Typical Active Current parameter table

Active Current

Consumption

Symbol

Limit

Values

Unit

Test Condition

Typ.

Baseload current I_CPUDDC

4.14

Modules including Core, SCU,

PORT, memories, ANATOP¹⁾

VADC and SHS

USICx

I_ADCDDC

3.73

Set CGATCLR0.VADC to 1²⁾

Set CGATCLR0.USIC0 to 1³⁾

Set CGATCLR0.CCU40 to 1⁴⁾

Set CGATCLR0.CCU80 to 1⁵⁾

Set CGATCLR0.POSIF0 to 1⁶⁾

Set CGATCLR0.LEDTSx to 1⁷⁾

Set CGATCLR0.BCCU0 to 1⁸⁾

Set CGATCLR0.MATH to 1⁹⁾

Set CGATCLR0.WDT to 1¹⁰⁾

Set CGATCLR0.RTC to 1¹¹⁾

Set CGATCLR0.MCAN0 to 1¹²⁾

I_USIC0DDC1.35

I_CCU40DDC0.99

I_CCU80DDC1.00

CCU4x

CCU8x

POSIFx

LEDTSx

BCCU0

MATH

I_PIF0DDC

I_LTSxDDC

1.05

1.14

I_BCCU0DDC0.29

I_MATHDDC0.50

WDT

I_WDTDDC

I_RTCDDC

0.03

0.01

RTC

MultiCAN

I_MCANDDC1.38

1) Baseload current is measured with device running in user mode, MCLK=PCLK=48 MHz, with an endless loop

in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.

2) Active current is measured with: module enabled, MCLK=48 MHz, running in auto-scan conversion mode

3) Active current is measured with: module enabled, each of the 2 USIC channels sending alternate messages

at 57.6 kbaud every 200 ms

4) Active current is measured with: module enabled, MCLK=PCLK=48 MHz, 1 CCU4 slice for PWM switching at

20kHz with duty cycle varying at 10%-90%, 1 CCU4 slice in capture mode for reading period and duty cycle

5) Active current is measured with: module enabled, MCLK=PCLK=48 MHz, 3 CCU8 slices with PWM frequency

at 20kHz and a period match interrupt used to toggle duty cycle between 10% and 90%

6) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96 MHz, hall sensor mode

7) Active current is measured with: module enabled, MCLK=48 MHz, 1 LED column, 6 LED/TS lines, Pad

Scheme A with large pad hysteresis config, time slice duration = 1.048 ms

8) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96MHz, FCLK=0.8 MHz, Normal

mode (BCCU clock = FCLK/4), 4 BCCU Channels with packers enabled and 1 Dimming Engine, change color

or dim every 1s

9) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96 MHz, tangent calculation in while

loop; CORDIC circular rotation, no keep, autostart; 32-by-32 bit signed DIV, autostart, DVS right shift by 11

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

10) Active current is measured with: module enabled, MCLK=48 MHz, time-out mode; WLB = 0, WUB =

0x00008000; WDT serviced every 1 s

11) Active current is measured with: module enabled, MCLK=48 MHz, Periodic interrupt enabled

12) Active current is measured with: module enabled, MCLK=48 MHz, running at 20 MHz baudrate generator, 1

node activated, 1 transmit and 1 receive object active.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.2.8

Flash Memory Parameters

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 25

Flash Memory Parameters

Symbol

Parameter

Values

Unit

Note /

Test Condition

Min. Typ. Max.

Erase time per

page / sector

_ERASECC

_PSERCC

_WUCC

6.8 7.1 7.6

Program time per

block

102 152 204

μs

Wake-Up time

−

32.2

−

μs

Read time per word

Data Retention Time

t_aCC

_RETCC

−

years Max. 100 erase /

program cycles

Flash Wait States ¹⁾

_WSFLASHCC 0

−

f_MCLK= 8 MHz

f_MCLK= 16 MHz

f_MCLK= 32 MHz

f_MCLK= 48 MHz

−

Erase Cycles

N_ECYCCC

5*10⁴cycles Sum of page and

sector erase cycles

Total Erase Cycles

N_TECYCCC

−

2*10⁶cycles

1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical

values are calculated from the execution of the Dhrystone benchmark program.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

sector N_LOG_SEC-1

page 15

page 14

page 13

sector 1

sector 0

page 1

page 0

1 page = 16 data blocks = 256 Bytes

data block 0

word 0

data block 1

data block 2

data block 14

data block 15

1 block= 4 words = 16 Bytes

word 1 word 2 word 3

¹⁾The number of sectors, N_LOG_SEC, depends on the Flash memory size of the product derivative.

Figure 19

Logical Structure of the Flash

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.3

AC Parameters

3.3.1

Testing Waveforms

V_DDP

90%

10%

V_SS

t_R

t_F

Figure 20

Rise/Fall Time Parameters

V_DDP

V_DDP/ 2

Test Points

V_SS

Figure 21

Testing Waveform, Output Delay

V_LOAD+ 0.1V

V_OH- 0.1V

Timing

Reference

Points

V_LOAD- 0.1V

V_OL+ 0.1V

Figure 22

Testing Waveform, Output High Impedance

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.3.2

Power-Up and Supply Threshold Characteristics

Table 26 provides the characteristics of the supply threshold in XMC1400.

The guard band between the lowest valid operating voltage and the brownout reset

threshold provides a margin for noise immunity and hysteresis. The electrical

parameters may be violated while V_DDPis outside its operating range.

The brownout detection triggers a reset within the defined range. The prewarning

detection can be used to trigger an early warning and issue corrective and/or fail-safe

actions in case of a critical supply voltage drop.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 26

Power-Up and Supply Threshold Parameters (Operating Conditions

apply)

Parameter

Symbol

Values

Typ. Max.

Unit Note /

Test Condition

Min.

_RAMPUPSR V_DDP

_DDPramp-up time

_DDPslew rate

−

10⁷

0.1

μs

S_VDDPrise

_VDDPOPSR

V/μs Slope during

normal operation

S_VDDP10SR

V/μs Slope during fast

transient within +/-

10% of V_DDP

_VDDPriseSR

−

V/μs Slope during

power-on or

restart after

brownout event

S_VDDPfall¹⁾SR 0

0.25 V/μs Slope during

supply falling out

of the +/-10%

limits²⁾

_DDPprewarning

_DDPPWCC 2.1

2.85

4.2

2.25 2.4

ANAVDEL.VDEL_

SELECT = 00_B

voltage

3.15

4.6

ANAVDEL.VDEL_

SELECT = 01_B

4.4

ANAVDEL.VDEL_

SELECT = 10_B

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 26

Power-Up and Supply Threshold Parameters (Operating Conditions

apply) (cont’d)

Parameter

Symbol

Values

Typ. Max.

1.62 1.75

Unit Note /

Test Condition

Min.

_DDPBOCC 1.55

_DDPbrownout reset

calibrated, before

user code starts

running

voltage

_DDPvoltage to

_DDPPACC

−

1.0

−

–

ensure defined pad

states

Start-up time from

power-on reset

_SSWSR

260

8.25

μs

Time to the first

user code

instruction³⁾

BMI program time

_BMISR

Time taken from a

user-triggered

system reset after

BMI installation is

is requested

1) A capacitor of at least 100 nF has to be added between V_DDPand V_SSPto fulfill the requirement as stated for

this parameter.

2) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to

the chip. A larger capacitor value has to be chosen if the power source sink a current.

3) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 48 MHz

and the clocks to peripheral as specified in register CGATSTAT0 are gated.

5.0V

V_DDPPW

}

VDDP

V_DDPBO

Figure 23

Supply Threshold Parameters

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.3.3

On-Chip Oscillator Characteristics

Table 27 provides the characteristics of the 96 MHz digital controlled oscillator DCO1.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 27

96 MHz DCO1 Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Conditions

Min. Typ Max.

Nominal frequency f_NOMCC

–

MHz under nominal

conditions¹⁾after trimming

Accuracy with

adjustmentbasedon

XTAL as reference

Δf_LTXCC -0.3

Δf_LTCC -1.7

-3.9

–

0.3

with respect to f_NOM(typ),

over temperature

(-40 °C to 105 °C)

Accuracy

–

3.4

4.0

with respect to f_NOM(typ),

over temperature

(0 °C to 85 °C)

with respect to f_NOM(typ),

over temperature

(-40 °C to 105 °C)

1) The deviation is relative to the factory trimmed frequency at nominal V_DDCand T_A= + 25 °C.

Table 28 provides the characteristics of the 32 kHz digital controlled oscillator DCO2.

Table 28

32 kHz DCO2 Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Conditions

Min. Typ. Max.

Nominal frequency

Accuracy

f_NOMCC –

32.75 –

kHz under nominal

conditions¹⁾after trimming

Δf_LTCC -1.7

–

3.4

with respect to f_NOM(typ),

over temperature

(0 °C to 85 °C)

-3.9

4.0

with respect to f_NOM(typ),

over temperature

(-40 °C to 105 °C)¹⁾

1) The deviation is relative to the factory trimmed frequency at nominal V_DDCand T_A= + 25 °C.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.3.4

Serial Wire Debug Port (SW-DP) Timing

The following parameters are applicable for communication through the SW-DP

interface.

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

Table 29

SWD Interface Timing Parameters(Operating Conditions apply)

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ. Max.

SWDCLK high time

SWDCLK low time

t₁SR

t₂SR

t₃SR

–

500000 ns

–

SWDIO input setup

–

to SWDCLK rising edge

SWDIO input hold

t₄SR

–

after SWDCLK rising edge

SWDIO output valid time t₅CC

after SWDCLK rising edge

–

C_L= 50 pF

C_L= 30 pF

SWDIO output hold time t₆CC

from SWDCLK rising edge

t₁

t₂

SWDCLK

t₆

SWDIO

(Output)

t₅

t₃

t₄

SWDIO

(Input )

Figure 24

SWD Timing

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.3.5

SPD Timing Requirements

The optimum SPD decision time between 0_Band 1_Bis 0.75 µs. With this value the

system has maximum robustness against frequency deviations of the sampling clock on

tool and on device side. However it is not always possible to exactly match this value

with the given constraints for the sample clock. For instance for a oversampling rate of

4, the sample clock will be 8 MHz and in this case the closest possible effective decision

time is 5.5 clock cycles (0.69 µs).

Table 30

Optimum Number of Sample Clocks for SPD

Sample Effective Remark

Sample Sampling Sample

Freq.

Factor

Clocks 0_BClocks 1_BDecision

Time¹⁾

8 MHz

1 to 5

6 to 12

0.69 µs

The other closest option

(0.81 µs) for the effective

decision time is less robust.

1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0_Bsample clocks)

For a balanced distribution of the timing robustness of SPD between tool and device, the

timing requirements for the tool are:

•

Frequency deviation of the sample clock is +/- 5%

Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal

sample frequency)

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.3.6

Peripheral Timings

Note: These parameters are not subject to production test, but verified by design and/or

characterization.

3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note: Operating Conditions apply.

Table 31

USIC SSC Master Mode Timing

Symbol Values

Typ. Max.

Parameter

Unit Note /

Test Condition

Min.

_CLKCC 4/MCLK

SCLKOUT master clock

period

−

Slave select output SELO t₁CC

active to first SCLKOUT

transmit edge

t_CLK/2 - 28

−

Slave select output SELO t₂CC

inactive after last

−

SCLKOUT receive edge

Data output DOUT[3:0]

valid time

t₃CC -28

t₄SR 75

−

Receive data input

−

DX0/DX[5:3] setup time to

SCLKOUT receive edge

Data input DX0/DX[5:3]

hold time from SCLKOUT

receive edge

t₅SR

−

Table 32

USIC SSC Slave Mode Timing

Parameter

Symbol

Min.

Values

Unit Note /

Test Conditio

Typ. Max.

DX1 slave clock period

t_CLKSR 4/MCLK

t₁₀SR 16

−

Select input DX2 setup to

first clock input DX1 transmit

edge¹⁾

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 32

USIC SSC Slave Mode Timing

Parameter

Symbol

Min.

Values

Typ. Max.

Unit Note /

Test Conditio

Select input DX2 hold after t₁₁

last clock input DX1 receive

edge¹⁾

−

Receive data input

t₁₂

−

DX0/DX[5:3] setup time to

shift clock receive edge¹⁾

Data input DX0/DX[5:3] hold t₁₃

time from clock input DX1

receive edge¹⁾

−

Data output DOUT[3:0] valid t₁₄

time

1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and

receive data input (bits DXnCR.DSEN = 0).

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Master Mode Timing

t₁

t₂

Select Output

SELOx

Inactive

Active

Clock Output

SCLKOUT

Receive

Edge

Last Receive

Edge

First Transmit

Edge

Transmit

Edge

t₃

Data Output

DOUT[3:0]

t₄

t₅

Data Input

DX0/DX[5:3]

Data

valid

Data

valid

Slave Mode Timing

t₁₀

t₁₁

Select Input

DX2

Inactive

Active

Inactive

Clock Input

DX1

Receive

Edge

Last Receive

Edge

First Transmit

Edge

Transmit

Edge

t₁₂

t₁₃

Data Input

DX0/DX[5:3]

Data

valid

Data

valid

t₁₄

Data Output

DOUT[3:0]

Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.

Receive Edge: with this clock edge, receive data at receive data input is latched.

Drawn for BRGH.SCLKCFG = 00_B. Also valid for for SCLKCFG = 01_Bwith inverted SCLKOUT signa.l

USIC_SSC_TMGX.VSD

Figure 25

USIC - SSC Master/Slave Mode Timing

Note: This timing diagram shows a standard configuration, for which the slave select

signal is low-active, and the serial clock signal is not shifted and not inverted.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

3.3.6.2 Inter-IC (IIC) Interface Timing

The following parameters are applicable for a USIC channel operated in IIC mode.

Note: Operating Conditions apply.

Table 33

USIC IIC Standard Mode Timing¹⁾

Symbol Values

Parameter

Unit Note /

Test Condition

Min.

Typ.

Max.

Fall time of both SDA and t₁

300

µs

SCL

CC/SR

Rise time of both SDA and t₂

1000

SCL

CC/SR

Data hold time

t₃

CC/SR

Data set-up time

t₄

250

4.7

4.0

4.7

4.0

4.7

CC/SR

LOW period of SCL clock t₅

CC/SR

HIGH period of SCL clock t₆

CC/SR

t₇

CC/SR

Hold time for (repeated)

START condition

Set-up time for repeated t₈

START condition

CC/SR

Set-up time for STOP

condition

t₉

CC/SR

Bus free time between a t₁₀

STOP and START

CC/SR

condition

Capacitive load for each

bus line

C_bSR

400

1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines

need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,

approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

Table 34

USIC IIC Fast Mode Timing¹⁾

Parameter

Symbol

Min.

Values

Typ.

Unit Note /

Test Condition

Max.

Fall time of both SDA and t₁

20 +

300

SCL CC/SR 0.1*C_b

Rise time of both SDA and t₂

20 +

300

µs

SCL

CC/SR 0.1*C_b

Data hold time

t₃

CC/SR

Data set-up time

t₄

100

1.3

0.6

1.3

CC/SR

LOW period of SCL clock t₅

CC/SR

HIGH period of SCL clock t₆

CC/SR

t₇

CC/SR

Hold time for (repeated)

START condition

Set-up time for repeated t₈

START condition

CC/SR

Set-up time for STOP

condition

t₉

CC/SR

Bus free time between a t₁₀

STOP and START

CC/SR

condition

Capacitive load for each

bus line

C_bSR

400

1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines

need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,

approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.

2) C_brefers to the total capacitance of one bus line in pF.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

t₁

t₂

t₄

70%

30%

SDA

SCL

t₁

t₃

t₂

t₆

9^th

clock

t₇

t₅

t₁₀

SDA

SCL

t₈

t₇

t₉

9^th

clock

Figure 26

USIC IIC Timing

3.3.6.3 Inter-IC Sound (IIS) Interface Timing

The following parameters are applicable for a USIC channel operated in IIS mode.

Note: Operating Conditions apply.

Table 35

USIC IIS Master Transmitter Timing

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

Clock period

Clock HIGH

t₁CC

t₂CC

4/f_MCLK

0.35 x

t_1min

Clock Low

t₃CC

0.35 x

t_1min

Hold time

t₄CC

t₅CC

Clock rise time

0.15 x ns

t_1min

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Electrical Parameter

t₁

t₂

t₅

t₄

t₃

SCK

WA/

DOUT

Figure 27

USIC IIS Master Transmitter Timing

USIC IIS Slave Receiver Timing

Table 36

Parameter

Symbol

Values

Unit Note /

Test Condition

Min.

Typ.

Max.

Clock period

Clock HIGH

t₆SR

t₇SR

4/f_MCLK

0.35 x

t_6min

Clock Low

Set-up time

Hold time

t₈SR

t₉SR

0.35 x

t_6min

0.3 x

t_6min

₁₀SR

t₆

t₇

t₈

t₉

SCK

t₁₀

WA/

DIN

Figure 28

USIC IIS Slave Receiver Timing

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Package and Reliability

The XMC1400 is a member of the XMC1000 Family of microcontrollers. It is also

compatible to a certain extent with members of similar families or subfamilies.

Each package is optimized for the device it houses. Therefore, there may be slight

differences between packages of the same pin-count but for different device types. In

particular, the size of the exposed die pad may vary.

If different device types are considered or planned for an application, it must be ensured

that the board layout fits all packages under consideration.

4.1

Package Parameters

Table 37 provides the thermal characteristics of the packages used in XMC1400.

Table 37

Thermal Characteristics of the Packages

Parameter

Symbol

Limit Values

Min. Max.

Unit

Package Types

Exposed Die Pad

Dimensions

Ex × Ey

3.7 × 3.7 mm

4.2 × 4.2 mm

4.6 × 4.6 mm

PG-VQFN-40-17

PG-VQFN-48-73

PG-VQFN-64-6

Thermal resistance

Junction-Ambient

R_ΘJACC -

86.0

45.3

44.9

66.7

44.7

K/W

PG-TSSOP-38-9¹⁾

PG-VQFN-40-17¹⁾

PG-VQFN-48-73¹⁾

PG-LQFP-64-26¹⁾

PG-VQFN-64-6¹⁾

1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.

Note: For electrical reasons, it is required to connect the exposed pad to the board

ground V_SSP, independent of EMC and thermal requirements.

4.1.1

Thermal Considerations

When operating the XMC1400 in a system, the total heat generated in the chip must be

dissipated to the ambient environment to prevent overheating and the resulting thermal

damage.

The maximum heat that can be dissipated depends on the package and its integration

into the target board. The “Thermal resistance R_ΘJA” quantifies these parameters. The

power dissipation must be limited so that the average junction temperature does not

exceed 115 °C.

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Package and Reliability

The difference between junction temperature and ambient temperature is determined by

ΔT = (P_INT+ P_IOSTAT+ P_IODYN) × R_ΘJA

The internal power consumption is defined as

_INT= V_DDP× I_DDP(switching current and leakage current).

The static external power consumption caused by the output drivers is defined as

_IOSTAT= Σ((V_DDP-V_OH) × I_OH) + Σ(V_OL× I_OL)

The dynamic external power consumption caused by the output drivers (P_IODYN) depends

on the capacitive load connected to the respective pins and their switching frequencies.

If the total power dissipation for a given system configuration exceeds the defined limit,

countermeasures must be taken to ensure proper system operation:

•

Reduce V_DDP, if possible in the system

Reduce the system frequency

Reduce the number of output pins

Reduce the load on active output drivers

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Package and Reliability

4.2

Package Outlines

Figure 29

PG-TSSOP-38-9

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Package and Reliability

9 x 0.4 = 3.6

0.4

0.9 MAX.

0.1 A C 2x

0.05

A B C

40x

0.08 C

COPLANARITY

0.1 C

Index Marking

0.1 B C 2x

40x

±0.05

0.2

0.07

0.05

A B C

Index Marking

Figure 30

(0.2)

±0.1

3.6

0.05

A B C

0.05 MAX.

STANDOFF

PG-VQFN-40-13, -14, -17-PO V05

PG-VQFN-40-17

11 x 0.5 = 5.5

0.5

0.9 MAX.

(0.203)

0.1 A

48x

0.05 C

COPLANARITY

0.1 C

±0.1

4.1

0.1 A B C

Index Marking

0.1 B

+0.05

-0.07

48x

0.1

0.25

±0.05

0.4

A B C

Index Marking

0.05 MAX.

0.05

STAND OFF

PG-VQFN-48-35, -73-PO V04

Figure 31

PG-VQFN-48-73

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Package and Reliability

15 x 0.5 = 7.5

0.15

0.5

±0.15

0.6

0.08 C 64x

COPLANARITY

64x

±0.05

0.22

0.08

C A-B D

SEATING PLANE

0.2 C A-B D 64x

0.2 H A-B D 4x

Index Marking

1) Does not include plastic or metal protrusion of 0.25 max. per side

2) Does not include dambar protrusion of 0.08 max. per side

PG-LQFP-64-10, -21, -26-PO V03

Figure 32

PG-LQFP-64-26

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

XMC1400 AA-Step

XMC1000 Family

Quality Declaration

15 x 0.4 = 6

0.4

0.9 MAX.

(0.2)

0.1 A C 2x

0.1 C

64x

0.08 C

COPLANARITY

±0.1

4.5

0.1 A B C

Index Marking

64x

0.1 B C 2x

±0.05

0.2

0.4

0.07

0.05

A B C

0.05 MAX.

STAND OFF

Index Marking

PG-VQFN-64-6-PO V04

Figure 33

PG-VQFN-64-6

All dimensions in mm.

Quality Declaration

Table 38 shows the characteristics of the quality parameters in the XMC1400.

Table 38

Quality Parameters

Symbol Limit Values

Parameter

Unit Notes

Min.

Max.

ESD susceptibility

according to Human Body SR

Model (HBM)

V_HBM

2000

Conforming to

EIA/JESD22-

A114-B

ESD susceptibility

V_CDM

500

Conforming to

according to Charged

Device Model (CDM) pins

JESD22-C101-C

Moisture sensitivity level

MSL

JEDEC

J-STD-020D

Soldering temperature

T_SDR

260

°C

Profile according

to JEDEC

J-STD-020D

Data Sheet

V1.3, 2016-10

Subject to Agreement on the Use of Product Information

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

SP001308154 [INFINEON]

相关型号：

SP001308172

SP001337840

SP001344584

SP001344588

SP001344590

SP001368958

SP001379684

SP001385014

SP001387576

SP001410042

SP001410046

SP001422940