STK14CA8C-35C35M_技术文档

STK14CA8C-3

1-Mbit (128K × 8) nvSRAM

1-Mbit (128K

× 8) nvSRAM

Features

Functional Description

■ 35 ns access time

The Cypress STK14CA8C-3 is a fast static RAM, with a

nonvolatile element in each memory cell. The memory is

organized as 128KB. The embedded nonvolatile elements

incorporate QuantumTrap technology, producing the world’s

most reliable nonvolatile memory. The SRAM provides infinite

read and write cycles, while independent nonvolatile data

resides in the highly reliable QuantumTrap cell. Data transfers

from the SRAM to the nonvolatile elements (the STORE

operation) takes place automatically at power-down. On

power-up, data is restored to the SRAM (the RECALL operation)

from the nonvolatile memory. Both the STORE and RECALL

operations are also available under software control.

■ Internally organized as 128K × 8

■ Hands-off automatic STORE on power-down with only a small

capacitor

■ STORE to QuantumTrap nonvolatile elements initiated by

software, device pin, or autostore on power-down

■ RECALL to SRAM initiated by software or power-up

■ Infinite read, write, and RECALL cycles

■ 1 million STORE cycles to QuantumTrap

■ 20-year data retention

■ Power supply operation

❐ Single 3.0 V + 20%, – 10% operation for Industrial

Temperature

❐ Single 3.3 V + 0.3 V operation for Military Temperature

■ Industrial and Military temperatures

■ 32-pin CDIP package

Logic Block Diagram

V_CAP

V_CC

Quatrum Trap

1024 X 1024

A₅

R

O

W

POWER CONTROL

A₆

A₇

STORE

RECALL

A₈

A9

D

E

C

O

D

E

R

STORE/RECALL

CONTROL

HSB

STATIC RAM

ARRAY

1024 X 1024

A₁₂

A₁₃

A₁₄

A₁₅

A₁₆

SOFTWARE

DETECT

A14 - A2

DQ₀

I

DQ₁

DQ₂

DQ₃

N

P

U

T

B

U

F

E

R

S

DQ₄

DQ₅

DQ₆

COLUMN I/O

DQ₇

COLUMN DEC

OE

A₂

A₀A₁

A₃A₄A₁₀A₁₁

CE

WE

Cypress Semiconductor Corporation

Document Number: 002-23969 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 26, 2019

STK14CA8C-3

Contents

Pinout ................................................................................3

Pin Definitions ..................................................................3

Device Operation ..............................................................4

SRAM Read ................................................................4

SRAM Write .................................................................4

AutoStore Operation ....................................................4

Hardware STORE Operation .......................................4

Hardware RECALL (Power-up) ...................................5

Software STORE .........................................................5

Software RECALL .......................................................5

Preventing AutoStore ..................................................5

Data Protection ............................................................5

Maximum Ratings .............................................................7

Operating Range ...............................................................7

DC Electrical Characteristics ..........................................7

Data Retention and Endurance .......................................9

Capacitance ......................................................................9

Thermal Resistance ..........................................................9

AC Test Loads ..................................................................9

AC Test Conditions ..........................................................9

AC Switching Characteristics .......................................10

SRAM Read Cycle ....................................................10

SRAM Write Cycle .....................................................10

Switching Waveforms ....................................................11

AutoStore/Power-up RECALL .......................................13

Switching Waveforms ....................................................13

Software Controlled STORE/RECALL Cycle ................14

Switching Waveforms ....................................................14

Hardware STORE Cycle .................................................15

Switching Waveforms ....................................................15

Truth Table For SRAM Operations ................................16

Ordering Information ......................................................17

Ordering Code Definitions

for Industrial Temperature ................................................17

Ordering Code Definitions

for Military Temperature ...................................................17

Package Diagrams ..........................................................18

Acronyms ........................................................................19

Document Conventions .................................................19

Units of Measure .......................................................19

Document History Page .................................................20

Sales, Solutions, and Legal Information ......................21

Worldwide Sales and Design Support .......................21

Products ....................................................................21

PSoC® Solutions ......................................................21

Cypress Developer Community .................................21

Technical Support .....................................................21

Document Number: 002-23969 Rev. *B

Page 2 of 21

STK14CA8C-3

Pinout

Figure 1. 32-pin CDIP pinout

V_CAP

A₁₄

1

V_CC

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

HSB

3

A₁₂

A₇

W

A₁₃

A₈

A₉

4

A₆

A₅

A₄

A₃

5

6

A₁₁

G

7

8

(TOP)

A₁₆

A₂

A₁₅

A₁₀

9

10

11

12

13

14

15

16

A₁

A₀

E

DQ₇

DQ₀

DQ₁

DQ₂

V_SS

DQ₆

DQ₅

DQ₄

DQ₃

Pin Definitions

Alternate

Pin Name

I/O Type

Description

Address inputs. Used to select one of the 131,072 bytes of the nvSRAM.

Pin Name

A₀–A₁₆

DQ₀–DQ₇

W

Input

Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.

WE

Input

Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O

pins is written to the specific address location.

Input

Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

chip.

E

CE

OE

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers

during read cycles. I/O pins are tri-stated on deasserting OE HIGH.

G

V_SS

V_CC

Ground

Ground for the device. Must be connected to the ground of the system.

Power supply Power supply inputs to the device.

Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE

is in progress. When pulled LOW, external to the chip, it initiates a nonvolatile STORE

operation. After each Hardware and Software STORE operation HSB is driven HIGH for a

short time (t_HHHD) with standard output high current and then a weak internal pull-up resistor

keeps this pin HIGH (external pull-up resistor connection is optional).

HSB

V_CAP

Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from

SRAM to nonvolatile elements.

Document Number: 002-23969 Rev. *B

Page 3 of 21

STK14CA8C-3

Figure 2 shows the proper connection of the storage capacitor

(V_CAP) for automatic STORE operation. Refer to DC Electrical

Characteristics on page 7 for the size of V_CAP. The voltage on

the V_CAPpin is driven to V_CCby a regulator on the chip. Place a

pull-up on WE to hold it inactive during power-up. This pull-up is

only effective if the WE signal is tristate during power-up. Many

MPUs tristate their controls on power-up. This must be verified

when using the pull-up. When the nvSRAM comes out of

power-on-RECALL, the MPU must be active or the WE held

inactive until the MPU comes out of reset.

Device Operation

The STK14CA8C-3 nvSRAM is made up of two functional

components paired in the same physical cell. They are an SRAM

memory cell and a nonvolatile QuantumTrap cell. The SRAM

memory cell operates as a standard fast static RAM. Data in the

SRAM is transferred to the nonvolatile cell (the STORE

operation), or from the nonvolatile cell to the SRAM (the RECALL

operation). Using this unique architecture, all cells are stored and

recalled in parallel. During the STORE and RECALL operations,

SRAM read and write operations are inhibited. The

STK14CA8C-3 supports infinite reads and writes similar to a

typical SRAM. In addition, it provides infinite RECALL operations

from the nonvolatile cells and up to 1 million STORE operations.

Refer to the Truth Table For SRAM Operations on page 16 for a

complete description of read and write modes.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware STORE operations are ignored unless at least one

write operation has taken place since the most recent STORE or

RECALL cycle. Software initiated STORE cycles are performed

regardless of whether a write operation has taken place. The

HSB signal is monitored by the system to detect if an AutoStore

cycle is in progress.

SRAM Read

Figure 2. AutoStore Mode

V_CC

The STK14CA8C-3 performs a read cycle when CE and OE are

LOW and WE and HSB are HIGH. The address specified on pins

A_0–16determines which of the 131,072 data bytes each are

accessed. When the read is initiated by an address transition,

the outputs are valid after a delay of t_AA(read cycle 1). If the read

0.1 uF

is initiated by CE or OE, the outputs are valid at t_ACEor at t_DOE

,

whichever is later (read cycle 2). The data output repeatedly

responds to address changes within the t_AAaccess time without

the need for transitions on any control input pins. This remains

valid until another address change or until CE or OE is brought

HIGH, or WE or HSB is brought LOW.

V_CC

WE

V_CAP

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB

is HIGH. The address inputs must be stable before entering the

write cycle and must remain stable until CE or WE goes HIGH at

the end of the cycle. The data on the common I/O pins DQ_0–7are

written into the memory if the data is valid t_SDbefore the end of

a WE-controlled write or before the end of a CE-controlled write.

Keep OE HIGH during the entire write cycle to avoid data bus

contention on common I/O lines. If OE is left LOW, internal

circuitry turns off the output buffers t_HZWEafter WE goes LOW.

V_CAP

V_SS

Hardware STORE Operation

The STK14CA8C-3 provides the HSB pin to control and

acknowledge the STORE operations. Use the HSB pin to

request a Hardware STORE cycle. When the HSB pin is driven

LOW, the STK14CA8C-3 conditionally initiates a STORE

operation after t_DELAY. An actual STORE cycle only begins if a

write to the SRAM has taken place since the last STORE or

RECALL cycle. The HSB pin also acts as an open drain driver

(internal 100 k weak pull-up resistor) that is internally driven

LOW to indicate a busy condition when the STORE (initiated by

any means) is in progress.

AutoStore Operation

The STK14CA8C-3 stores data to the nvSRAM using one of the

following three storage operations: Hardware STORE activated

by HSB; Software STORE activated by an address sequence;

AutoStore on device power-down. The AutoStore operation is a

unique feature of QuantumTrap technology and is enabled by

default on the STK14CA8C-3.

During a normal operation, the device draws current from V_CCto

charge a capacitor connected to the V_CAPpin. This stored

charge is used by the chip to perform a single STORE operation.

If the voltage on the V_CCpin drops below V_SWITCH, the part

automatically disconnects the V_CAPpin from V_CC. A STORE

operation is initiated with power provided by the V_CAPcapacitor.

Note After each Hardware and Software STORE operation HSB

is driven HIGH for a short time (t_HHHD) with standard output high

current and then remains HIGH by internal 100 k pull-up

resistor.

SRAM write operations that are in progress when HSB is driven

LOW by any means are given time (t_DELAY) to complete before

the STORE operation is initiated. However, any SRAM write

cycles requested after HSB goes LOW are inhibited until HSB

returns HIGH. In case the write latch is not set, HSB is not driven

LOW by the STK14CA8C-3. But any SRAM read and write

cycles are inhibited until HSB is returned HIGH by MPU or other

external source.

Note If the capacitor is not connected to V_CAPpin, AutoStore

must be disabled using the soft sequence specified in Preventing

AutoStore on page 5. In case AutoStore is enabled without a

capacitor on V_CAPpin, the device attempts an AutoStore

operation without sufficient charge to complete the Store. This

corrupts the data stored in nvSRAM.

Document Number: 002-23969 Rev. *B

Page 4 of 21

STK14CA8C-3

During any STORE operation, regardless of how it is initiated,

the STK14CA8C-3 continues to drive the HSB pin LOW,

releasing it only when the STORE is complete. Upon completion

of the STORE operation, the nvSRAM memory access is

inhibited for t_LZHSBtime after HSB pin returns HIGH. Leave the

HSB unconnected if it is not used.

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x0C63 Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared. Next, the nonvolatile information is transferred into the

SRAM cells. After the t_RECALLcycle time, the SRAM is again

ready for read and write operations. The RECALL operation

does not alter the data in the nonvolatile elements.

Hardware RECALL (Power-up)

During power-up or after any low power condition

(V_CC< V_SWITCH), an internal RECALL request is latched. When

V_CCagain exceeds the sense voltage of V_SWITCH, a RECALL

cycle is automatically initiated and takes t_HRECALLto complete.

During this time, HSB is driven low by the HSB driver.

Preventing AutoStore

The AutoStore function is disabled by initiating an AutoStore

disable sequence. A sequence of read operations is performed

in a manner similar to the Software STORE initiation. To initiate

the AutoStore disable sequence, the following sequence of CE

or OE controlled read operations must be performed:

Software STORE

Data is transferred from SRAM to the nonvolatile memory by a

software address sequence. The STK14CA8C-3 Software

STORE cycle is initiated by executing sequential CE or OE

controlled read cycles from six specific address locations in

exact order. During the STORE cycle an erase of the previous

nonvolatile data is first performed, followed by a program of the

nonvolatile elements. After a STORE cycle is initiated, further

input and output are disabled until the cycle is completed.

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x0B45 AutoStore Disable

Because a sequence of READs from specific addresses is used

for STORE initiation, it is important that no other read or write

accesses intervene in the sequence, or the sequence is aborted

and no STORE or RECALL takes place.

The AutoStore is reenabled by initiating an AutoStore enable

sequence. A sequence of read operations is performed in a

manner similar to the Software RECALL initiation. To initiate the

AutoStore enable sequence, the following sequence of CE or OE

controlled read operations must be performed:

To initiate the Software STORE cycle, the following read

sequence must be performed:

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x0FC0 Initiate STORE cycle

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x0B46 AutoStore Enable

The software sequence may be clocked with CE controlled reads

or OE controlled reads, with WE kept HIGH for all the six READ

sequences. After the sixth address in the sequence is entered,

the STORE cycle commences and the chip is disabled. HSB is

driven LOW. After the t_STOREcycle time is fulfilled, the SRAM is

activated again for the read and write operation.

If the AutoStore function is disabled or reenabled, a manual

STORE operation (Hardware or Software) must be issued to

save the AutoStore state through subsequent power-down

cycles. The part comes from the factory with AutoStore enabled

and 0x00 written in all cells.

Data Protection

Software RECALL

The STK14CA8C-3 protects data from corruption during low

voltage conditions by inhibiting all externally initiated STORE

and write operations. The low voltage condition is detected when

Data is transferred from nonvolatile memory to the SRAM by a

software address sequence. A Software RECALL cycle is

initiated with a sequence of read operations in a manner similar

to the Software STORE initiation. To initiate the RECALL cycle,

the following sequence of CE or OE controlled read operations

must be performed:

V_CCis less than V_SWITCH. If the STK14CA8C-3 is in a write mode

(both CE and WE are LOW) at power-up, after a RECALL or

STORE, the write is inhibited until the SRAM is enabled after

t_LZHSB(HSB to output active). This protects against inadvertent

writes during power-up or brown out conditions.

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

Document Number: 002-23969 Rev. *B

Page 5 of 21

STK14CA8C-3

Table 1. Mode Selection

[1]

A₁₆–A₀

Mode

I/O

Power

Standby

Active

CE

WE

OE

H

X

Not selected

Read SRAM

Write SRAM

Output high Z

Output data

Input data

L

H

L

X

L

Active

Active^[2]

H

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8B45

Read SRAM

Output data Output

data Output data

Output data Output

data Output data

AutoStore disable

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4B46

Read SRAM

AutoStore enable

Output data Output

data Output data

Output data Output

data Output data

Active^[2]

[2]

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8FC0

Read SRAM

Nonvolatile

STORE

Output data Output

data Output data

Output data Output

data Output high Z

Active I_CC2

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4C63

Read SRAM

Nonvolatile

RECALL

Output data Output

data Output data

Output data Output

data Output high Z

Active^[2]

Notes

1. While there are 17 address lines on the STK14CA8C-3, only the lower 14 are used to control software modes.

2. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.

Document Number: 002-23969 Rev. *B

Page 6 of 21

STK14CA8C-3

Package power dissipation capability

(T_A= 25 °C) ................................................................. 1.0 W

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Surface mount Pb soldering temperature

(3 seconds) .............................................................. +260 C

Storage temperature ................................ –65 C to +150 C

Maximum accumulated storage time:

DC output current

(1 output at a time, 1 s duration) ................................. 15 mA

Static discharge voltage

(per MIL-STD-883, Method 3015) ......................... > 2001 V

At 150 C ambient temperature ...................... 1000 h

At 85 C ambient temperature .................... 20 Years

Maximum junction temperature ................................. 150 C

Supply voltage on V_CCrelative to V_SS...........–0.5 V to 4.1 V

Latch-up current .....................................................> 140 mA

Operating Range

Voltage applied to outputs

in high Z state ..................................... –0.5 V to V_CC+ 0.5 V

Range

Industrial

Military

Ambient Temperature

–40 C to +85 C

V_CC

2.7 V to 3.6 V

3.0 V to 3.6 V

Input voltage .......................................–0.5 V to V_CC+ 0.5 V

–55 C to +125 C

Transient voltage (< 20 ns)

on any pin to ground potential ............–2.0 V to V_CC+ 2.0 V

DC Electrical Characteristics

Over the Operating Range

Parameter

Description

Power supply

Test Conditions

Min

2.7

3.0

–

Typ ^[3]

3.0

3.3

–

Max

3.6

70

Unit

V

V_CC

Industrial

Military

V

I_CC1

Average V_CCcurrent

t_RC= 35 ns

Industrial

Military

mA

Values obtained without output

loads (I_OUT= 0 mA)

–

85

I_CC2

Average V_CCcurrent during

STORE

All inputs don’t care,

Industrial

Military

–

10

15

mA

V_CC= Max

Average current for duration

t_STORE

I_CC3

Average V_CCcurrent at

All inputs cycling at CMOS levels.

Values obtained without output loads

(I_OUT= 0 mA).

–

35

–

mA

t

_RC= 200 ns, V_CC(Typ), 25 °C

I_CC4

Average V_CAPcurrent during

AutoStore cycle

All inputs don’t care. Average Industrial

–

5

10

5

mA

current for duration t_STORE

Military

I_SB

V_CCstandby current

CE > (V_CC– 0.2 V).

_IN< 0.2 V or > (V_CC– 0.2 V).

Standby current level after

nonvolatile cycle is complete.

Inputs are static. f = 0 MHz.

Industrial

Military

V

10

[4]

I_IX

Input leakage current (except

HSB)

V_CC= Max, V_SS< V_IN< V_CC

Industrial

Military

–1

–5

–

+1

+5

+1

+5

+1

+5

A

Input leakage current (for HSB)

Industrial

Military

–100

–1

I_OZ

Off-state output leakage current V_CC= Max, V_SS< V_OUT< V_CC

,

Industrial

Military

CE or OE > V_IHor WE < V_IL

–5

Notes

3. Typical values are at 25 °C, V = V

. Not 100% tested.

CC

CC(Typ)

4. The HSB pin has I

= –2 µA for V of 2.4 V when both active high and low drivers are disabled. When they are enabled standard V and V are valid. This

OUT

O

H

O

H

O

L

parameter is characterized but not tested.

Document Number: 002-23969 Rev. *B

Page 7 of 21

STK14CA8C-3

DC Electrical Characteristics (continued)

Over the Operating Range

Parameter

V_IH

Description

Input HIGH voltage

Test Conditions

Min

Typ ^[3]

Max

V_CC+ 0.5

0.8

Unit

V

Industrial

Military

2.0

–

2.2

V

V_IL

Input LOW voltage

Output HIGH voltage

Output LOW voltage

Storage capacitor

V_SS– 0.5

–

V

V_OH

V_OL

V_CAP

I_OUT= –2 mA

2.4

–

V

I_OUT= 4 mA

–

0.4

V

[5]

Between V_CAPpin and V_SS

61

–

68

–

180

F

V

[6, 7]

V_VCAP

Maximum voltage driven on V_CAPV_CC= Max

pin by the device

V_CC

Notes

5. Min V

value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V

value guarantees that the capacitor on

CAP

V

is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it

CAP

is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V

options.

CAP

6. Maximum voltage on V

pin (V

) is provided for guidance when choosing the V

capacitor. The voltage rating of the V capacitor across the operating

CAP

VCAP

CAP

temperature range should be higher than the V

voltage.

VCAP

7. These parameters are guaranteed by design and are not tested.

Document Number: 002-23969 Rev. *B

Page 8 of 21

STK14CA8C-3

Data Retention and Endurance

Over the Operating Range

Parameter

Description

Min

20

Unit

DATA_R

Data retention

Industrial

Military

Years

1

NV_C

Nonvolatile STORE operations

Industrial

Military

1,000

100

K

Capacitance

Parameter ^[8]

Description

Test Conditions

Max

Unit

pF

C_IN

Input capacitance (except HSB) T_A= 25 C, f = 1 MHz, V_CC= V_CC(Typ)

Input capacitance (for HSB)

7

8

7

8

pF

C_OUT

Output capacitance (except HSB)

pF

Output capacitance (for HSB)

pF

Thermal Resistance

Parameter ^[8]

Description

Test Conditions

32-pin CDIP Unit

_JA

Thermal resistance

(junction to ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, in

accordance with EIA/JESD51.

22.3

C/W

_JC

Thermal resistance

(junction to case)

11

C/W

AC Test Loads

Figure 3. AC Test Loads

577 

for tristate specs

577 

3.0 V

R1

OUTPUT

R2

789 

R2

789 

5 pF

30 pF

AC Test Conditions

Input Pulse Levels .................................................0 V to 3 V

Input Rise and Fall Times (10% to 90%) .................... < 3 ns

Input and Output Timing Reference Levels .................. 1.5 V

Note

8. These parameters are guaranteed by design and are not tested.

Document Number: 002-23969 Rev. *B

Page 9 of 21

STK14CA8C-3

AC Switching Characteristics

Over the Operating Range

Parameters ^[9]

35 ns

Unit

Description

Cypress

Alt. Parameter

Parameter

Min

Max

SRAM Read Cycle

t_ACE

t_ACS

t_RC

Chip enable access time

Read cycle time

–

35

–

ns

[10]

35

t_RC

[11]

t_AA

t_OE

t_OH

t_LZ

Address access time

–

3

–

0

–

0

–

35

15

–

ns

t_AA

Output enable to data valid

t_DOE

[11]

Output hold after address change

Chip enable to output active

Chip disable to output inactive

Output enable to output active

Output disable to output inactive

Chip enable to power active

Chip disable to power standby

t_OHA

[12, 13]

–

t_LZCE

t_HZCE

t_LZOE

[12, 13]

t_HZ

t_OLZ

t_OHZ

t_PA

13

–

13

–

t_HZOE

[12]

t_PU

[12]

t_PS

35

t_PD

SRAM Write Cycle

t_WC

t_PWE

t_SCE

t_SD

t_WC

t_WP

t_CW

t_DW

t_DH

t_AW

t_AS

Write cycle time

35

25

12

0

–

ns

Write pulse width

Chip enable to end of write

Data setup to end of write

Data hold after end of write

Address setup to end of write

Address setup to start of write

Address hold after end of write

Write enable to output disable

–

t_HD

–

t_AW

t_SA

25

0

–

t_HA

t_WR

0

–

[12, 13, 14]

t_WZ

–

13

t_HZWE

[12, 13]

t_OW

Output active after end of write

3

–

ns

t_LZWE

Notes

9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V (typ), and output loading of the specified

CC

I

/I and load capacitance shown in Figure 3 on page 9.

OL OH

10. WE must be HIGH during SRAM read cycles.

11. Device is continuously selected with CE and OE LOW.

12. These parameters are guaranteed by design and are not tested.

13. Measured ±200 mV from steady state output voltage.

14. If WE is low when CE goes low, the outputs remain in the high impedance state.

Document Number: 002-23969 Rev. *B

Page 10 of 21

STK14CA8C-3

Switching Waveforms

Address

Figure 4. SRAM Read Cycle No. 1 (Address Controlled) ^{[15, 16, 17]}

t_RC

Address Valid

t_AA

Output Data Valid

Previous Data Valid

t_OHA

Data Output

Figure 5. SRAM Read Cycle No. 2 (CE and OE Controlled) ^{[15, 17]}

Address

CE

Address Valid

t_RC

t_HZCE

t_ACE

t_AA

t_LZCE

t_HZOE

t_DOE

OE

t_LZOE

High Impedance

Data Output

Output Data Valid

t_PU

t_PD

Active

I_CC

Standby

Notes

15. WE must be HIGH during SRAM read cycles.

16. Device is continuously selected with CE and OE LOW.

17. HSB must remain HIGH during READ and WRITE cycles.

Document Number: 002-23969 Rev. *B

Page 11 of 21

STK14CA8C-3

Switching Waveforms (continued)

Figure 6. SRAM Write Cycle No. 1 (WE Controlled) ^{[18, 19, 20]}

t_WC

Address

CE

Address Valid

t_SCE

t_HA

t_AW

t_PWE

WE

Data Input

Data Output

t_SA

t_HD

t_SD

Input Data Valid

t_LZWE

t_HZWE

High Impedance

Previous Data

Figure 7. SRAM Write Cycle No. 2 (CE Controlled) ^{[18, 19, 20]}

t_WC

Address Valid

Address

t_SA

t_SCE

t_HA

CE

t_PWE

WE

t_HD

t_SD

Input Data Valid

Data Input

High Impedance

Data Output

Notes

18. HSB must remain HIGH during READ and WRITE cycles.

19. If WE is low when CE goes low, the outputs remain in the high impedance state.

20. CE or WE must be > V during address transitions.

IH

Document Number: 002-23969 Rev. *B

Page 12 of 21

STK14CA8C-3

AutoStore/Power-up RECALL

Over the Operating Range

STK14CA8C-3

Unit

Parameter

Description

Min

Max

[21]

Power-up RECALL duration

STORE cycle duration

–

20

ms

ns

t_HRECALL

[22]

–

8

t_STORE

[23]

Time allowed to complete SRAM write cycle

Low voltage trigger level

35

t_DELAY

Industrial

Military

–

2.65

2.95

–

V

V_SWITCH

[24]

V_CCrise time

150

µs

t_VCCRISE

[24]

HSB output disable voltage

–

1.9

V

V_HDIS

[24]

t_LZHSB

HSB to output active time

HSB high active time

–

5

µs

ns

[24]

t_HHHD

500

Switching Waveforms

Figure 8. AutoStore or Power-up RECALL ^[25]

V_CC

V_SWITCH

V_HDIS

22

Note

22

t_VCCRISE

t_STORE

Note

t_HHHD

26

Note

HSB OUT

AutoStore

t_DELAY

t_LZHSB

t_DELAY

POWER-

UP

RECALL

t_HRECALL

Read & Write

Inhibited

(RWI)

Read & Write

POWER-UP

RECALL

BROWN

OUT

AutoStore

POWER

DOWN

AutoStore

POWER-UP

RECALL

Notes

21. t

starts from the time V rises above V .

SWITCH

HRECALL

CC

22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

23. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t

24. These parameters are guaranteed by design and are not tested.

.

DELAY

25. Read and Write cycles are ignored during STORE, RECALL, and while V is less than V

.

CC

SWITCH

26. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.

Document Number: 002-23969 Rev. *B

Page 13 of 21

STK14CA8C-3

Software Controlled STORE/RECALL Cycle

Over the Operating Range

35 ns

Unit

Parameter ^{[27, 28]}

Description

Min

Max

t_RC

STORE/RECALL initiation cycle time

Address setup time

35

0

–

ns

µs

t_SA

–

t_CW

Clock pulse width

25

0

t_HA

Address hold time

–

t_RECALL

RECALL duration

–

200

Switching Waveforms

Figure 9. CE and OE Controlled Software STORE/RECALL Cycle ^[28]

t_RC

Address

Address #1

t_CW

Address #6

t_CW

t_SA

CE

t_SA

t_HA

OE

t_HHHD

t_HZCE

HSB (STORE only)

DQ (DATA)

29

Note

t_DELAY

t_LZCE

t_LZHSB

High Impedance

t_STORE/t_RECALL

RWI

Figure 10. AutoStore Enable / Disable Cycle ^[28]

t_RC

Address

Address #1

t_CW

Address #6

t_CW

t_SA

CE

t_SA

t_HA

OE

t_SS

t_HZCE

29

t_LZCE

t_DELAY

Note

DQ (DATA)

RWI

Notes

27. The software sequence is clocked with CE controlled or OE controlled reads.

28. The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.

29. DQ output data at the sixth read may be invalid since the output is disabled at t

time.

DELAY

Document Number: 002-23969 Rev. *B

Page 14 of 21

STK14CA8C-3

Hardware STORE Cycle

Over the Operating Range

STK14CA8C-3

Unit

Parameter

Description

Min

–

Max

35

t_DHSB

t_PHSB

HSB to output active time when write latch not set

Hardware STORE pulse width

ns

s

15

–

[30, 31]

t_SS

Soft sequence processing time

100

Switching Waveforms

Figure 11. Hardware STORE Cycle ^[32]

Write Latch set

t

PHSB

HSB (IN)

t

STORE

t

HHHD

DELAY

HSB (OUT)

SO

t

LZHSB

RWI

Write Latch not set

t

PHSB

HSB (IN)

HSB pin is driven high to V

only by Internal

CCQ

100 K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

HSB (OUT)

RWI

t

DELAY

DHSB

Figure 12. Soft Sequence Processing ^{[30, 31]}

t_SS

Soft Sequence

Command

Soft Sequence

Command

Address

Address #1

t_SA

Address #6

t_CW

Address #1

Address #6

t_CW

CE

V_CC

Notes

30. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

31. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

32. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

Document Number: 002-23969 Rev. *B

Page 15 of 21

STK14CA8C-3

Truth Table For SRAM Operations

HSB must remain HIGH for SRAM operations.

CE

H

L

WE

X

OE

X

Inputs/Outputs

High Z

Mode

Deselect/power-down

Read

Power

Standby

Active

H

L

Data out (DQ₀–DQ₇)

High Z

L

H

Output disabled

Write

L

X

Data in (DQ₀–DQ₇)

Document Number: 002-23969 Rev. *B

Page 16 of 21

STK14CA8C-3

Ordering Information

Speed

Package

Diagram

Operating

Range

Ordering Code

(ns)

Package Type

35

STK14CA8C-35C35M

002-23724 32-pin CDIP

Military

All the mentioned parts are Pb-free.

Ordering Code Definitions for Industrial Temperature

STK14CA8C-3 C 35 I TR

Packaging Option:

Blank = Tube

TR = Tape and Reel

Temperature Range:

Blank = Commercial (0 to 70 °C)

I - Industrial (–40 to 85 °C)

Speed:

35 = 35 ns

Package

C = 32-pin CDIP

Ordering Code Definitions for Military Temperature

STK14CA8C - 3 5 C 35 M TR

Packaging Option:

Blank = Tube

TR = Tape and Reel

Temperature Range

M = Military (–55 to 125 °C)

Access Time

35 = 35 ns

Package

C = 32-pin CDIP

Endurance

5 = Military (10⁵Cycles)

Document Number: 002-23969 Rev. *B

Page 17 of 21

STK14CA8C-3

Package Diagram

Figure 13. 32-pin Side Braze DIP (40.64 × 7.49 × 3.96 mm) Package Outline, 002-23724

D

b2

eA

E

E1

c

TOP VIEW

A2

A

A1 L

e

b

SIDE VIEW

DIMENSIONS

NOM

-

NOTES:

SYMBOL

MIN

-

MAX

3.96

1.52

2.44

0.58

1.65

0.31

41.91

8.13

7.75

1. ALL DIMENSIONS ARE IN MILLIMETERS.

A

A1

A2

b

b2

c

D

E

E1

e

eA

L

1.02

2.18

0.38

1.14

0.23

40.26

7.36

7.24

1.27

-

0.48

-

0.25

40.64

7.87

7.49

2.54 BSC

7.62 REF

-

3.18

4.31

002-23724 *B

Document Number: 002-23969 Rev. *B

Page 18 of 21

STK14CA8C-3

Acronyms

Document Conventions

Units of Measure

Acronym

Description

chip enable

Symbol

°C

Unit of Measure

CE

CMOS

complementary metal oxide semiconductor

electronic industries alliance

hardware store busy

degree Celsius

kilohm

k

MHz

A

F

s

mA

ms

mV

ns

EIA

megahertz

microampere

microfarad

microsecond

milliampere

millisecond

millivolt

HSB

I/O

input/output

JEDEC

joint electron devices engineering council

non-volatile static random access memory

output enable

nvSRAM

OE

RoHS

restriction of hazardous substances

read and write inhibited

RWI

nanosecond

ohm

SRAM

WE

static random access memory

write enable



%

percent

pF

ps

picofarad

picosecond

volt

V

W

watt

Document Number: 002-23969 Rev. *B

Page 19 of 21

STK14CA8C-3

Document History Page

Document Title: STK14CA8C-3, 1-Mbit (128K × 8) nvSRAM

Document Number: 002-23969

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

6193423

6260901

GVCH

06/27/2018 New data sheet.

*A

07/25/2018 Updated Package Diagram:

spec 002-23724 – Changed revision from ** to *A.

*B

6478873

GVCH

03/26/2019 Datasheet status changed from Preliminary to Final

Maximum Ratings: Updated latch-up current to 140 mA for Industrial and Mil-

itary Temperature

^{Thermal Resistance: Added}_JAand _JCvalues

Ordering Information: Removed STK14CA8C-3C35I part

Document Number: 002-23969 Rev. *B

Page 20 of 21

STK14CA8C-3

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

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Technical Support

Internet of Things

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including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

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liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

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Document Number: 002-23969 Rev. *B

Revised March 26, 2019

Page 21 of 21


型号：	STK14CA8C-35C35M
厂家：	Infineon
描述：	nvSRAM (non-volatile SRAM) 静态存储器
文件：	总21页 (文件大小：430K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STK14CA8C-35C35M [INFINEON]

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