TDA5212 [INFINEON]
ASK/FSK 915MHz Single Conversion Receiver; ASK / FSK 915MHz的单转换接收器
| 型号： | TDA5212 |
| 厂家： | 
Infineon |
| 描述： | ASK/FSK 915MHz Single Conversion Receiver |
| 文件： | 总51页 (文件大小：1194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
ASK/FSK 915MHz Single Conversion Receiver
TDA 5212 Version 1.1
Specification May 2003
preliminary
Revision History
Current Version: 1.1 as of 09.05.03
Previous Version: 1.0
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
5-12, 5-13
5-12, 5-13
Table 5-4, Table 5-5, Bill of Materials
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®,
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Edition 05.03
Published by Infineon Technologies AG,
Balanstraße 73,
81541 München
© Infineon Technologies AG May 2003.
All Rights Reserved.
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TDA 5212
preliminary
Product Info
Product Info
Package
General Description The IC is a very low power consump-
tion single chip FSK/ASK Superhet-
erodyne Receiver (SHR) for the re-
ceive frequency range between 910
and 920 MHz that is pin compatible to
the ASK Receiver TDA5202. The IC
offers a high level of integration and
needs only a few external compo-
nents. The device contains a low noise
amplifier (LNA), a double balanced
mixer, a fully integrated VCO, a PLL
synthesiser, a crystal oscillator, a lim-
iter with RSSI generator, a PLL FSK
demodulator, a data filter, a data com-
parator (slicer) and a peak detector.
Additionally there is a power down fea-
ture to save battery life.
Features
Low supply current (Is = 5.4 mA typ.
in FSK mode, Is = 4.8 mA typ. in
ASK mode)
Receive frequency range 910 to
920 MHz
Limiter with RSSI generation,
operating at 10.7 MHz
Supply voltage range 5 V ±10%
Power down mode with very low
supply current (90 nA typ.)
Selectable reference frequency
2nd order low pass data filter with
external capacitors
FSK and ASK demodulation capa-
bility
Data slicer with self-adjusting
threshold
Fully integrated VCO and PLL
Synthesiser
FSK sensitivity better than
-102 dBm over specified tempera-
ture range (- 40 to +85°C)
ASK sensitivity better than
-109 dBm over specified tempera-
ture range (- 40 to +85°C)
Application
Keyless Entry Systems
Remote Control Systems
Low Bitrate ISM-band Communica-
tion Systems
Ordering Information
Type
Ordering Code
Package
TDA 5212
P-TSSOP-28-1
samples available
Wireless Components
Product Info
Specification, May 2003
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-2
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2-2
2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3.1
3.2
3.3
3.4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3-9
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.6 FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.7 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-2
4.1
4.2
4.3
4.4
4.5
4.6
Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
4-5
4-6
4-7
4-8
4-8
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.7 Principle of the Precharge Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-2
5-2
5-3
5-4
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
5.3
5.4
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9
Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
6 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
i
2
Product Description
Contents of this Chapter
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5212
preliminary
Product Description
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne
Receiver (SHR) for receive frequencies between 910 and 920 MHz that is pin
compatible to the ASK Receiver TDA5202. The IC offers a high level of integra-
tion and needs only a few external components. The device contains a low
noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL
synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK
demodulator, a data filter, a data comparator (slicer) and a peak detector. Addi-
tionally there is a power down feature to save battery life.
2.2 Application
Keyless Entry Systems
Remote Control Systems
Low Bitrate ISM-band Communication Systems
2.3 Features
Low supply current (Is = 5.4 mA typ.FSK mode, 4.8 mA typ. ASK mode)
Supply voltage range 5V ±10%
Power down mode with very low supply current (90nA typ.)
FSK and ASK demodulation capability
Fully integrated VCO and PLL Synthesiser
RF input sensitivity ASK -112dBm typ. at 25°C, better than -109dBm over
complete specified operating temperature range (-40 to +85°C)
RF input sensitivity FSK -105dBm typ. at 25°C, better than -102dBm over
complete specified operating temperature range (-40 to +85°C)
Receive frequency range between 910 and 920 MHz
Selectable reference frequency
Limiter with RSSI generation, operating at 10.7MHz
2nd order low pass data filter with external capacitors
Data slicer with self-adjusting threshold
Wireless Components
2 - 2
Specification, May 2003
TDA 5212
preliminary
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2 - 3
Specification, May 2003
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
TDA 5212
preliminary
Functional Description
3.1 Pin Configuration
CRST1
VCC
LNI
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CRST2
PDW N
PDO
2
3
TAG C
AG ND
LNO
4
DATA
3VO UT
THRES
FFB
5
6
VCC
M I
7
TDA 5212
8
O PP
M IX
9
SLN
AG ND
FSEL
IFO
10
11
12
13
14
SLP
LIM X
LIM
DG ND
VDD
CSEL
M SEL
Pin_Configuration_5212_V1.0.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3 - 2
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No. Symbol
Equivalent I/O-Schematic
Function
1
CRST1
External Crystal Connector 1
4.15V
1
50uA
2
3
VCC
LNI
5V Supply
LNA Input
57uA
3
500uA
4k
1k
Wireless Components
3 - 3
Specification, May 2003
TDA 5212
preliminary
Functional Description
4
TAGC
AGC Time Constant Control
4.3V
3uA
4
1k
1.4uA
1.7V
5
6
AGND
LNO
Analogue Ground Return
LNA Output
5V
1k
6
7
8
VCC
MI
5V Supply
Mixer Input
1.7V
2k
2k
9
MIX
Complementary Mixer Input
8
9
400uA
10
11
AGND
BUF
Analogue Ground Return
Mixer Buffer Ground
Wireless Components
3 - 4
Specification, May 2003
TDA 5212
preliminary
Functional Description
12
IFO
10.7 MHz IF Mixer Output
300uA
2.2V
60
12
4.5k
13
14
DGND
VDD
Digital Ground Return
5V Supply (PLL Counter Cir-
cuitry)
15
MSEL
ASK/FSK Modulation Format
Selector
1.2V
3.6k
15
16
CSEL
7.xx or 14.xx MHz Quartz
Selector
1.2V
80k
16
Wireless Components
3 - 5
Specification, May 2003
TDA 5212
preliminary
Functional Description
17
18
LIM
Limiter Input
2.4V
15k
17
LIMX
Complementary Limiter Input
75uA
330
18
15k
19
SLP
Data Slicer Positive Input
15uA
100
3k
19
80µA
20
SLN
Data Slicer Negative Input
5uA
10k
20
Wireless Components
3 - 6
Specification, May 2003
TDA 5212
preliminary
Functional Description
21
22
23
24
OPP
OpAmp Noninverting Input
Data Filter Feedback Pin
AGC Threshold Input
5uA
200
21
FFB
5uA
100k
22
THRES
5uA
10k
23
3VOUT
3V Reference Output
24
20k
3.1V
Wireless Components
3 - 7
Specification, May 2003
TDA 5212
preliminary
Functional Description
25
DATA
Data Output
500
25
40k
26
PDO
Peak Detector Output
200
26
27
PDWN
Power Down Input
27
220k
220k
28
CRST2
External Crystal Connector 2
4.15V
28
50uA
Wireless Components
3 - 8
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.3 Functional Block Diagram
VCC
IF
Filter
MSEL
LNO
MI
MIX IFO
12
LIM
LIMX
FFB
OPP
SLP
SLN
6
8
9
17
18
15
21
19
20
22
LNI
3
4
LNA
RF
-
+
-
FSK
-
DATA
FSK
ASK
25
+
LIMITER
SLICER
PLL Demod
OP
+
-
+
TAGC
PEAK
DETECTOR
26 PDO
TDA 5212
OTA
THRES
23
24
UREF
3VOUT
AGC
ꢀ
CRYSTAL
OSC
BUF
VCO
: 128 / 64
Reference
DET
VCC
14
13
Bandgap
Loop
Filter
Reference
DGND
16
1
28
27
11
2,7
5,10
PDWN
VCC AGND
BUF
CSEL
Crystal
Functional_diagram_5212.wmf
Figure 3-2
Main Block Diagram
Wireless Components
3 - 9
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 910 to 920 MHz to the intermediate frequency (IF) at 10.7MHz with a
voltage gain of approximately 21dB. A low pass filter with a corner frequency of
20MHz is built on chip in order to suppress RF signals to appear at the IF output
( IFO pin). The IF output is internally consisting of an emitter follower that has
a source impedance of approximately 330 ꢀꢁto facilitate interfacing the pin
directly to a standard 10.7MHz ceramic filter without additional matching cir-
cuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The oscillator signal is fed both to the synthesiser divider chain and to
the downconverting mixer via a buffer amplifier. The BUF pin (Pin 11) has to be
tied to ground. No additional components are necessary. The loop filter is also
realised fully on-chip. High-side injection of the local oscillator has to be used
for the receive frequency band of 910 to 920 MHz, yielding local oscillator fre-
quencies in the region of 920 to 930 MHz. See also Section 4.4.
Wireless Components
3 - 10
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in
the 7 and 14MHz range as the overall division ratio of the PLL can be switched
between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States
CSEL
Crystal Frequency
7.xx MHz
Open
Shorted to ground
14.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80dB that has a bandpass-characteristic centred around
10.7MHz. It has an input impedance of 330 ꢀꢁto allow for easy interfacing to a
10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength
Indicator (RSSI) generator which produces a DC voltage that is directly propor-
tional to the input signal level as can be seen in Figure 4-2. This signal is used
to demodulate the ASK receive signal in the subsequent baseband circuitry and
to turn down the LNA gain by approximately 18dB in case the input signal
strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear
phase detector as is the output of the 10.7 MHz center frequency VCO. The
demodulator gain is typically 180µV/kHz. The passive loop filter output that is
comprised fully on chip is fed to both the VCO and the modulation format
switch.This signal is representing the demodulated signal. This switch is actu-
ally a switchable amplifier with an AC gain of 11 that is controlled by the MSEL
pin (Pin 15) as shown in the following table. This gain was chosen to facilitate
detection in the subsequent circuits.
Table 3-3 MSEL Pin Operating States
MSEL
Modulation Format
Open
ASK
FSK
Shorted to ground
Wireless Components
3 - 11
Specification, May 2003
TDA 5212
preliminary
Functional Description
The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC
offset produced by the demodulator in case of large frequency offsets of the IF
signal. The resulting frequency characteristic and details on the principle of
operation of the switch are described in Section 4.6. The demodulator circuit is
switched off in case of reception of ASK signals.
3.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kꢀꢁ on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of approximately 120kBaud. The maximum
achievable data rate also depends on the IF Filter bandwidth and the local oscil-
lator tolerance values. Both inputs are accessible. The output delivers a digital
data signal (CMOS-like levels) for the detector. The self-adjusting threshold on
pin 20 its generated by RC-term or peak detector depending on the baseband
coding scheme. The data slicer threshold generation alternatives are described
in more detail in Section 4.5.
3.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The input
is connected to the output of the RSSI-output of the Limiter, the output is con-
nected to the PDO pin (Pin 26 ). This output can be used as an indicator for the
received signal strength to use in wake-up circuits and as a reference for the
data slicer in ASK mode. The output current is typically 850µA, the leakage cur-
rent is typically 700nA. Note that the RSSI level is also output in case of FSK
mode.
Wireless Components
3 - 12
Specification, May 2003
TDA 5212
preliminary
Functional Description
3.4.10 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 90nA.
Table 3-4 PDWN Pin Operating States
PDWN
Operating State
Powerdown Mode
Receiver On
Open or tied to ground
Tied to Vs
Wireless Components
3 - 13
Specification, May 2003
4
Applications
Contents of this Chapter
4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8
4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
TDA 5212
preliminary
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is
shown.
R1
R2
U
threshold
23
Pins:
24
RSSI (0.8 - 2.8V)
20k
ꢀ
OTA
VCC
+3.1V
I
LNA
load
Gain control
vol tag e
RSSI > Uthreshold: Iload=4.2µA
RSSI < Uthreshold: Iload= -1.5µA
4
Uc :< 2.6V : Gain high
Uc :> 2.6V : Gain low
UC
C
U
= V - 0.7V
CC
Ucc mmianx= 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpe-
dance amplifier that is used to compare the received signal strength signal
(RSSI) generated by the Limiter with an externally provided threshold voltage
Uthres. As shown in the following figure the threshold voltage can have any
value between approximately 0.8 and 2.8V to provide a switching point within
the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage
can be generated by attaching a voltage divider between the 3VOUT pin (i.e.
Pin 24) which provides a temperature stable 3V output generated from the inter-
nal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is higher than Uthres, the OTA generates a positive current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charge an external capacitor which finally generates the LNA gain control volt-
age.
Wireless Components
4 - 2
Specification, May 2003
TDA 5212
preliminary
Applications
3
2.5
2
RSSI Level
1.5
1
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating sce-
nario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It should be noted that the output of the 3VOUT pin is capable of driving up to
50µA, but that the THRES pin input current is only in the region of 40nA. As the
current drawn out of the 3VOUT pin is directly related to the receiver power con-
sumption, the power divider resistors should have high impedance values. The
sum of R1 and R2 has to be 600kꢀ in order to yield 3V at the 3VOUT pin. R1
can thus be chosen as 240kꢀ, R2 as 360kꢀ to yield an overall 3VOUT output
current of 5µA1 and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the THRES, such
as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain
control voltage of the LNA due to the charging and discharging currents of the
OTA and thus is also responsible for the AGC time constant. As the charging
and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall
be chosen according to the data rate. According to measurements performed
at Infineon the capacitor value should be greater than 47nF.
1. note the 20kꢀ resistor in series with the 3.1V internal voltage source
Wireless Components
4 - 3
Specification, May 2003
TDA 5212
preliminary
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kꢀ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
C1
22
C2
21
Pins:
19
R
R
100k
100k
Filter_Design.wmf
Figure 4-3
(1)
Data Filter Design
(2)
b
2Q b
C1 = ----------------------
R2ꢀf3dB
C2 = ---------------------------
4QRꢀf3dB
with
b
Q = ------
a
(3)
the quality factor of the poles
where
in case of a Bessel filter
and thus
a = 1.3617, b = 0.618
Q = 0.577
and in case of a Butterworth filter
and thus
a = 1.141, b = 1
Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kꢀ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4 - 4
Specification, May 2003
TDA 5212
preliminary
Applications
4.3 Crystal Load Capacitance Calculation
The value of the capacitor necessary to achieve that the crystal oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
crystal specifications given by the crystal manufacturer.
CS
Pin 28
Input
Crystal
impedance
Z1-28
TDA5212
Pin 1
Quartz_load_5212.wmf
Figure 4-4
Determination of Series Capacitance Value for the Crystal Oscillator
Crystal specified with load capacitance
1
CS ꢁ
1
Cl
ꢀ 2ꢀ f X L
with Cl the load capacitance (refer to the crystal specification).
Examples:
7.2 MHz:
CL = 12 pF
CL = 12 pF
XL=500 ꢀ
CS = 9.5 pF
CS = 5.6 pF
14.5 MHz:
XL=1050 ꢀ
These values may be obtained in high accuracy by putting two capacitors in
series to the quartz, such as 18pF and 20pF in the 7.2MHz case and 18pF and
8.2pF in the 14.5MHz case.
Wireless Components
4 - 5
Specification, May 2003
TDA 5212
preliminary
Applications
4.4 Crystal Frequency Calculation
The local oscillator (UHF PLL) signal has to be high-side injected into the down-
converting mixer. Thus the crystal frequency is calculated by using the following
formula:
ƒQU = (ƒRF + 10.7) / r
with
ƒRF ....
ƒLO ....
ƒQU ....
receive frequency
local oscillator (PLL) frequency (ƒRF + 10.7)
crystal oscillator frequency
r
....
ratio of local oscillator (PLL) frequency and crystal
frequency as shown in the subsequent table.
Table 4-1 PLL Division Ratio Dependence on States of CSEL
CSEL
open
GND
Ratio r = (fLO/fQU)
128
64
This yields the following example:
CSEL tied to GND:
fQU
ꢀ
ꢀ
915MHz ꢁ10.7MHz / 64 ꢀ 14.4641 MHz
ꢁ
Wireless Components
4 - 6
Specification, May 2003
TDA 5212
preliminary
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated in two ways, depending on
the signal coding scheme used. In case of a signal coding scheme without DC
content such as Manchester coding the threshold can be generated using an
external R-C integrator as shown in the following . The cut-off frequency of the
R-C integrator has to be lower than the lowest frequency appearing in the data
signal. In order to keep distortion low, the minimum value for R is 20kꢀ.
R
C
data out
25
Pins:
19
20
Uthreshold
data
filter
data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in con-
nection with two resistors and one capacitor as shown in the following figure.
The component values are depending on the coding scheme and the protocol
used.
R
C
R
data out
25
Pins:
20
19
26
Uthreshold
peak detector
data slicer
data
filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4 - 7
Specification, May 2003
TDA 5212
preliminary
Applications
4.6 ASK/FSK Switch Functional Description
The TDA5211 is containing an ASK/FSK switch which can be controlled via Pin
15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are
having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of the
FSK amplifier in order to achieve an appropriate demodulation gain character-
istic. In order to compensate for the DC-offset generated especially in case of
the FSK PLL demodulator there is a feedback connection between the thresh-
old voltage of the bit slicer comparator (Pin 20) to the negative input of the FSK
switch amplifier. This is shown in the figure below:
MSEL
15
RSSI (ASK signal)
ASK/FSK Switch
Data Filter
R2=100k
DATA Out
25
R1=100k
-
FSK PLL Demodulator
ASK
FSK
+
+
-
v = 1
Comp
+
-
0.18 mV/kHz
R3=300k
typ. 2 V
1.5 V......2.5 V
R4=30k
FFB
OPP SLP
SLN
22
21
19
20
ASK mode : v=1
FSK mode : v=11
R
C1
C2
C
ask_fsk_datapath.WMF
Figure 4-7
ASK/FSK mode datapath
4.6.1 FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown
above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is
determined by the external RC-combination. The upper cutoff frequency f3 is
determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 180µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting
dynamic gain of this circuit is 2mV/kHz within the bandpass. The gain for the DC
Wireless Components
4 - 8
Specification, May 2003
TDA 5212
preliminary
Applications
content of FSK signal remains at 180µV/kHz. The cutoff frequencies of the
bandpass have to be chosen such that the spectrum of the data signal is influ-
enced in an acceptable amount.
In case that the user data is containing long sequences of logical zeros the
effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset
voltage inherent at the negative input of the slicer comparator (Pin20) is used.
The comparator has no hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises
the voltage appearing at pin 20 (e.g. 1mV with R = 100kꢀ). In order to obtain
benefit of this asymmetrical offset for the demodulation of long zeros the lower
of the two FSK frequencies should be chosen in the transmitter as the zero-
symbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v
v-3dB
20dB/dec
-40dB/dec
3dB
0dB
f
DC
f1
f2
f3
0.18mV/kHz
2mV/kHz
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
1
f1 ꢃ
Rꢀ330kꢁ
2ꢀ
ꢀC
R ꢂ 330kꢁ
Wireless Components
4 - 9
Specification, May 2003
TDA 5212
preliminary
Applications
f2 ꢁ vꢀ f1 ꢁ11ꢀ f1
f3 ꢀ f3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.
Example:
R = 100kꢀ
C = 47nF
This leads to f1 = 44Hz
and
f2 = 485Hz
4.6.2 ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charac-
tersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff
frequency is determined by the external capacitors C12 and C14 and the inter-
nal 100k resistors as described in Section 4.2
0dB
-3dB
-40dB/dec
f
f3dB
freq_ask.WMF
Figure 4-9
Frequency charcteristic in case of ASK mode
Wireless Components
4 - 10
Specification, May 2003
TDA 5212
preliminary
Applications
4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network
as described in Section 4.5 it is necessary to use large values for the capacitor
C attached to the SLN pin (pin 20) in order to achieve long time constants. This
results also from the fact that the choice of the value for R connected between
the SLP and SLN pins (pins 19 and 20) is limited by the 330kꢀ resistor appear-
ing in parallel to R as can be seen in Figure 4-6. Apart from this a resistor value
of 100kꢀ leads to a voltage offset of 1mv at the comparator input as described
in Section 4.6.1. The resulting startup time constant ꢂ can be calculated with:
1
ꢂ = (R // 330kꢀ) · C
1
In case R is chosen to be 100kꢀ and C is chosen as 47nF this leads to
ꢂ = (100kꢀ // 330kꢀ) · 47nF = 77kꢀ · 47nF = 3.6ms
1
When the device is turned on this time constant dominates the time necessary
for the device to be able to demodulate data properly. In the powerdown mode
the capacitor is only discharged by leakage currents.
In order to reduce the turn-on time in the presence of large values of C a pre-
charge circuit was included in the TDA5210 as shown in the following figure.
C2
R1+R2=600k
R1
R2
C
R
U
thres hold
20
19
24
23
Iload
Uc
ASK/FSK Switch
Uc>Us Uc<Us
DataFilter
-
U2
+
0 / 240uA
OTA
Us
U2<2.4V : I=240uA
U2>2.4V: I=0
-
20k
+2.4V
+3.1V
precharge.WMF
Figure 4-10 Principle of the precharge circuit
Wireless Components
4 - 11
Specification, May 2003
TDA 5212
preliminary
Applications
This circuit charges the capacitor C with an inrush current Iload of 240µA for a
duration of T2 until the voltage Uc appearing on the capacitor is equal to the volt-
age Us at the input of the data filter. This voltage is limited to 2.5V. As soon as
these voltages are equal or the duration T2 is exceeded the precharge circuit is
disabled.
ꢂ is the time constant of the charging process of C which can be calculated as
2
ꢂ Wꢁ20kꢀ · C2
2
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can
then be calculated according to the following formula:
ꢂ
ꢁ
.
/
1
ꢁ
/
T2 ꢄ ꢀ ln
W ꢀ ꢀ1.6
2
2
2.4V
3V
ꢁ
ꢁ
/
/
0
1 ꢃ
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V
2.4V
T2
2
e-fkt1.WMF
Figure 4-11 Voltage appearing on C2 during precharging process
The voltage appearing on the capacitor C connected to pin 20 is shown in the
following figure. It can be seen that due to the fact that it is charged by a con-
stant current source it exhibits is a linear increase in voltage which is limited to
Wireless Components
4 - 12
Specification, May 2003
TDA 5212
preliminary
Applications
USmax = 2.5V which is also the approximate operating point of the data filter
input. The time constant appearing in this case can be denoted as T3, which
can be calculated with
U
Smax ꢁ C
2,5V
240ꢂA
T3 = ----------------------- = ---------------- ꢁ C
240ꢂA
Uc
Us
T3
e-Fkt2.WMF
Figure 4-12 Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 20nF and C = 47nF yields
ꢂ = 0.4ms
2
T2 = 0.64ms
T3 = 0.49ms
This means that in this case the inrush current could flow for a duration of
0.64ms but stops already after 0.49ms when the USmax limit has been reached.
T3 should always be chosen to be shorter than T2.
It has to be noted finally that during the turn-on duration T2 the overall device
power consumption is increased by the 240µA needed to charge C.
Wireless Components
4 - 13
Specification, May 2003
TDA 5212
preliminary
Applications
The precharge circuit may be disabled if C2 is not equipped. This yields a T2
close to zero. Note that the sum of R4 and R5 has to be 600kꢀ in order to pro-
duce 3V at the THRES pin as this voltage is internally used also as the refer-
ence for the FSK demodulator.
Wireless Components
4 - 14
Specification, May 2003
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
TDA 5212
preliminary
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
=-40°C ... + 85°C
Limit Values
AMB
#
Parameter
Symbol
Unit
Remarks
min
-0.3
max
5.5
1
2
3
4
5
Supply Voltage
Vs
Tj
V
°C
Junction Temperature
Storage Temperature
Thermal Resistance
ESD integrity, all pins
-40
-40
+150
+125
114
+1
Ts
°C
RthJA
VESD
K/W
kV
-1
HBM
according to
MIL STD
883D,
method
3015.7
Wireless Components
5 - 2
Specification, May 2003
TDA 5212
preliminary
Reference
5.1.2 Operating Range
Within the operating range the IC operates as explained in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature T
= -40°C ... + 85°C
AMB
#
1
2
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
max
Supply Current
I
6
mA
mA
f
f
= 915MHz, FSK Mode
= 915MHz, ASK Mode
SF
RF
RF
I
5.4
SA
Receiver Input Level
ASK
FSK, frequ. dev. ± 50kHz
@ source impedance 50ꢀ,
RFin
-109
-102
-13
-13
dBm BER 2E-3, average power
dBm level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth
3
4
6
LNI Input Frequency
MI/X Input Frequency
fRF
fMI
910
910
920
920
920
930
MHz
MHz
MHz
UHF Local Oscillator Fre-
quency Range
fLO
7
8
9
3dB IF Frequency Range
Powerdown Mode On
Powerdown Mode Off
fIF -3dB
PWDNON
PWDNOFF
VTHRES
5
0
23
MHz
V
0.8
2
V
V
S
S
10 Gain Control Voltage,
LNA high gain state
2.8
V
V
11 Gain Control Voltage,
LNA low gain state
VTHRES
0
0.7V
V
This value is guaranteed by design.
Wireless Components
5 - 3
Specification, May 2003
TDA 5212
preliminary
Reference
5.1.3 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the spec-
ified voltage and ambient temperature range. Typical characteristics are the
median of the production. The device performance parameters marked with
were measured on an Infineon evaluation board as desdribed in Section 5.2
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
#
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
typ
max
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
90
120
5.7
nA
Pin 27 (PDWN)
open or tied to 0 V
2
Supply current, device
operating in FSK mode
I
5.4
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) tied to
GND
SF
3
Supply current, device
operating in ASK mode
I
4.8
5.1
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
SA
LNA
Signal Input LNI (PIN 3), V
> 2.8V, high gain mode
THRES
1
Average Power Level
at BER = 2E-3
RFin
-112
dBm Manchester
encoded datarate
(Sensitivity) ASK
4kBit, 280kHz IF
Bandwidth
2
Average Power Level
at BER = 2E-3
RFin
-105
dBm Manchester enc.
datarate 4kBit,
(Sensitivity) FSK
280kHz IF Bandw.,
± 50kHz pk. dev.
3
4
5
Input impedance,
S
0.717 / -78.4 deg
t.b.d.
11 LNA
f
= 915 MHz
RF
Input level @ 1dB C.P.
fRF=915 MHz
P1dB
dBm
LNA
Input 3rd order intercept
LNA
IIP3
LO
t.b.d.
dBm fin = 914 & 916MHz
point f = 915 MHz
RF
6
LO signal feedthrough at
antenna port
t.b.d.
dBm
LNI
Signal Output LNO (PIN 6), V
> 2.8V, high gain mode
THRES
1
2
Gain f = 915 MHz
RF
S
1.401 / 98.4 deg
0.869 / -25.7 deg
21 LNA
22 LNA
Output impedance,
S
f
= 915 MHz
RF
Wireless Components
5 - 4
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
#
Parameter
Symbol
Limit Values
typ
Unit Test Conditions
L
Item
min
max
3
4
Voltage Gain Antenna to
G
t.b.d.
dB
dB
AntMI
MI f = 915 MHz
RF
Noise Figure
NF
t.b.d.
LNA
Signal Input LNI, V
= GND, low gain mode
THRES
1
Input impedance,
= 915 MHz
S
0.753 / -86.26 deg
11 LNA
f
RF
2
Input level @ 1dB C. P.
= 915 MHz
P1dB
t.b.d.
dBm
LNA
f
RF
Signal Input LNI, V
= GND, low gain mode
THRES
Input 3rd order intercept
LNA
3
IIP3
t.b.d.
dBm fin = 914 & 916MHz
point f = 915 MHz
RF
Signal Output LNO, V
= GND, low gain mode
THRES
1
2
Gain f = 915 MHz
S
0.174 / 107.4 deg
RF
21 LNA
22 LNA
Output impedance,
S
0.868 / -28.1 deg
f
= 915 MHz
RF
3
Voltage Gain Antenna to
MI f = 915 MHz
G
t.b.d.
dB
AntMI
RF
Signal 3VOUT (PIN 24)
1
2
Output voltage
Current out
V
I
2.9
3
3.1
V
I3Vout = 5µA
3VOUT
50
µA
3VOUT
Signal THRES (PIN 23)
1
2
3
4
Input Voltage range
LNA low gain mode
LNA high gain mode
Current in
V
0
0
V -1V
S
V
V
see Section 4.1
THRES
THRES
THRES
V
V
2.8
3
5
V
S
V
or shorted to Pin 24
ITHRES_in
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
3.8
1
4.2
1.5
4.8
2
µA
µA
RSSI > V
RSSI < V
THRES
2
Current in,
I
TAGC_in
THRES
LNA high gain state
MIXER
Signal Input MI/MIX (PINS 8/9)
1
Input impedance,
= 915 MHz
S
0.912 / -30.13 deg
-25
11 MIX
f
RF
Input 3rd order intercept
point
MIX
2
IIP3
dBm
Wireless Components
5 - 5
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
typ
max
Signal Output IFO (PIN 12)
1
2
Output impedance
Z
330
ꢀ
IFO
Conversion Voltage Gain
G
t.b.d.
dB
MIX
f
=869 MHz
RF
3
4
Noise Figure, SSB
(~DSB NF+3dB)
NF
t.b.d.
t.b.d.
dB
dB
MIX
RF to IF isolation
A
RF-IF
LIMITER
Signal Input LIM/X (PINS 17/18)
1
2
3
4
Input Impedance
RSSI dynamic range
RSSI linearity
Z
264
60
330
396
80
ꢀ
dB
LIM
DR
RSSI
LIN
dB
±1
RSSI
Operating frequency (3dB
points)
f
5
10.7
23
MHz
LIM
DATA FILTER
1
Useable bandwidth
BW
100
kHz
BB
FILT
SLICER
Signal Output DATA (PIN 25)
1
Useable bandwith
BW
100
20
kHz
pF
BB
SLIC
2
Capacitive loading of out-
put
C
max
SLIC
3
4
5
6
LOW output voltage
HIGH output voltage
Output current
V
0
0.1
V
V
SLIC_L
VS-1.1V
600
VS-1V
750
33
VS-0.9V
900
V
SLIC_H
I
µA
µA
SLIC_out
Leakage current
I
30
36
SLIC_in
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
2
3
4
LOW output voltage
HIGH output voltage
Load current
V
V
0
0.1
3.1
V
V
SLIC_L
2.9
700
580
3
SLIC_H
I
850
700
1000
820
µA
nA
load
Leakage current
I
leakage
Wireless Components
5 - 6
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
typ
max
CRYSTAL OSCILLATOR
Signals CRSTL1, CRISTL 2, (PINS 1/28)
1
Operating frequency
f
6
15
MHz fundamental mode,
series resonance
CRSTL
- 860 +
j500
2
Input Impedance
@ ~7.2MHz
Z
ꢀ
1-28
- 550 +
j1050
3
4
5
Input Impedance
@ ~14.5MHz
Z
ꢀ
1-28
Serial Capacity
@ ~7.2MHz
C
=C1
=C1
9.5
5.6
pF
pF
S7
Serial Capacity
@ ~14.5MHz
C
S14
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
2
FSK Mode
ASK Mode
V
1.4
0
4
V
V
or open
MSEL
V
0.2
MSEL
FSK DEMODULATOR
1
Demodulation Gain
G
180
200
220
µV/
FMDEM
kHz
2
Useable IF Bandwidth
BW
10.2
10.7
11.2
MHz
IFPLL
POWER DOWN MODE
Signal PDWN (PIN 27)
1
2
3
4
Powerdown Mode On
Powerdown Mode Off
Input bias current PDWN
PWDNON
0
0.8
V
V
PWDN
Off
2.8
V
S
I
t.b.d.
µA
ms
PDWN
note: startup - time is
also dependent on data
filter and data slicer time
constants
Start-up Time until valid IF
signal is detected
T
1
4
SU
PLL DIVIDER
Signal CSEL (PIN 16)
1
f
range 7.xxMHz
V
1.4
V
or open
CRSTL
CSEL
Wireless Components
5 - 7
Specification, May 2003
TDA 5212
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions
L
Item
min
0
typ
max
0.2
2
3
f
range 14.xxMHz
V
I
V
CRSTL
CSEL
Input bias current CSEL
Measured only in lab.
5
µA
CSEL tied to GND
CSEL
Wireless Components
5 - 8
Specification, May 2003
TDA 5212
preliminary
Reference
5.2 Test Circuit
The device performance parameters marked with in Section 5.1.3 were mea-
sured on an Infineon evaluation board.
Test_circuit.wmf
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5 - 9
Specification, May 2003
TDA 5212
preliminary
Reference
5.3 Test Board Layouts
Figure 5-2
Top Side of the Evaluation Board
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5 - 10
Specification, May 2003
TDA 5212
preliminary
Reference
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 11
Specification, May 2003
TDA 5212
preliminary
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5212 at
915 MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials
Ref
Value
100kꢀ
100kꢀ
820kꢀ
240kꢀ
360kꢀ
10kꢀ
3.3nH
3.9nH
1pF
Specification
0805, ± 5%
R1
R2
0805, ± 5%
R3
0805, ± 5%
R4
0805, ± 5%
R5
0805, ± 5%
R6
0805, ± 5%
L1
Toko, PTL2012-F15N0G
0805,COG, ± 2%
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
0805, COG, ± 5%
1206, X7R, ± 10%
Toko, PTL2012-F15N0G
0805, COG, ± 5%
0805, COG, ± 5%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, X7R, ± 10%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, COG, ± 1%
0805, COG, ± 0.25pF
Jauch Q 14.129690-S1
Murata
L2
C1
C2
3.3pF
4.7pF
100pF
47nF
C3
C4
C5
C6
3.3pF
100pF
22pF
C7
C8
C9
100pF
10nF
C10
C11
C12
C13
C14
C15
C16
C17
10nF
220pF
47nF
470pF
47nF
8.2pF
18pF
Q1
Q2
14.129690MHz
SFE10.7MA5-A
142-0701-801
STL_2POL
X2, X3
X1, X4, S1, S5
S4
Johnson
2-pole pin connector
3-pole pin connector, or not equipped
Infineon
STL_3POL
IC1
TDA 5212
Wireless Components
5 - 12
Specification, May 2003
TDA 5212
preliminary
Reference
The following components are necessary in addition to the above mentioned
ones for evaluation of the TDA5212 in conjunction with a Microchip HCS515
decoder.
Table 5-5 Bill of Materials Addendum
Ref
Value
22kꢀ
Specification
0805, ± 5%
0805, ± 5%
0805, ± 5%
0805, ± 5%
0805, ± 5%
1206, X7R, ± 10%
1206, X7R, ± 10%
Microchip
R21
R22
R23
R24
R25
C21
C22
IC2
T1
10kꢀ
22kꢀ
820kꢀ
560kꢀ
100nF
100nF
HCS512
BC 847B
LS T670-JL
Infineon
D1
Infineon
Wireless Components
5 - 13
Specification, May 2003
TDA 5212
preliminary
Reference
Wireless Components
5 - 14
Specification, May 2003
TDA 5212
preliminary
List of Figures
6
List of Figures
Figure 2-1 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1 LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-2 RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-4 Determination of Series Capacitance Value for the Crystal Oscillator . . . . . . . . . . . . .
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . .
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . .
Figure 4-7 ASK/FSK mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-8 Frequency characterstic in case of FSK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
3-2
3-9
4-2
4-3
4-4
4-5
4-7
4-7
4-8
4-9
Figure 4-9 Frequency charcteristic in case of ASK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 4-10 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Figure 4-11 Voltage appearing on C2 during precharging process . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Figure 4-12 Voltage transient on capacitor C attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9
Figure 5-2 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Wireless Components
List of Figures - i
Specification, May 2003
TDA 5212
preliminary
List of Tables
7
List of Tables
Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
Table 3-2 CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Table 3-3 MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Table 3-4 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C . . . . . . . . .
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C . . . . . . . . . . . . . . . . .
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . .
5-2
5-3
5-4
Table 5-4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5-5 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Wireless Components
List of Tables - i
Specification, May 2003
相关型号：
TDA5235
Enhanced Sensitivity Double-Configuration Receiver with Digital Baseband Processing
INFINEON
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