TLE4473GV52 [INFINEON]
Dual Low Drop Voltage Regulator; 双路低压差稳压器型号: | TLE4473GV52 |
厂家: | Infineon |
描述: | Dual Low Drop Voltage Regulator |
文件: | 总15页 (文件大小:653K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual Low Drop Voltage Regulator
TLE 4473 GV53
TLE 4473 GV52
Features
• Output 1: 300 mA, 3.3 V ( 3%) or 2.6 V ( 3%)
• Output 2: 180 mA, 5 V ( 2%)
• Low quiescent current consumption
• Disable function separately for both outputs
• Wide operation range: up to 42 V
• Very low dropout voltage
P-DSO-12-2, -3, -6
• 2 independent reset circuits
• Watchdog
• Output protected against short circuit
• Wide temperature range: -40 °C to 150 °C
• Overtemperature protection
• Overload protection
Functional Description
The TLE 4473 is a monolithic integrated voltage regulator with two very low-drop
outputs, Q1 for loads up to 300 mA and Q2 providing a maximum of 180 mA. An input
voltage in the range of 5.6 V ≤ VI ≤ 45 V is transformed to VQ2 = 5.0 V ( 2%) and
VQ1 = 3.3 V 3% (TLE 4473 GV53) or VQ1 = 2.6 V 3% (TLE 4473 GV52). The device is
also available with dual 5 V output voltage, please refer to the TLE 4473 GV55 data
sheet. Two inhibit pins allow a flexible power management. Both outputs can
independently be enabled or disabled. Thus the current consumption of the application
can be reduced to a minimum. The quiescent current of the TLE 4473 with both outputs
disabled is < 1 µA. The TLE 4473 is designed to supply microprocessor systems and
sensors under the severe conditions of automotive applications and is therefore
equipped with additional protection functions against overload, short circuit and
overtemperature.
The device operates in the wide junction temperature range of -40 °C to 150 °C.
Type
Ordering Code
Q67007-A9668
Q67007-A9683
Package
TLE 4473 GV53
TLE 4473 GV52
P-DSO-12-6
P-DSO-12-6
Data Sheet
1
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
The low drop regulator features a reset with adjustable power on delay for each of the
outputs. In addition the output for the microcontroller supply comes up with a watchdog
in order to supervise a microcontroller.
TLE 4473 GV53 / TLE 4473 GV52
e. g. µC I/O
Q2
4
2
7
I
VBat
or Sensor
Supply
10
µF
Overtemperature
Shutdown
4.7 kΩ
Current and
Saturation
Control,
Bandgap
RO2
Reset
Overcurrent
Protection
Reference
Generator
?1
D2 10
9
INH2
Inhibit
µC
100 nF
Q1
5
µC Core
Supply
22 µF
or
10 µF
4.7 kΩ
Current and
Saturation
Control,
RO1
WI
3
1
Reset
µC
Generator
Reset
Overcurrent
Protection
Watchdog
(from µC)
8
INH1
Watchdog
Inhibit
Ignition
D1 11
100 nF
6, 12
GND
AEB03507.VSD
Figure 1
Block Diagram with Typical External Components
Data Sheet
2
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Reset and Watchdog Behaviour:
The reset output RO1 is in high-state if the voltage on the delay capacitor CD1 is greater
or equal VDL1. The delay capacitor CD1 is charged with the current IDC1 for output voltages
greater than the reset threshold VRT1. If the output voltage drops below VRT1 (“reset
condition”), the delay capacitor CD1 will be discharged rapidly. If VD1 reaches VDL1, the
reset output RO1 is set to low.
At power-on, the charging process of CD1 starts from 0 V, which leads to the equation
CD1 × VDU1
tD, on = ----------------------------
(1)
IDC1
for the power-on reset delay time.
When the voltage at the delay capacitor has reached VDU1 and RO1 was set to high, the
watchdog circuit is enabled and discharges CD1 with the constant current IDD1
.
If there is no rising edge observed at the watchdog input, CD1 will be discharged down to
VDL1, where the reset output RO1 will be set to low and CD1 will be charged again with
the current IDC1 until VD1 reaches VDU1 and reset will be set high again.
If a watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period, CD1 is charged again and the reset output stays high. After VD1 has reached VDU1
,
the periodical cycle starts again.
The watchdog timing is shown in Figure 2. The maximum duration between two
watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher
capacitances on pin D1 result in larger watchdog trigger time:
TWI,tr
= 0.42 ms/nF × CD1
(2)
max
If the output voltage Q2 decreases below VRT2 , the external capacitor CD2 is discharged.
When the voltage at this capacitor drops below VDL2, a reset signal is generated at pin
11 (RO2), i.e. the reset output is set to low-level. If the output voltage rises above the
reset threshold, CD2 will be charged with the constant current IDC2. After the power-on-
reset time, the voltage at the capacitor reaches VDU2 and the reset output will be set to
high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of CD2 using Equation (1) analogous for Q2.
Data Sheet
3
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
VW
Ι
t
t
t
t
t
V
Ι
VQ
TWD, p
VD1
TWI, tr
VDU1
VDL1
tWD, L
VWO
(VDU1 - VDL1
)
(VDU1
-
VDL1) (Ι DC1
Ι DC1 Ι DD1
+
Ι DD1
)
(VDU1 - VDL1)
TWI, tr
=
CD1
;
TWD, p
=
CD1
;
tWD, L
=
CD1
Ι DD1
x
Ι DC1
AED03099_4473gv53
Figure 2
Watchdog Timing Schedule
Data Sheet
4
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
P-DSO-12-6
WI
RO2
RO1
Q2
1
2
3
4
5
6
12
11
10
9
GND
D1
D2
INH2
INH1
I
Q1
8
N.C.
7
AEP03318_4473gv53.VSD
Pin 6 and heat slug should be connected to GND
Figure 3
Table 1
Pin Configuration TLE 4473 GV53, TLE 4473 GV52 (top view)
Pin Definitions and Functions (TLE 4473 GV53, TLE 4473 GV52)
Pin No. Symbol Function
1
WI
Watchdog input; input for watchdog pulses, positive edge
triggered
2
3
4
RO2
RO1
Q2
Reset output for Q2; open collector output
Reset and watchdog output for Q1; open collector output
Output voltage 2 (5 V); block to GND with a capacitor CQ2 ≥ 22 µF,
ESR < 5 Ω at 10 kHz or CQ2 ≥ 10 µF, ESR < 4 Ω at 10 kHz
5
Q1
Output voltage 1 (3.3 V/2.6 V); block to GND with a capacitor
CQ1 ≥ 10 µF, ESR < 5 Ω at 10 kHz
6
7
N.C.
I
Not connected; connect to GND
Input voltage; block to GND directly at the IC with a ceramic
capacitor.
8
INH1
INH2
D2
Inhibit input 1; low level at INH2 and INH1 disables Q2 and Q1
Inhibit input 2; low level disables Q2
9
10
11
Reset Delay 2; connect a capacitor to set reset delay for Q2
D1
Reset Delay 1; connect a capacitor to GND to set reset delay and
watchdog timing for Q1
12
GND
Ground
Heatsink N. C.
Not connected; connect to GND
Data Sheet
5
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Table 2
Absolute Maximum Ratings
-40 °C < Tj < 150 °C
Parameter
Symbol Limit Values Unit
Remarks
Min.
Max.
Input I
Voltage
VI
II
-42
–
45
–
V
–
Current
mA
Internally limited
Stand-by Output Q2
Voltage
VQ2
IQ2
-0.3
–
18
–
V
–
Current
mA
Internally limited
Main Output Q1
Voltage
VQ1
IQ1
-0.3
–
18
–
V
–
Current
mA
Internally limited
Inhibit Input INH1
Voltage
VINH1
IINH1
-42
-2
45
2
V
–
–
Current
mA
Inhibit Input INH2
Voltage
VINH2
IINH2
-42
-2
45
2
V
–
–
Current
mA
Reset Output RO1
Voltage
VRO1
IRO1
-0.3
–
18
–
V
–
Current
mA
Internally limited
Reset Output RO2
Voltage
VRO2
IRO2
-0.3
–
18
–
V
–
Current
mA
Internally limited
Reset Delay D1
Voltage
VD1
ID1
-0.3
-5
7
5
V
–
–
Current
mA
Reset Delay D2
Voltage
VD
ID
-0.3
-5
7
5
V
–
–
Current
mA
Data Sheet
6
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Table 2
Absolute Maximum Ratings (cont’d)
-40 °C < Tj < 150 °C
Parameter
Symbol Limit Values Unit
Remarks
Min.
Max.
Watchdog Input WI
Voltage
VRADJ
IRADJ
-0.3
-5
7
5
V
–
–
Current
mA
Temperatures
Junction temperature
Storage temperature
ESD Protection
Tj
-40
-50
150
150
°C
°C
–
–
Tstg
Electrostatic Discharge
Voltage
VESD
–2
2
kV
Human Body Model
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
Data Sheet
7
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Table 3
Operating Range
Symbol Limit Values Unit
Parameter
Remarks
Min.
5.6
Max.
42
Input voltage
VI
Tj
V
Q1 & Q2
4.5
42
V
only Q1 regulating
–
Junction temperature
-40
150
°C
Thermal Resistances P-DSO-12-6
Junction pin
Rthj-pin
–
–
3
K/W
K/W
–
Junction ambient
Rthj-a
Rthj-a
Rthj-a
Rthj-a
115
PCB Heat Sink
Area 0 mm2 1)
Junction ambient
Junction ambient
Junction ambient
–
–
–
100
60
K/W
K/W
K/W
PCB Heat Sink
Area 100 mm2 1)
PCB Heat Sink
Area 300 mm2
1)
48
PCB Heat Sink
Area 600 mm2 1)
1) Package mounted on PCB 80 × 80 × 1.5 mm3; 35 µ Cu; 5 µ Sn; zero airflow.
Note: In the operating range the functions given in the circuit description are fulfilled.
Integrated protection functions are designed to prevent IC destruction under fault
conditions. Protection functions are not designed for repetitive operation.
Data Sheet
8
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Electrical Characteristics
VI1 =13.5 V; VINH1 =VINH2= 5V; – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
REGULATOR 2:
Output Q2
Output voltage
VQ2
IQ2
4.90 5.0
200 300
5.10
600
600
V
1 mA < IQ2< 180 mA;
6 V < VI < 28 V
Output current
limitation
mA VQ2 = 4.5 V
Output drop voltage; VDRQ2
DRQ2 = VI2 – VQ2
–
300
mV IQ2 = 100 mA; 1)
V
Load regulation
Line regulation
∆VQ2,Lo
∆VQ2,Li
–
–
15
5
50
20
mV 1 mA < IQ2 < 200 mA;
mV IQ2 = 1 mA;
6 V < VI < 28 V
PSRR
Power supply ripple
rejection
–
65
–
dB
fr = 100 Hz;
Vr = 1 Vpp
Current Consumption
Quiescent current;
stand-by
Iq = II – IQ2
Iq
–
–
–
–
165
205
180
210
µA
µA
µA
µA
TLE 4473 GV52;
IQ2 = 500 µA; Tj = 25 °C;
V
INH1 < VINH1 OFF (Q1 off)
TLE 4473 GV52;
IQ2= 500 µA; Tj = 85 °C;
VINH1 < VINH1 OFF (Q1 off)
TLE 4473 GV53;
IQ2 = 500 µA; Tj = 25 °C;
V
INH1 < VINH1 OFF (Q1 off)
TLE 4473 GV53;
IQ2= 500 µA; Tj = 85 °C;
VINH1 < VINH1 OFF (Q1 off)
–
235
µA
IQ2 = 500 µA;
VINH1 < VINH1 OFF (Q1 off)
Data Sheet
9
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Electrical Characteristics (cont’d)
VI1 =13.5 V; VINH1 =VINH2= 5V; – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Current Consumption (cont’d)
Quiescent current;
stand-by
Iq
5
mA IQ2 = 100 mA;
VINH1 < VINH1 OFF(Q1 off)
Iq = II – IQ2
Quiescent current;
inhibited
Iq
–
–
1
µA
VINH1=VINH2= 0V;
TJ < 85°C
Inhibit Input INH2
Turn-on Voltage
Turn-off Voltage
H-input current
L-input current
VINH2 ON
–
–
2.3
–
V
VQ2 on
VQ2 off
VINH2 OFF 0.8
–
V
IINH2 ON
– 1
– 1
0.5
0.1
3
µA
µA
VINH2 = 5 V
IINH2 OFF
1
0 V < VINH2 < 0.8 V
Reset Timing D2
Charge current
IDC2
5.0
1.6
9.0
1.8
13.0 µA
VD2 = 0.7 V
Upper timing
threshold
VDU2
2.2
V
–
Lower timing
threshold
VDL2
0.3
0.45 0.6
V
–
Saturation Voltage
Reset delay time
VD2,SAT
TRD2
100
mV VQ2 < VRT2
12
–
20
28
10
ms
CD2 = 100 nF
CD2 = 100 nF
Reset reaction time Trr
µs
Data Sheet
10
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Electrical Characteristics (cont’d)
VI1 =13.5 V; VINH1 =VINH2= 5V; – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Reset Output RO2
Reset switching
threshold
VRT2
4.5
–
4.65 4.8
1.4
V
–
Reset output current IRO2
–
mA Collector current of RO1,
power good, reset still
delayed.
VQ2=5V, VD2=0V,VRO2=0.3V
Reset output low
voltage
VRO2L
–
0.15 0.3
V
V
VQ2 ≥ 1 V, VD2=0V,
RO2= 0.5mA
I
Reset high voltage VRO2H
4.5
–
–
RRO2,ext=4.7kΩ
REGULATOR 1:
Output Q1
Output voltage
VQ12
VQ12
IQ1
3.20 3.3
3.40
V
V
TLE 4473 GV53
1 mA < IQ1< 300 mA;
4.5 V < VI < 28 V
Output voltage
2.52 2.60 2.68
TLE 4473 GV52
1 mA < IQ1< 300 mA;
4.5 V < VI < 28 V
Output current
limitation
350 500
600
mA VQ1 = 3.0 V
(TLE 4473 GV53);
VQ1 = 2.3 V
(TLE 4473 GV52)
Load regulation
Line regulation
∆VQ1,Lo
∆VQ1,Li
–
–
5
5
50
20
mV 5 mA < IQ1 < 300 mA;
mV IQ1 = 5 mA;
6 V < VI< 28 V
Power-Supply-
Ripple-Rejection
–
65
–
dB
fr = 100 Hz;
Vr = 1Vpp
PSRR
Data Sheet
11
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Electrical Characteristics (cont’d)
VI1 =13.5 V; VINH1 =VINH2= 5V; – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Current Consumption
Quiescent current;
Iq = II – IQ1– IQ2
Iq
–
–
–
–
200
210
7
265
280
20
µA
µA
TLE 4473 GV52;
IQ1 = 500 µA;
Q1 on; Q2 off; Tj < 85°C
TLE 4473 GV53;
IQ1 = 500 µA;
Q1 on; Q2 off; Tj < 85°C
mA IQ1 = 300 mA
IQ2 = 500 µA,
VQ1 & VQ2 on
250
500
µA
IQ2 = IQ1 = 500 µA;
VQ1 & VQ2 on
Inhibit Input INH1
Turn-on Voltage
Turn-off Voltage
H-input current
L-input current
VINH1 ON
–
–
2.3
–
V
VQ1 on
VINH1 OFF 0.8
–
V
VQ1 off
IINH1 ON
– 1
– 1
0.5
0.1
3
µA
µA
VINH1= 5 V
0 V < VINH1< 0.8 V
IINH1 OFF
1
Watchdog and Reset Timing D1
Charge current
IDC1
IDD1
VDU1
3.0
1.1
0.7
7.0
1.5
1.1
11.0 µA
VD1 = 0.7 V
VD1 = 0.7 V
–
Discharge current
3.7
1.6
µA
Upper timing
threshold
V
Lower timing
threshold
VDL1
0.2
0.35 0.6
12
V
–
Data Sheet
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Electrical Characteristics (cont’d)
VI1 =13.5 V; VINH1 =VINH2= 5V; – 40 °C < Tj < 150 °C; unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Watchdog and Reset Timing D1 (cont’d)
Saturation Voltage
VD1,SAT
100
40
mV VQ1 < VRT2
Watchdog trigger
time
TWI,tr
24
32
17
ms
CD1 = 100 nF
Reset delay time
TRD1
11
–
23
ms
CD1 = 100 nF
CD1 = 100 nF
Reset reaction time Trr
5.0
µs
Reset Output RO1
Reset switching
threshold
VRT1
2.97 3.08 3.18
2.34 2.42 2.50
V
V
TLE 4473 GV53
TLE 4473 GV52
Reset threshold
headroom
VR1HEAD
VR1HEAD
100
80
–
–
–
–
–
mV TLE 4473 GV53
Reset threshold
headroom
–
mV TLE 4473 GV52
Reset output current IRO1
1.4
mA Collector current of RO1,
power good, reset still
delayed.
VQ1= 3.30 V
(TLE 4473 GV53),
VQ1 = 2.60 V
(TLE 4473 GV52);
VQ2=5.0 V;
VD1=0 V,VRO1=0.3 V
Reset output low
voltage
VRO1L
VRO1H
VRO1H
–
0.1
0.3
–
V
V
V
VQ1 ≥ 1 V, VD1=0V,
RO1=0.5mA
I
Reset output high
voltage
2.45 –
3.15 –
RRO1,ext=4.7kΩ connected
to Q1;TLE 4473 GV52
Reset output high
voltage
–
RRO1,ext=4.7kΩ connected
to Q1;TLE 4473 GV53
1) Drop voltage = VI – VQ (measured when the output voltage has dropped 100 mV from the nominal value
obtained at 13.5 V input)
Data Sheet
13
Rev. 1.0, 2004-07-14
TLE 4473 GV53
TLE 4473 GV52
Package Outlines
1)
1)
0.1
0.1
6.4
7.5
A
B
(Mold)
1
5
0.3
10.3
0.1
0.25 B
5 x
=
1
12x
0.25
0.4 +0.13
M
C A B
0.1
5.1
(Metal)
7
12
1
7
12
Index Marking
6
6
1
0.1
7.8
Heatslug
(Heatslug)
1) Does not include plastic or metal protrusion of 0.15 max. per side
GPS09349
Figure 4
P-DSO-12-6 (Plastic Dual Small Outline)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
14
Rev. 1.0, 2004-07-14
Edition 2004-07-14
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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