TLE6285G [INFINEON]
LIN-Transceiver LDO; LIN收发器LDO![TLE6285G](http://pdffile.icpdf.com/pdf1/p00075/img/icpdf/TLE6285_393792_icpdf.jpg)
型号: | TLE6285G |
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描述: | LIN-Transceiver LDO |
文件: | 总23页 (文件大小:649K) |
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LIN-Transceiver LDO
TLE 6285
Target Data Sheet
1
Overview
1.1
Features
• Single-wire transceiver, suitable for LIN protocol
• Transmission rate up to 20 kBaud
• Compatible to LIN specification
• Compatible to ISO 9141 functions
• Very low current consumption in sleep mode
• Control output for voltage regulator
• Short circuit proof to ground and battery
• Overtemperature protection
P-DSO-16-4
• Output voltage 5V, tolerance £ ± 2 %
• 150 mA output current capability
• Low-drop voltage
• Overtemperature protection
• Reverse polarity protection
• Short-circuit proof
• Adjustable reset threshold
• Wide temperature range
• Suitable for use in automotive electronics
Type
TLE 6285 G
Ordering Code
on request
Package
P-DSO-16-4
1.2
Description
The TLE 6285 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit
in a P-DSO-16-4 package. It works as an interface between the protocol controller and
the physical bus. The TLE 6285 is especially suitable to drive the bus line in LIN systems
in automotive and industrial applications. Further it can be used in standard ISO9141
systems.
In order to reduce the current consumption the TLE 6285 offers a sleep operation mode.
In this mode a voltage regulator can be controlled in order to minimize the current
consumption of the whole application (VR in sleep mode <1µA!). The on-chip voltage
regulator (VR) is designed for this application but it is also possible to use an external
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Target Data TLE 6285
voltage regulator. A wake-up caused by a message on the bus enables the voltage
regulator and sets the RxD output low until the device is switched to normal operation
mode. To achieve proper operation of the µC, the device supplies a reset signal. The
reset delay time is selected application specific by an external capacitor. The reset
threshold is adjustable.
®
The IC is based on the Smart Power Technology SPT which allows bipolar and CMOS
control circuitry in accordance with DMOS power devices existing on the same
monolithic circuit.
The TLE 6285 is designed to withstand the severe conditions of automotive applications.
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1.3
Pin Configuration (top view)
GND
INHI
1
2
3
4
5
16
15
14
13
GND
RD
RO
RTh
VCCO
INHO
RxD
VBAT
BUS
TxD
12
6
7
11
10
ENLIN
GND
VCCI
8
9
GND
P-DSO-16-4
Leadframe
1
16
15
14
13
12
11
10
9
GND
GND
RD
2
INHI
RO
Chip:
3
4
5
6
7
RTh
Voltage
Regulator
VCCO
INHO
RxD
VBAT
BUS
Chip:
TxD
VCCI
Transceiver
ENLIN
GND
8
GND
P-DSO-16-4
Figure 1 Pinout
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1.4
Pin Definitions and Functions:
Pin No. Symbol Function
1,8,9,16 GND
Ground; place to cooling tabs to improve thermal behavior
2
INHI
Inhibit Voltage Regulator Input; TTL compatible, HIGH active
(HIGH switches the VR on); connect to VBAT if not needed
3
RO
Reset Output; open collector output connected to the output via
a resistor of 20kW
4
5
6
VCCO
INHO
RxD
5V Output; connected to GND with 22µF capacitor, ESC<3W
Inhibit LIN Output; to control a voltage regulator
Receive Data Output; internal 30kW pull up to Vs, LOW in
dominat state
7
ENLIN
Enable LIN Input; integrated 30kW pull down, transceiver in
normal operation mode when HIGH
10
11
VCCI
TxD
5V Supply Input; VCC input to supply the LIN transceiver
Transmit Data Input; internal 30kW pull up to Vs, LOW in
dominant state
12
13
BUS
VBAT
LIN BUS Output/Input; internal 30kW pull up to Vs, LOW in
dominant state
Battery Supply Input; a reverse current protection diode is
required, block GND with 100nF ceramic capacitor and 22µF
capacitor
14
15
RTh
RD
Reset Threshold; internal defined typical 4.6V, adjustable down
to 3.5V according to the voltage level on this pin; connect to GND
if not needed
Reset delay; connected to ground via external delay capacitor
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1.5
Functional Block Diagram
13
5
VBAT
INHO
10
VCCI
Mode
7
ENLIN
Output
Stage
30 k
9
Control
Driver
30 k
9
12
Bus
Temp.-
Protection
11
TxD
Receiver
6
RxD
TLE 6259 G
5
GND
TLE 4299
13
VBat
4
V
CCO
Band-
Gap-
Reference
Current
and
Saturation
Control
RSO
Inhibit
Control
RRO
INHI
2
SO
SI
Reference
3
RO
Reset
Control
R
14
Th
1,8,9,16
GND
15
RD
Figure 2 Block Diagram
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2
Circuit Description
The TLE 6285 is a single-wire transceiver combined with a LDO. It is a chip by chip
integrated circuit in a P-DSO-16-4 package. It works as an interface between the
protocol controller and the physical bus. The TLE 6285 is especially suitable to drive the
bus line in LIN systems in automotive and industrial applications. Further it can be used
in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed
for sleep mode applications but it is also possible to use an external voltage regulator.
Start Up
Power Up
Normal Mode
ENLIN INHO VCC
high high
ON
ENLIN high
low
ENLIN
Stand-By
INHO
ENLIN
low high
RxD VCC
low1)
ON
3)
ENLIN
(VCC
high
ON)
high
Wake Up
t > tWAKE
Sleep Mode
ENLIN INHO VCC
low floating OFF2)
1)
after wake-up via bus
2)
3)
ON when INHO not connected to INHI
Figure 3 Operation Mode State Diagram
2.1 Operation Modes
In order to reduce the current consumption the TLE 6285 offers a sleep operation mode.
This mode is selected by switching the enable input EN low (see figure 3, state
diagram). In the sleep mode a voltage regulator can be controlled via the INHO output
in order to minimize the current consumption of the whole application. A wake-up caused
by a message on the communication bus automatically enables the voltage regulator by
switching the INHO output high. In parallel the wake-up is indicated by setting the RxD
output low. When entering the normal mode this wake-up flag is reset and the RxD
output is released to transmit the bus data.
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In case the voltage regulator control input is not connected to INH output or the
microcontroller is active respectively, the TLE6285 can be set in normal operation mode
without a wake-up via the communication bus.
2.2
LIN Transceiver
The LIN Transceiver has already a pull up resistor of 30kW as termination implemented.
There is also a diode in this path, to protect the circuit from feedback of voltages from
the bus line to the power supply. To configure the TLE 6285 as a master node, an
additional external termination resistor of 1kW is required. To avoid reverse currents from
the bus line into the battery supply line in case of an unpowered node, it is also
recommended to place a diode in series to the external pull up. For small systems (low
bus capacitance) the EMC performance of the system is supported by an additional
capacitor of at least 1nF in the master node (see figure 6, application circuit).
An capacitor of 10µF at the supply voltage input VS buffers the input voltage. In
combination with the required reverse polarity diode this prevents the device from
detecting power down conditions in case of negative transients on the supply line.
2.3
Input Capacitor
The input capacitor CI is necessary for compensation of line influences. Using a resistor
of approx. 1 W in series with CI, the oscillating circuit consisting of input inductivity and
input capacitance can be damped. The output capacitor is necessary for the stability of
the regulating circuit. Stability is guaranteed at values ³ 22 mF and an ESR of £ 5 W
within the operating temperature range. For small tolerances of the reset delay the
spread of the capacitance of the delay capacitor and its temperature coefficient should
be noted.
2.4
Voltage regulator
The 6285 incorporates a PNP based very low drop linear voltage regular. It regulates the
output voltage to VCC = 5 V for an input voltage range of 5.5 V £ VI £ 45 V. The control
circuit protects the device against potential caused by damages overcurrent and
overtemperature.
The internal control circuit achieves a 5 V output voltage with a tolerance of ± 2% in the
temperature range of Tj = – 40 to 150 °C.
The device includes a power on reset and an under voltage reset function with adjustable
reset delay time and adjustable reset switching threshold as well as a sense control/early
warning function. The device includes an inhibit function to disable it when the ECU is
not used for example while the motor is off.
The reset logic compares the output voltage VCC to an internal threshold. If the output
voltage drops below this level, the external reset delay capacitor CD is discharged. When
VD is lower than VLD, the reset output RO is switched Low. If the output voltage drop is
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very short, the VLD level is not reached and no reset-signal is asserted. This feature
avoids resets at short negative spikes at the output voltage e.g. caused by load changes.
As soon as the output voltage is more positive than the reset threshold, the delay
capacitor is charged with constant current. When the voltage reaches VUD the reset
output RO is set High again.
The reset threshold is either the internal defined VRT voltage (typical 4.6 V) or can be
lowered by a voltage level at the RTh input down to 3.5 V. The reset delay time and the
reset reaction time are defined by the external capacitor CD. The reset function is active
down to VI = 1 V.
The device is capable to supply 150 mA. For protection at high input voltage above 25 V,
the output current is reduced (SOA protection).
2.5
Reset
The power on reset feature is necessary for a defined start of the microprocessor when
switching on the application. For the reset delay time after the output voltage of the
regulator is above the reset threshold, the reset signal is set High again. The reset delay
time is defined by the reset delay capacitor CD at pin RD (refer to figure 4 and 5).
The under-voltage reset circuitry supervises the output voltage. In case VQ decreases
below the reset threshold the reset output is set LOW after the reset reaction time. The
reset LOW signal is generated down to an output voltage VCC to 1 V. Both the reset
reaction time and the reset delay time is defined by the capacitor value.
The power on reset delay time is defined by the charging time of an external delay
capacitor CD.
CD = (td ´ ID) / DV
[1]
With
CD reset delay capacitor
td
reset delay time
DV = VUD,
typical 1.8 V for power up reset
DV = VUD – VLD typical 1.35 V for undervoltage reset
charge current typical 6.5 mA
For a delay capacitor CD =100 nF the typical power on reset delay time is 28 ms.
ID
The reset reaction time tRR is the time it takes the voltage regulator to set reset output
LOW after the output voltage has dropped below the reset threshold. It is typically 1 ms
for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated
using the following equation:
t
RR = 10 ns / nF ´ CD
[2]
The reset output is an open collector output with a pull-up resistor of typical 20 kW to Q.
An external pull-up can be added with a resistor value of at least 5.6 kW.
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In addition the reset switching threshold can be adjusted by an external voltage divider.
The feature is useful for microprocessors which guarantee safe operation down to
voltages below the internally set reset threshold of 4.65 V typical.
If the internal used reset threshold of typical 4.65 V is used, the pin RADJ has to be
connected to GND.
If a lower reset threshold is required by the system, a voltage divider defines the reset
threshold VRth between 3.5 V and 4.60 V:
V
Rth = VRADJ TH ´ (R1 + R2) / R2
[3]
VRADJ TH is typical 1.36 V.
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3
Electrical Characteristics
Absolute Maximum Ratings
3.1
Parameter
Symbol Limit Values Unit
Remarks
min.
max.
Voltages
Supply voltage
VCC
VS
Vbus
Vbus
VI
-0.3
-0.3
-20
-20
-0.3
6
V
V
V
V
V
Battery supply voltage
Bus input voltage
Bus input voltage
Logic voltages at
EN, TxD, RxD
40
32
40
t < 1 s
0 V < VCC < 5.5 V
VCC
+ 0.3
Input voltages at INH
VINH
-0.3
VS
V
+ 0.3
Output current at INH
Reset output voltage
Reset delay voltage
Output voltage Vcc
INHIBIT voltage
Reset Threshold voltage
Reset Threshold current
Electrostatic discharge
voltage at Vs, Bus
IINH
VR
1
7
7
7
45
7
10
4
mA
V
V
V
V
V
mA
kV
– 0.3
– 0.3
– 0.3
– 40
– 0.3
– 10
-4
VD
VQ
VINH
VTh
ITh
VESD
human body model
(100 pF via 1.5 kW)
Electrostatic discharge
voltage
VESD
-2
2
kV
human body model
(100 pF via 1.5 kW)
Temperatures
Junction temperature
Tj
-40
150
°C
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause
irreversible damage to the integrated circuit.
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3.2
Operating Range
Parameter
Symbol Limit Values Unit
Remarks
min.
4.5
6
max.
5.5
20
Supply voltage
Battery Supply Voltage
Junction temperature
VCC
VS
Tj
V
V
°C
–
– 40
150
Thermal Shutdown (junction temperature)
Thermal shutdown temp.
Thermal shutdown hyst.
TjSD
DT
150
–
170
10
190
–
°C
K
Thermal Resistances
–
–
Junction ambient LIN
Junction ambient Vreg
Rthj-a
Rthj-a
–
–
185
70
K/W
K/W
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3.3
Electrical Characteristics
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with
respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Current Consumption LIN
recessive state;
Current consumption
ICC
IS
0.5
0.5
0.7
0.7
20
1.5
1.0
2.0
1.5
30
mA
V
TxD = VCC
recessive state;
TxD = VCC
Current consumption
Current consumption
Current consumption
Current consumption
Current consumption
mA
mA
mA
µA
V
dominant state;
TxD = 0 V
ICC
IS
V
dominant state;
TxD = 0 V
V
sleep mode;
IS
Tj = 25 °C
sleep mode
IS
20
40
µA
Current Consumption Vreg
Inhibit ON;
Current consumption;
Iq
Iq
Iq
Iq
Iq
–
–
–
–
–
65
65
170
0.7
–
105
100
500
2
mA
mA
mA
mA
mA
IQ £ 1 mA, Tj < 85 °C
Iq = II – IQ
Inhibit ON;
Current consumption;
IQ £ 1 mA, Tj = 25 °C
Iq = II – IQ
Inhibit ON;
Current consumption;
IQ = 10 mA
Iq = II – IQ
Inhibit ON;
Current consumption;
Iq = II – IQ
IQ = 50 mA
VINHI = 0 V;
Tj = 25 °C
Current consumption;
1
Iq = II – IQ
Receiver Output R´D
VRD = 0.8 x VCC
VRD = 0.2 x VCC
,
,
HIGH level output current
LOW level output current
IRD,H
IRD,L
-0.7 -0.4 mA
0.7 mA
0.4
12
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3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with
respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Bus receiver
-8 V < Vbus < Vbus,dom
Receiver threshold voltage, Vbus,rd 0.44 0.48
V
V
recessive to dominant edge
x VS x VS
0.52 0.56
x VS x VS
Vbus,rec < Vbus < 20 V
Receiver threshold voltage, Vbus,dr
dominant to recessive edge
Vbus,hys
=
Receiver hysteresis
Vbus,hys 0.02 0.04 0.06 mV
x VS x VS x VS
V
bus,rec - Vbus,dom
wake-up threshold voltage
Vwake
0.40 0.55 0.70
V
x VS x VS x VS
Transmission Input T´D
recessive state
HIGH level input voltage
threshold
VTD,H
2.9
0.7 x V
VCC
TxD input hysteresis
LOW level input voltage
threshold
VTD,hys 300 600
mV
V
dominant state
VTxD < 0.3 Vcc
VTD,L
0.3 x 2.1
VCC
TxD pull up current
ITD
-150 -110 -80
µA
Bus transmitter
VTxD = VCC
Bus recessive output voltage Vbus,rec 0.9 x
VS
V
VS
VTxD = 0 V;
Bus dominant output voltage Vbus,dom
0
1.5
V
Vbus,short = 13.5 V
Bus short circuit current
Leakage current
Ibus,sc
Ibus,lk
40
85
125
mA
mA
VCC = 0 V, VS = 0 V,
Vbus = -8 V, Tj < 85 °C
-350 -100
VCC = 0 V, VS = 0 V,
Vbus = 20 V, Tj < 85 °C
5
20
47
mA
kW
Bus pull up resistance
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Rbus
20
30
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3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with
respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Enable input (pin ENLIN)
normal mode
HIGH level input voltage
threshold
VEN,on
2.8
0.7 x V
VCC
low power mode
LOW level input voltage
threshold
VEN,off 0.3 x 2.2
V
VCC
EN input hysteresis
VEN,hys 300 600
mV
EN pull down resistance
REN
15
30
60
kW
Inhibit output (pin INHO)
IINHO = - 0.15 mA
HIGH level drop voltage
DVINH
0.5
1.0
5.0
V
DVINH = VS - VINH
sleep mode;
Leakage current
IINH,lk
- 5.0
µA
VINHO = 0 V
Vcc Output (pin Vcco)
1 mA £ IQ £ 100 mA;
Output voltage
VQ
VQ
4.90 5.00 5.10
4.85 5.00 5.15
V
6 V £ VI £ 16 V
IQ £ 150 mA;
Output voltage
V
6 V £ VI £ 16 V
–
Current limit
IQ
250 400
500
mA
IQ = 100 mA1)
Drop voltage
Load regulation
Line regulation
Vdr
DVQ
DVQ
–
–
–
0.22 0.5
V
mV
mV
IQ = 1 mA to 100 mA
5
30
25
VI = 6 V to 28 V;
10
IQ = 1 mA
fr = 100 Hz; Vr = 1 VSS
;
Power Supply Ripple
rejection
PSRR
–
66
–
dB
IQ = 100 mA
5 mA £ IQ £ 150 mA;
Output voltage
VQ
VQ
4.90 5.00 5.10
4.90 5.00 5.10
V
6 V £ VI £ 28 V
6 V £ VI £ 32 V;
Output voltage
V
IQ = 100 mA;
Tj = 100 °C
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3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with
respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Reset Generator (pins RO,RD)
–
Switching threshold
Reset pull up
Reset low voltage
Vrt
RRO
VR
4.50 4.60 4.80
V
kW
V
–
10
–
20
40
VQ < 4.5 V; internal
RRO; IR = 1 mA
0.17 0.40
Pull up resistor to Q
–
External reset pull up
Delay switching threshold
Switching threshold
Reset delay low voltage
Charge current
Reset delay time
Reset reaction time
Reset adjust switching
threshold
VR ext
VDT
VST
VD
Ich
td
5.6
1.5
–
–
kW
V
V
1.85 2.2
–
0.40 0.50 0.60
–
4.0
17
0.5
VQ < VRT
VD = 1 V
CD = 100 nF
CD = 100 nF
VQ > 3.5 V
–
0.1
12.0 mA
35
3.0
V
8.0
28
1.2
ms
ms
V
trr
VRADJ TH 1.26 1.36 1.44
Inhibit Input (pin INHI)
VQ off
Inhibit OFF voltage range
VINH
–
–
0.8
V
OFF
VQ on
Inhibit ON voltage range
High input current
Low input current
VINH ON 3.5
–
3
0.5
–
5
2
V
mA
mA
VINHI = 5 V
VINHI = 0 V
IINH ON
–
–
IINH OFF
Note: The reset output is low within
the range VQ = 1 V to VQ,rt
1)Drop voltage = Vi – VQ (measured
when the output voltage has
dropped 100 mV
from the nominal value obtained at
6 V input)
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3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with
respect to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Dynamic Transceiver Characteristics
80% > Vbus > 20%
falling edge slew rate
Sbus(L)
-3
-2.0 -1
V/µs
Cbus= 3.3 nF;
Tambient < 85 °C;
V
CC = 5 V; VS = 13.5 V
20% < Vbus < 80%
rising edge slew rate
Sbus(H)
td(L),TR
1
2
1.5
5
3
V/µs
µs
Cbus= 3.3 nF;
V
CC = 5 V; VS = 13.5 V
Cbus = 3.3nF;
Propagation delay
TxD-to-RxD LOW (recessive
to dominant)
10
V
CC = 5 V; VS = 13.5 V
CRxD = 20 pF
Cbus = 3.3 nF;
Propagation delay
TxD-to-RxD HIGH (dominant
to recessive)
td(H),TR
2
5
10
µs
V
CC = 5 V; VS = 13.5 V
CRxD = 20 nF
VCC = 5 V
Propagation delay
TxD LOW to bus
Propagation delay
TxD HIGH to bus
td(L),T
td(H),T
td(L),R
td(H),R
tsym,R
1
1
1
1
4
4
4
4
µs
µs
µs
µs
VCC = 5 V
VCC = 5V;
Propagation delay
CRxD = 20pF
bus dominant to RxD LOW
VCC = 5 V;
Propagation delay
CRxD = 20 pF
bus recessive to RxD HIGH
tsym,R = td(L),R - td(H),R
tsym,T = td(L),T - td(H),T
Receiver delay symmetry
Transmitter delay symmetry tsym,T
Wake-up delay time
-2
-2
30
2
2
200
µs
µs
µs
twake
100
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4
Diagrams
V
I
<
trr
t
VQ
VQ, rt
ID, ch
d
d
V
t
t
t
t
=
VD
CD
VDU
VDRL
trd
trr
VRO
Power-ON
Reset
Over-
temperature
Voltage Drop Under-
at Input voltage
Secondary
Spike
Load
Bounce
AET03066
Figure 4
Time Response, Watchdog with High-Frequency Clock
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Typical Performance Characteristics
Output Voltage VQ versus
Temperature Tj
Output Voltage VQ versus
Input Voltage VI
AED01671
AED01808
5.2
12
VQ
VQ
V
V
5.1
10
VΙ = 13.5 V
5.0
8
4.9
4.8
4.7
4.6
6
RL = 50
Ω
4
2
0
-40
0
40
80
120 C 160
0
2
4
6
8
V 10
Tj
VΙ
Version 1.02
18
2002-05-15
Target Data TLE 6285
Charge Current Ich versus
Temperature Tj
Drop Voltage Vdr versus
Output Current IQ
AED03108
AED02929
12
400
mV
µA
10
ID
VDR
125 ˚C
300
250
200
150
100
50
8
6
4
2
0
25 ˚C
V
= 13.5 V
I
VD = 1 V
0
-40
0
40
80
120 ˚C 160
0
50
100
150 mA 200
Tj
IQ
Switching Voltage Vdt and Vst versus
Temperature Tj
Reset Adjust Switching Threshold
VRADJTH versus Temperature Tj
AED03109
AED01804
1.5
3.2
V
VD
V
VRADJTH
2.8
1.4
1.3
1.2
1.1
1.0
0.9
VΙ = 13.5 V
2.4
2.0
1.6
1.2
0.8
0.4
0
VUD
V
LD
-40
0
40
80
120 ˚C 160
-40
0
40
80
120 C 160
Tj
Tj
Version 1.02
19
2002-05-15
Target Data TLE 6285
Sense Threshold Vsi
Output Current Limit IQ versus
versus Temperature Tj
Input Voltage VI
AED02933
AED03110
350
1.6
Ι Q
mA
V
VSi
300
1.5
Sense Output High
Sense Output Low
250
200
150
100
50
1.4
1.3
1.2
1.1
1.0
Tj = 25 C
Tj = 125 C
0
-40
0
40
80
120 ˚C 160
0
10
20
30
40
V 50
Tj
VΙ
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Output Current IQ
AED02931
AED02932
1.0
mA
5
mA
Iq
Iq
0.8
0.6
0.4
0.2
0
4
3
2
1
0
0
10
20
30
40
mA 60
0
50
100
150 mA 200
IQ
IQ
Version 1.02
20
2002-05-15
Target Data TLE 6285
5
Application
Vbat LIN bus
master node
3
7
RO
VBAT
13
ENLIN
22 µF
6
11
10
RxD
TxD
VCCI
µP
100 nF
1 k
12 Bus
5
INHO
GND
TLE 6285 G
100 nF
100 nF
5V
4
VCCO
2
INHI
RD
R1
R2
22 µF
RTh
1,8,9,16
15
14
GND
CD
100 nF
ECU 1
slave node
3
7
RO
VBAT
13
ENLIN
22 µF
6
RxD
TxD
VCCI
µP
100 nF
12
5
11
10
Bus
INHO
GND
TLE 6285 G
100 nF
100 nF
5V
4
VCCO
2
INHI
RD
R1
R2
22 µF
RTh
1,8,9,16
15
14
GND
CD
100 nF
ECU X
Figure 5
Application Circuit
Version 1.02
21
2002-05-15
Target Data TLE 6285
6
Package Outlines
P-DSO-16-4
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Dimensions in mm
Version 1.02
22
2002-05-15
Target Data TLE 6285
Edition 1999-10-12
Published by Infineon Technologies AG
St.-Martin-Strasse 53
D-81541 München
© Infineon Technologies AG1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and
shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited
to warranties of non-infringement, regarding circuits, descriptions
and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and condi-
tions and prices please contact your nearest Infineon Technologies
Office in Germany or our Infineon Technologies Representatives
worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous
substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-sup-
port devices or systems with the express written approval of Infine-
on Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system,
or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the hu-
man body, or to support and/or maintain and sustain and/or protect
human life. If they fail, it is reasonable to assume that the health of
the user or other persons may be endangered.
Version 1.02
23
2002-05-15
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