TLE7244SLXUMA2 [INFINEON]
Buffer/Inverter Based Peripheral Driver, 0.29A, PDSO24, GREEN, PLASTIC, SSOP-24;
| 型号： | TLE7244SLXUMA2 |
| 厂家： | 
Infineon |
| 描述： | Buffer/Inverter Based Peripheral Driver, 0.29A, PDSO24, GREEN, PLASTIC, SSOP-24 驱动 光电二极管 接口集成电路 |
| 文件： | 总28页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet, Rev. 1.3, October 2011
SPIDER - TLE7244SL
8 Channel Protected Low-Side Relay Switch
Automotive Power
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Table of Contents
Table of Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Voltage and Current naming definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
5
Input and Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input and Power Stages Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.1.1
5.2
5.2.1
5.2.2
5.3
6
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
6.2
6.3
6.4
7
7.1
Diagnosis Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Diagnosis Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1
8.2
8.3
8.3.1
8.4
9
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
11
Datasheet
2
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
SPIDER - TLE7244SL
1
Overview
Features
•
•
•
•
•
•
•
4 input pins providing flexible PWM configuration
Limp home functionality (direct driving) provided by a dedicated pin
16 bit SPI for diagnostics and control
Daisy chain capability also compatible with 8bit SPI devices
Very wide range of digital supply voltage
Green Product (RoHS compliant)
AEC Qualified
PG-SSOP-24-7
Description
The SPIDER - TLE7244SL is a eight channel low-side switch in PG-SSOP-24-7 package providing embedded
protective functions.
It is especially designed as relay driver in automotive applications.
A serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the load.
For direct control and PWM there are four input pins available.
The device is monolithically integrated. The power transistors are built by N-channel MOSFETs.
Table 1
Basic Electrical data
Digital supply voltage
Analog supply voltage
VDD
VDDA
3.0 V ... 5.5 V
4.5 V ... 5.5 V
Max. ON State resistance at Tj = 150°C for each channel RDS(ON,max) 1.7 Ω
Nominal load current
IL (nom)
290 mA
Overload switch off threshold
Output leakage current per channel at 25 °C
Drain to Source clamping voltage
Maximum SPI clock frequency
ID (OVL,max) 950 mA
ID (STB,max) 1 µA
VDS(AZ)
41 V
5 MHz
fSCLK,max
Diagnostic Features
•
•
•
•
latched diagnostic information via SPI register
Overtemperature monitoring
Overload detection in ON state
Open load detection in OFF state
Type
Package
PG-SSOP-24-7
Marking
TLE7244SL_A
SPIDER - TLE7244SL
Datasheet
3
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Overview
Protection Functions
•
•
•
•
Short circuit
Over load
Over temperature
Electrostatic discharge (ESD)
Application
•
•
All types of resistive, inductive and capacitive loads
Especially designed for driving relays in automotive applications
Detailed Description
The SPIDER - TLE7244SL is a eight channel low-side relay switch designed for typical automotive relays
providing embedded protective functions. The PG-SSOP-24-7 package is used to get a footprint optimized
solution. The 16 bit serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads.
The SPI interface provides daisy chain capability.
The SPIDER - TLE7244SL is equipped with four input pins that can be individually routed to the output control of
their dedicated channels thus offering flexibility in design and PCB layout. The input multiplexer is controlled via
SPI.
There is a dedicated limp home pin LHI which provides a straightforward usage of the input pins as dedicated
driver for four outputs.
The device provides full diagnosis of the load, which is open load as well as short circuit detection. The SPI
diagnosis bits indicate latched fault conditions that may have occurred.
Each output stage is protected against short circuit. In case of over load, the affected channel switches off. There
are temperature sensors available for each channel to protect the device in case of over temperature.
The device is supplied by two power supply lines. The analog supply supports 5 V, the digital supply offers a very
wide flexibility in supply voltage ranging from 3.0 V up to 5.5 V.
The power transistors are built by N-channel vertical power MOSFETs. The inputs are ground referenced CMOS
compatible. The device is monolithically integrated in Smart Power Technology.
In terms of PCB layout improvement, all output pins are available at one side of the device. The other side bundles
the signals to the micro-controller.
Datasheet
4
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Block Diagram
2
Block Diagram
VDD
VDDA
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
RST
stand-by control
IN1
IN2
IN3
IN4
input mux and
control
control,
diagnostic
and
protective
functions
temperature
LHI
sensor
CS
SCLK
SI
short circuit
detection
SPI
gate
control
SO
open load
detection
diagnosis
register
GND
Blockdiagram.emf
Figure 1
Block Diagram for the SPIDER - TLE7244SL
Datasheet
5
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
(top view)
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
GND
VDDA
CS
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GND
SI
RST
SCLK
SO
5
6
7
8
9
10
11
12
LHI
IN1
IN2
IN3
IN4
GND
VDD
Pinout.emf
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
20
1)
Pin
Symbol
I/O
Function
Power Supply
13
VDD
-
-
-
Digital Supply Voltage; Connected to 3.3V or 5V Voltage with Reverse
protection Diode and Filter against EMC
24
VDDA
Analog Supply Voltage; Connected to 5V Voltage with Reverse
protection Diode and Filter against EMC
Ground; common ground for digital, analog and power
1,2,11,12 GND
Power Stages
3
4
5
6
7
8
9
10
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
O
O
O
O
O
O
O
O
Output Channel 1; Drain of power transistor channel 1
Output Channel 2; Drain of power transistor channel 2
Output Channel 3; Drain of power transistor channel 3
Output Channel 4; Drain of power transistor channel 4
Output Channel 5; Drain of power transistor channel 5
Output Channel 6; Drain of power transistor channel 6
Output Channel 7; Drain of power transistor channel 7
Output Channel 8; Drain of power transistor channel 8
Inputs
17
16
IN1
IN2
I
I
PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
Datasheet
6
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Pin Configuration
1)
Pin
15
14
18
21
SPI
23
20
22
19
Symbol
IN3
IN4
LHI
RST
I/O
Function
I
I
I
I
PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
PD Control Input; Digital input 3.3 V or 5V. In case of not used keep open.
PD Limp Home; Digital input 3.3 V or 5V. In case of not used keep open.
PD Reset input pin; Digital input 3.3 V or 5V. Low active
CS
SCLK
SI
I
I
I
O
PU SPI chip select; Digital input 3.3 V or 5V. Low active
PD serial clock; Digital input 3.3 V or 5V.
PD serial data in; Digital input 3.3 V or 5V.
SO
serial data out; Digital output with voltage level referring to VDD.
1) O: Output, I: Input,
PD: pull-down resistor integrated,
PU: pull-up resistor integrated
Datasheet
7
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Pin Configuration
3.3
Voltage and Current naming definition
Figure 3 shows all the terms used in this data sheet, with associated convention for positive values.
Vbat
IDDA
IDD
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
VDDA
VDD
RST
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VDS1
VDS2
VDS3
VDS4
VDS5
VDS6
VDS7
VDS8
VDDA
VDD
VRST
IRST
IIN1
IN1
IN2
IN3
IIN2
VIN1
VIN 2
VIN3
IIN3
IIN4
OUT8
CS
IN4
LHI
I
CS
VIN4
ILHI
ISCLK VCS
VLHI
SCLK
SI
VSCLK
VSI
ISI
ISO
SO
VSO
GND
IGND
Terms.emf
Figure 3
Terms
Datasheet
8
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Unless otherwise specified: Tj = -40 C to +150 C; VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V
all voltages with respect to ground, positive current flowing into pin
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Power Supply
4.1.1
4.1.2
4.1.3
Digital supply voltage
Analog supply voltage
Output voltage for short circuit protection VOUT
(single pulse)
VDD
VDDA
-0.3
-0.3
0
5.5
5.5
36
V
V
V
–
–
–
Power Stages
4.1.4
4.1.5
4.1.6
Load current
Voltage at power transistor
Maximum energy dissipation one
channel
ID
VDS
EAS
-0.5
–
0.5
41
A
V
mJ
–
active clamped
2)
V =16V,
clamp
bat
V
=45V,
Tj(0) = 150 °C
ID(0) =0.50 A
Tj(0) = 105 °C
ID(0) =0.40 A
Tj(0) = 105 °C
ID(0) =0.40 A
single pulse
–
–
–
67
31
24
EAR
repetitive (1 · 104 cycles)
repetitive (1 · 106 cycles)
Logic Pins
–
–
4.1.7
IN1,IN2,IN3,IN4;Voltage at input pins
VIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
5.5
5.5
5.5
V
V
V
V
V
V
V
4.1.8
RST; Voltage at reset pin
VRST
VLHI
VCS
VSCLK
VSI
4.1.9
LHI; Voltage at limp home input pin
CS; Voltage at chip select
SCLK; Voltage at serial clock pin
SI; Voltage at serial input pin
SO; Voltage at serial output pin
–
3)
4.1.10
4.1.11
4.1.12
4.1.13
V
V
V
V
DD + 0.3
DD + 0.3
DD + 0.3
DD + 0.3
3)
3)
3)
VSO
Temperatures
4.1.14
4.1.15
Junction Temperature
Storage Temperature
Tj
Tstg
-40
-55
150
150
°C
°C
–
–
ESD Susceptibility
HBM4)
4.1.16
ESD Resistivity
VESD
-4
4
kV
1) Not subject to production test, specified by design.
2) Pulse shape represents inductive switch off: I (t) = I (0) × (1 - t / tpulse); 0 < t < t
D
D
pulse
3) level must not exceed VDD+0.3V < 5.5 V
4) ESD susceptibility, HBM according to EIA/JESD 22-A114
Datasheet
9
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
General Product Characteristics
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
5.5
5.5
4.2.1
4.2.1
4.2.2
Digital supply voltage
Analog supply voltage
extended supply range
VDD
VDDA
VDDA
3.0
4.5
4.0
V
V
–
–
4.5
parameter deviations are
possible
4.2.3
4.2.4
Digital Supply current in reset mode IDD(RST)
–
–
10
0.5
µA
mA
Tj = 85 °C
Digital supply current
IDD(ON)
V
DD = VDDA = 5 V
(all channels active)
V
RST = VCS = VDD
VSCLK = 0 V
VIN = 0 V
4.2.5
4.2.6
Analog supply current
(all channels active)
Analog supply turn-ON time
IDDA(ON)
–
5
–
mA
µs
–
tDDA(ON)
15
VDDA = 0V to 5V (linear)
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note:This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
–
Typ.
–
Max.
25
1) 2)
4.3.7
4.3.8
4.3.9
Junction to Soldering Point
RthJSP
RthJA
RthJA
K/W
K/W
K/W
1) 3)
1) 4)
Junction to Ambient
(1s0p+600mm2Cu)
Junction to Ambient (2s2p)
–
–
68
58
–
–
1) Not subject to production test, specified by design
2) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).
Ta = 25 °C. LS1 to LS8 are dissipating 1 W power (0.125 W each).
3) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm2
and 70 µm thickness. Ta = 25 °C, LS1 to LS8 are dissipating 1 W power (0.125 W each).
4) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Ta = 25 °C, LS1 to LS8 are dissipating 1 W power (0.125 W each).
Datasheet
10
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Input and Power Stages
5
Input and Power Stages
The SPIDER - TLE7244SL is a eight channel low-side relay switch.
The power stages are built by N-channel vertical power MOSFET transistors.
5.1
Power Supply
The SPIDER - TLE7244SL is supplied by two power supply lines VDD and VDDA
.
The digital power supply line VDD is designed to be functional at a very wide voltage range. The analog power
supply VDDA supports 5 V supply.
There are power-on reset functions implemented for both supply lines. After start-up of the power supply, all SPI
registers are reset to their default values and the device is in idle mode. Capacitors at pins VDD -GND and VDDA
-
GND are recommended.
There is a reset pin available. Low level at this pin causes all registers to be set to their default values and the
quiescent supply currents are minimized.
5.1.1
Limp Home Mode
The SPIDER - TLE7244SL offers the capability of driving dedicated channels during eventual fail-safe operation
of the system. This limp home mode is activated by a high signal at pin LHI. In this mode, the SPI registers are
reset and the input pins are directly routed to their corresponding channels OUT1 to OUT4, see Table 2 for details.
OUT5 to OUT8 are turned off in limp home mode. Furthermore, the SPI is ignored and all input pin are referred to
V
DDA in order to ensure a defined operation mode if the digital supply or the microcontroller fail.
A high signal on LHI overrides a Reset signal on RST. In case of a limp home during standby the device will
therefore wake up and enter the limp home mode.
After limp home operation all registers are reset and the device enters in standby mode following low logic RST
state, or returns to idle (all channels OFF). Next SPI transmission will receive a TER Flag.
Input
controlled
Output
IN1
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
Table 2
Routing during limp home mode
5.2
Input Circuit
There are four input pins available at SPIDER - TLE7244SL, which can be configured to be used for control of the
output stages. The INnparameter of the SPI selects the input pin to be used. Figure 4 shows the input circuit of
SPIDER - TLE7244SL.
During Limp home mode a default routing is switched and the SPI commands are ignored.
Datasheet
11
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Input and Power Stages
OFF
Channel 1
IN1
ON
OFF
LHI
IN1
IN2
IN3
IN4
OFF
Channel 2
IN2
IN3
IN4
ON
OFF
LHI
Channel 3
OFF
ON
OFF
IN1
IN2
LHI
Channel 4
IIN 1
OFF
ON
IIN 2
OFF
LHI
Channel 5
OFF
IN3
IN4
OFF
IIN 3
ON
OFF
IN5
IN6
IN7
LHI
Channel 6
IIN 4
OFF
OFF
OFF
ON
OFF
LHI
Channel 7
OFF
ON
OFF
LHI
Channel 8
LHI
LHI
ILHI
OFF
OFF
ON
OFF
IN8
LHI
InputLogic.emf
Figure 4
Input matrix and logic
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses. After power-on reset, the device enters idle mode (all channel OFF).
5.2.1
Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance
intends to continue driving the current. The voltage clamping is necessary to prevent destruction of the device,
see Figure 5 for details. Nevertheless, the maximum allowed load inductance is limited.
Datasheet
12
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Input and Power Stages
Vbat
L,
RL
ID
OUT
VDS
VDS(CL)
GND
OutputClamp.emf
Figure 5
Output Clamp Implementation
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the SPIDER - TLE7244SL. This energy
can be calculated with following equation:
V
bat – VDS(CL)
RL IL
bat – V
L
------------------------------------
------
E = VDS(CL)
ln 1 – ------------------------------------ + IL
RL
RL
V
DS(CL)
Following equation simplifies under the assumption of RL = 0:
Vbat
bat – V
2
1
--
E = LIL
1 – ------------------------------------
2
V
DS(CL)
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
5.2.2
Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the IN bits of the serial peripheral
interface SPI. The switching times tON and tOFF are designed equally.
CS
SPI: ON
SPI: OFF
t
tON
tOFF
VDS
80%
20%
t
SwitchOn.emf
Figure 6
Switching a Resistive Load
In input mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to SPI OFF
command respectively. Please refer to Section 8.3 for details on operation modes.
Datasheet
13
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Input and Power Stages
5.3
Input and Power Stages Characteristics
Note:Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Supply and Input
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 C to +150 C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Power Supply
VDD
5.3.1
5.3.2
Digital supply voltage
3.0
–
–
–
5.5
0.5
V
mA
–
Digital supply current, all channels IDD(ON)
V
DD = VDDA = 5 V
ON
V
RST = VCS = VDD
VSCLK = 0 V
VIN = 0 V
5.3.3
Digital supply stand-by current, all IDD(STB)
µA
fSCLK = 0 Hz
channels in stand-by mode
VCS = VDD
–
–
–
–
–
–
20
20
40
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
5.3.4
5.3.5
Digital supply reset current
IDD(RST)
µA
VRST =VLHI = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
–
–
–
–
–
–
10
10
20
Digital power-on reset threshold
voltage
VDD(PO)
–
–
2.7
V
–
5.3.6
5.3.7
Analog supply voltage
Analog supply current
all channels ON
VDDA
IDDA(ON)
4.5
–
–
–
5.5
5
V
mA
–
–
5.3.8
5.3.9
Analog supply stand-by current
all channels in stand-by mode
IDDA(STB)
µA
VCS = VDD
VSI = 0 V
VSCLK = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
VRST =VLHI = 0 V
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
20
20
40
Analog supply reset current
IDDA(RST)
µA
5
5
20
5.3.10 Analog power-on reset threshold VDDA(PO)
–
–
4.0
V
–
voltage
Datasheet
14
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Input and Power Stages
Electrical Characteristics: Supply and Input
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 C to +150 C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Output characteristics
5.3.11 On-State resistance per channel
RDS(ON)
–
0.8
1.4
–
–
Ω
IL = 400 mA
Tj = 25 °C 1)
–
1.7
–
IL = 400 mA
Tj = 150 °C
5.3.12 Nominal load current
IL(nom)
290
mA
µA
V
1)all channels on
Ta = 85 °C
T
j,max = 150 °C
based on Rthja,2s2p
5.3.13 Output leakage current in stand-by ID(STB)
VDS = 13.5 V
mode
(per channel)
–
–
–
–
–
–
1
2
5
Tj = 25 °C 1)
Tj = 85 °C 1)
Tj = 150 °C
5.3.14 Output clamping voltage
VDS(CL)
41
–
54
–
Input Characteristics
L level of pins IN1..IN4 and LHI
VIN(L)
VIN(H)
V
–
5.3.15
5.3.16
5.3.17
5.3.18
0
2.0
3
–
–
12
40
0.6
5.5
80
2)
H level of pins IN1..IN4 and LHI
V
1)
L-input pull-down current through pin IN IIN(L)
µA
µA
V = 0.6 V
IN
H-input pull-down current through pin IIN(H)
V
V
DD = 5.5 V
10
80
IN
IN = VDD
Reset Characteristics
L level of pin RST
VRST(L)
VRST(H)
–
–
5.3.19
0
–
–
0.2*
VDD
H level of pin RST
5.3.20
0.4*
VDD
3
VDD
L-input pull-down current through pin IRST(L)
µA
µA
1) VRST = 0.6 V
5.3.21
12
40
80
80
RST
H-input pull-down current through pin IRST(H)
V
DD = 5.5 V
5.3.22
10
RST
V
RST = VDD
Timings
5.3.23 Reset wake-up time
5.3.24 Reset and LHI signal duration
twu(RST)
tRST(L)
tON
–
50
–
–
–
30
200
–
50
µs
µs
µs
–
–
5.3.25 Turn-on time
Vbat = 13.5 V
VDS = 20% Vbat
resistive load
all channels
IDS = 180 mA
5.3.26 Turn-off time
tOFF
–
30
50
µs
Vbat = 13.5 V
VDS = 80% Vbb
resistive load
all channels
IDS = 180 mA
1) Not subject to production test, specified by design.
2) level must not exceed VDD+0.3V < 5.5 V
Datasheet
15
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Protection Functions
6
Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent IC
destruction under fault conditions described in this datasheet. Fault conditions are considered as “outside” normal
operating range. Protection functions are not designed for continuous repetitive operation.
6.1
Over Load Protection
The SPIDER - TLE7244SL is protected in case of over load or short circuit of the load. After time tOFF(OVL), the over
loaded channel nswitches off and the according diagnosis flag Dnis set.The channel can be switched on after
clearing the diagnosis flag. Please refer to Figure 7 for details.
IN1
t
t
tOFF(OVL)
Program OUT 1 to
STANDBY and to
IN1 again
IOUT1
IOUT(OVL)
IN1 = 01b
D1 = 0b
D1 = 1b
D1 = 0b
OverLoad.emf
Figure 7
Shut down at over load
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses. After power-on reset, the device enters idle mode.
6.2
Over Temperature Protection
A temperature sensor for each channel causes an overheated channel nto switch off to prevent destruction and
the according diagnosis flag Dnis set. The channel can be switched on after clearing the diagnosis flag. Please
refer to Chapter 7.1 for information on diagnosis features.
6.3
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diode of the power transistor causes power dissipation. The reverse
current through the intrinsic body diode of the power transistor has to be limited by the connected load. The VDD
and VDDA supply pins must be protected against reverse polarity externally. The over temperature and over load
protection is not active during reverse polarity.
Datasheet
16
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Protection Functions
6.4
Protection Characteristics
Note:Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Protection
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 C to +150 C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
0.5
3
Typ.
Max.
Over Load Protection
6.4.1
6.4.2
Over load detection current
all channels
Over load shut-down delay time
ID(OVL)
tOFF(OVL)
Tj(SC)
–
0.95
50
–
A
–
–
–
–
µs
°C
Over Temperature Protection
6.4.3 Thermal shut down temperature
150
1701)
–
1) Not subject to production test, specified by design
Datasheet
17
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Diagnosis Features
7
Diagnosis Features
The SPI of SPIDER - TLE7244SL provides diagnosis information about the device and about the load. There are
following diagnosis flags implemented:
The diagnosis information of the protective functions of channel nis latched in the diagnosis flag Dn.
The open load diagnosis of channel nis latched in the diagnosis flag OLn.
Both flags are cleared by programming the specific channel to Standby (STB).
Failure Mode
Comment
Open Load or short circuit Diagnosis, when channel nis switched on: none
to ground
Diagnosis, when channel nis switched off: according to voltage level at the output pin, flag OLn
is set after time td(OL)
.
When the channel is in OFF there is Diagnosis active, in Standby the Diagnosis is not enabled
Over Temperature
When over temperature occurs, the according diagnosis flag Dnis set. If the affected channel n
was active it is switched off.
The diagnosis flags are latched until they have been cleared by programming the channel STB.
Over Load
(Short Circuit)
When over load is detected at channel n, the affected channel is switched off after time tOFF(OVL)
and the dedicated diagnosis flag Dnis set.
The diagnosis flags are latched until they have been cleared by programming the channel STB
7.1
Diagnosis Characteristics
Note:Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Diagnosis
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 C to +150 C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
OFF State Diagnosis
7.1.1
7.1.2
7.1.3
Open load detection threshold
voltage
VDS(OL)
1.0
–
–
–
–
2.5
80
V
–
Output pull-down diagnosis current ID(PD)
µA
µs
V
DS = 13.5 V
per channel
Open load diagnosis delay time
td(OL)
30
200
–
ON State Diagnosis
7.1.4
7.1.5
Over load detection current
Over load detection delay time
ID(OVL)
tOFF(OVL)
0.5
3
–
–
0.95
50
A
µs
–
–
Datasheet
18
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Serial Peripheral Interface (SPI)
8
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred, while the minimum of 16 bit is also taken into
consideration. Therefore the interface provides daisy chain capability even with 8 bit SPI devices.
MSB 14
MSB 14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
SO
SI
CS
SCLK
time
SPI.emf
Figure 8
Serial peripheral interface
The SPI protocol is described in Section 8.3. It is reset to the default values after power-on reset.
8.1
SPI Signal Description
CS - Chip Select:
The system micro controller selects the SPIDER - TLE7244SL by means of the CS pin. Whenever the pin is in low
state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CS High to Low transition:
•
•
The diagnosis information is transferred into the shift register.
SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. The transmission error flag is set after any kind of reset, so a reset
between two SPI commands is indicated. For details, please refer to Figure 9. This information stays available
to the first rising edge of SCLK.
TER
SI
SO
1
0
OR
SO
S
SI SPI
CS
SCLK
S
TER. emf
Figure 9
Transmission Error Flag on SO Line
Datasheet
19
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Serial Peripheral Interface (SPI)
CS Low to High transition:
Data from shift register is transferred into the input matrix register only, when after the falling edge of CS exactly
a multiple (1, 2, 3, …) of eight SCLK signals have been detected, while the minimum valid length is of course 16
clocks for the 16 register bits of SPIDER - TLE7244SL.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. Please refer to Section 8.3 for further information.
SO - Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 8.3
for further information.
8.2
Daisy Chain Capability
The SPI of SPIDER - TLE7244SL provides daisy chain capability. In this configuration several devices are
activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device
(see Figure 10), which builds a chain. The ends of the chain are connected with the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK, which is connected to the
SCLK line of each device in the chain.
device 1
SPI
device 2
SPI
device 3
SPI
SI
SO SI
SO SI
SO
MO
MI
MCS
MCLK
SPI_DasyChain.emf
Figure 10 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 16 SCLK cycles, the data transfer for one SPIDER - TLE7244SL has been
finished. In single chip configuration, the CS line must go high to make the device accept the transferred data. In
daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using multiple
devices in daisy chain, the number of bits must be correspond with the number of register bits. Figure 11 is
showing a example with 3 SPI devices, where #1 and #3 are 16 bit SPI and #2 has a 8 bit SPI. To get a successful
transmission, there have to be 2* 16 bit + 1* 8bit shifted through the devices. After that, the MCS line must go high.
Datasheet
20
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Serial Peripheral Interface (SPI)
SO device 3
SI device 3
SO device 2
SI device 2
SO device 1
SI device 1
MI
MO
MCS
MCLK
time
SPI_DasyChain2.emf
Figure 11 Data Transfer in Daisy Chain Configuration
8.3
SPI Protocol
The SPI protocol of the SPIDER - TLE7244SL provides two registers. The input register and the diagnosis
register. The diagnosis register contains eight pairs of diagnosis flags, the input register contains the input
multiplexer configuration. After power-on reset, all register bits are set to 1 and the device is in idle mode.
SI
Default: FFFFH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
Field
Bits
Type
Description
INn
(n = 8 - 1)
15:14,
13:12,
11:10,
9:8,
W
Input Register Channel n
00B Stand-by Mode:
Channel is switched off.
Diagnosis flags are cleared.
Diagnosis current is disabled.
7:6,
5:4,
01B Input Mode:
3:2,
Channel is switched according to signal at input pin.
Diagnosis current is enabled in OFF-state.
1:0
10B ON Mode:
Channel is switched on.
11B OFF Mode:
Channel is switched off.
Diagnosis current is enabled.
Note:If all channels are programmed to Standby, the device changes to power down status with minimum current
consumption (sleep mode).
Datasheet
21
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Serial Peripheral Interface (SPI)
SO
CS1)
TER OL8
Reset Value: 10000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D8
OL7
D7
OL6
D6
OL5
D5
OL4
D4
OL3
D3
OL2
D2
OL1
D1
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
Field
Bits
Type Description
TER
CS
R
R
R
Transmission Error
0
Previous transmission was successful (modulo 8 clocks received, minimum 16 bit).
Previous transmission failed or first transmission after reset.
1
OLn
(n = 8 - 1)
15,13,
11,9,7,
5, 3, 1
14,12,
10,8,6,
4, 2, 0
Open Load Flag of channel n
0
Normal operation.
Open load has occurred in OFF state.
1
Dn
(n = 8 - 1)
Diagnosis Flag of channel n
0
Normal operation.
Over load or over temperature switch off has occurred in ON state.
1
8.3.1
Timing Diagrams
tCS( lead)
tCS(lag)
tCS(td)
tSCLK(P)
tSCLK(L)
0.7Vcc
0.2Vcc
CS
SCLK
SI
tSCLK(H)
0.7Vcc
0.2Vcc
tSI(su)
tSI(h)
0.7Vcc
0.2Vcc
tSO(en)
tSO(v)
tSO(dis)
0.7Vcc
0.2Vcc
SO
SPI Timing.emf
Figure 12 Timing Diagram
Datasheet
22
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Serial Peripheral Interface (SPI)
8.4
SPI Characteristics
Note:Characteristics show the deviation of parameter at given supply voltage and junction temperature. Typical
values show the typical parameters expected from manufacturing.
Electrical Characteristics: Serial Peripheral Interface (SPI)
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 C to +150 C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Input Characteristics (CS, SCLK, SI)
8.4.1
8.4.2
L level of pin
0
–
0.2*
–
CS
VCS(L)
VSCLK(L)
VSI(L)
VDD
SCLK
SI
H level of pin
CS
SCLK
SI
0.4*
VDD
–
VDD
–
VCS(H)
VSCLK(H)
VSI(H)
8.4.3
8.4.4
L-input pull-up current through CS ICS(L)
H-input pull-up current through CS ICS(H)
3
3
17
15
40
40
µA
µA
VCS = 0 V
1)
VCS = 0.4*VDD
1)
8.4.5
L-input pull-down current through
pin
3
12
80
µA
VSCLK = 0.6 V
VSI = 0.6 V
ISCLK(L)
ISI(L)
SCLK
SI
8.4.6
H-input pull-down current through
10
40
80
µA
pin
SCLK
SI
ISCLK(H)
ISI(H)
VSCLK = VDD
VSI = VDD
Output Characteristics (SO)
8.4.7
8.4.8
L level output voltage
H level output voltage
VSO(L)
VSO(H)
0
–
–
0.6
VDD
V
ISO = -2 mA
ISO = 1.5 mA
VDD
-
0.4 V
8.4.9
Timings
Output tristate leakage current
ISO(OFF)
-10
–
10
µA
V
CS = VDD
1)
1)
1)
1)
1)
8.4.10 Serial clock frequency
8.4.11 Serial clock period
8.4.12 Serial clock high time
8.4.13 Serial clock low time
8.4.14 Enable lead time (falling CS to
rising SCLK)
8.4.15 Enable lag time (falling SCLK to
rising CS)
8.4.16 Transfer delay time (rising CS to
falling CS)
fSCLK
0
–
–
–
–
–
5
–
–
–
–
MHz
ns
ns
ns
ns
tSCLK(P)
tSCLK(H)
tSCLK(L)
tCS(lead)
200
50
50
250
1)
tCS(lag)
tCS(td)
250
250
20
–
–
–
–
–
–
ns
ns
ns
1)2)
1)
8.4.17 Data setup time (required time SI to tSI(su)
falling SCLK)
Datasheet
23
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Serial Peripheral Interface (SPI)
Electrical Characteristics: Serial Peripheral Interface (SPI)
All voltages with respect to ground, positive current flowing into pin
unless otherwise specified: VDD = 3.0 V to VDDA, VDDA= 4.5V to 5.5V, Tj = -40 C to +150 C
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
–
Typ.
–
Max.
8.4.18 Output enable time (falling CS to
SO valid)
8.4.19 Output disable time (rising CS to
SO tri-state)
tSO(en)
tSO(dis)
tSO(v)
200
200
100
ns
ns
ns
CL = 50 pF 1)
CL = 50 pF 1)
CL = 50 pF 1)
–
–
–
–
8.4.20 Output data valid time with
capacitive load
1) Not subject to production test, specified by design.
2) Diagnosis flag update needs the time specified in Chapter 7.1 to get valid information
Datasheet
24
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Application Information
9
Application Information
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 13 shows a simplified application circuit. VDD and VDDA need to be externally reverse polarity protected.
Vbat
+5V
100nF
VDDA
VDD
OUT1
OUT2
OUT3
OUT4
OUT5
KL15Relay
KL50Relay
Wiper Relay
IN1
IN2
IN3
IN4
Limp Home Circuit
Possibility to control OUT 1-
4 via Inputs IN1-4 during
malfunction of µC
Horn Relay
OUT6
OUT7
OUT8
VCC
GPIO
RST
low-side
gate control
µC
XC2000
GND
VDD
CS
SPI
Limp Home Signal
(eg WD out of SBC TLE 8264 G Hermes)
SCLK
SO
SPI
LHI
SI
GND
GND
TLE7244SL.emf
Figure 13 Application Diagram
Note:This is a very simplified example of an application circuit. The function must be verified in the real application.
For further information you may contact http://www.infineon.com/spider
Datasheet
25
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Package Outlines
10
Package Outlines
0.35 x 45˚
1)
±0.1
C
3.9
8˚ MAX.
8˚ MAX.
0˚...8˚
+0.06
0.19
0.1
B
B
0.65
0˚...8˚
0.17
0.64±0.25
0.2
Seating Plane
2)
±0.05
±0.2
0.25
6
M
M
C
C A B 24x
24
13
12
1
A
1)
±0.1
8.65
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-5, -6
Figure 14 PG-SSOP-24-7 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Please specify the package needed (e.g. green package) when placing an order
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
Datasheet
26
Rev. 1.3, 2011-10-21
SPI Driver for Enhanced Relay Control
SPIDER - TLE7244SL
Revision History
11
Revision History
Version
Rev. 1.3
Rev. 1.2
Rev. 1.1
Date
Changes
Marking changed to TLE7244SL_A
parameter 4.1.6 on page 9, condition and max limit values changed
new parameter 4.2.6 on page 10 “Analog Supply Turn-ON time” added
5.1 Power Supply on page 11: change from “device is in standby mode” to “device
is in idle mode” after power-on reset (as already described on page 12, 16 and 21)
2011-10-21
2011-05-23
2011-03-24
Rev. 1.0
2009-09-30
released Datasheet
Datasheet
27
Rev. 1.3, 2011-10-21
Edition 2011-10-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
相关型号：
TLE7245G
Buffer/Inverter Based Peripheral Driver, 1A, PDSO24, PLASTIC, SOP-24Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250
High Speed CAN-TransceiverWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250G
High Speed CAN TransceiverWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250GVIO
High Speed CAN TransceiverWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250GVIOXUMA2
Interface Circuit, PDSO8, DSO-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250GXUMA1
Interface Circuit, PDSO8, GREEN, PLASTIC, SOP-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250LE
Material Content Data SheetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250LEXUMA1
Interface Circuit, PDSO8, TSON-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250LE_15
Material Content Data SheetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250SJ
Material Content Data SheetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250SJXUMA1
Interface Circuit, PDSO8, DSO-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
TLE7250SJ_15
Material Content Data SheetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
INFINEON
©2020 ICPDF网 联系我们和版权申明